CYRUSTEK ES51993

ES51993
11,000 Counts ADC
Features
• Max. 11,000 counts resolution
• Conversion rate selectable by MPU
command: 1.6/s Æ 128/s
• Input signal full scale: 110mV
• 50/60Hz line noise rejection selectable by
MPU command
• Low battery detection
• Multiple input channels for ADC
• 3-wire serial bus and EOC signal for MPU
I/O port
Description
ES51993 is an 11000-count dual-slope analogto-digital converter (ADC) with peak hold
function. The conversion rate and buzzer
frequency can be selected or decided by an
external microprocessor. The conversion rate
can be varied from 1.6 time/sec to 128
times/sec
under
4MHz/12MHz
crystal
oscillation clock. Besides, ES51993 also
provides multi-channel input, low battery
detection, power-down mode, 50/60Hz line
noise rejection selection, and I/O port level
selection for flexible design.
• -3V power operation with internal charge
pumping circuit
• MPU I/O power level selectable by external
control pin
• Support Peak Hold with calibration mode
• Zero calibration for eliminating offset error
• On-chip buzzer driving and frequency
selectable by MPU command
• Support sleep mode by external CS(chipselect) pin
Application
Clamp meter
Thermometer
Portable instrumentation
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ES51993
11,000 Counts ADC
Pin Assignment
CAZ
CINT
IO_control
CS
V+
DGND
LBAT
AGND
V-
V12
LQFP-32L
CREF+
1 32 31 30 29 28 27 26 25 24
2
23
3
22
C+
COSC1
CREFREF+
4
5
21
20
OSC2
uP_VCC
REFBUF
RAZ
6
19
7
8
18
9 10 11 12 13 14 15 16 17
BUZOUT
EOC
SCLK
2
VINSDATA
VIN2+
VIN1+
PMIN
VIN+
PMAX
PHIN
ES51993
06/09/20
ES51993
11,000 Counts ADC
Pin Description
Pin No
Symbol
Type
1
2
3
4
5
6
7
8
CAZ
CINT
CREF+
CREFREF+
REFBUF
RAZ
I
O
I/O
I/O
I
I
O
O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PHin
PMAX
PMIN
VIN+
VIN1+
VIN2+
VINSDATA
SCLK
EOC
BUZOUT
uP_VCC
OSC2
OSC1
CC+
CS
I/O_control
LBAT
28
29
30
31
32
DGND
V+
VAGND
V12
Description
Auto-zero capacitor connection.
Integrator output. Connect to integral capacitor
Positive connection for reference capacitor.
Negative connection for reference capacitor.
Differential reference high voltage input.
Differential reference low voltage input.
Buffer output pin. Connect to integral resistor
Buffer output pin in high-speed mode. Connect to high-speed integral
resistor.
I
Pick hold signal input which is reference to AGND
O Minimum peak hold output capacitor connection.
O Maximum peak hold output capacitor connection.
I
Analog differential high signal input.
I
Analog signal high input1
I
Analog signal high input2
I
Analog differential low signal input.
I/O Serial data I/O pin. Nch open-drain output.
I
Serial clock input pin.
O An indicator for ADC conversion ending.
O Buzzer frequency output
I
MPU I/O port power level selection
O Crystal oscillation connection
I
Crystal oscillation connection
O Negative capacitor connection for on-chip DC-DC converter.
O Positive capacitor connection for on-chip DC-DC converter.
I
Chip select input pin. Pull to Low to enter power down mode.
I
MPU I/O port ground level selection
I
Low battery configuration. If 3V battery is used, connect it to AGND.
The default low-battery threshold voltage is –2.3V. If 9V or other
battery voltage is used, the low battery annunciator is displayed when
the voltage of this pin is less than V12
G Digital ground
O/P Output of on-chip DC-DC converter.
P Negative supply voltage. Connecting to 3V battery negative terminal.
G Analog ground
O Output of band-gap voltage reference. Typically –1.23V
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11,000 Counts ADC
Function description
1. Dual Slope A/D-Four Phases Timing
ES51993 is a dual-slope analog-to-digital converter (ADC). Figure 1 is a structure
of dual-slope integrator. Its measurement cycle has two distinct phases: input signal
integration (INT) phase and reference voltage integration (DINT) phase.
In INT phase, the input signal is integrated for a fixed time period, then A/D
enters DINT phase in which an opposite polarity constant reference voltage is
integrated until the integrator output voltage becomes to zero. Since both the time
period for input signal integration and the amount of reference voltage are fixed, thus
the de-integration time is proportional to the input signal. Hence, we can define the
mathematical equation about input signal, reference voltage integration (see Figure 1.):
TINT
1
1
V IN (t )dt =
× V REF × TDINT
∫
Buf × C int 0
Buf × C int
where, V IN (t ) = input signal
V REF = reference voltage
T INT = integration time (fixed)
TDINT = de-integration time (proportional to V IN (t ) )
Cint
input
signal
Buf
reference
voltage
integrator
output
RAZ
BufX10
RAZ
integrator output
integrator output
input signal > 0
integration
time
different
input
input signal < 0
different
input
fixed slope
fixed slope
Fixed
Variable
integration deintegration
time
time
Fixed
Variable
integration deintegration
time
time
integration
time
Figure 1. the structure of dual-slope integrator and its output waveform.
If V IN (t ) is a constant, we can rewrite above equation:
TDINT =
T INT
× V IN
V REF
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ES51993
11,000 Counts ADC
Besides the INT phase and DINT phase, ES51993 exploits auto zero (AZ) phase
and zero integration (ZI) phase to achieve accurate measurement. In AZ phase, the
system offset is stored. The offset error will be eliminated in DINT phase. Thus a
higher accuracy could be obtained. In ZI phase, the internal status will be recovered
quickly to that of zero input. Thus the succeeding measurements won’t be disturbed by
current measurement especially in case of overload.
As mentioned above, the measurement cycle of ES51993 contains four phases:
(1) auto zero phase (AZ)
(2) input signal integration phase (INT)
(3) reference voltage integration phase (DINT)
(4) zero integration phase (ZI)
The time ratios of these four phases, AZ, INT, DINT and ZI to the entire
measurement cycle are 8.8%, 32%, 35.2% and 24% respectively. However the actual
duration of each phase depends on conversion rate. An example is shown in the table
below. A user can easily deduce other cases based on the table.
Voltage:
CR (times/sec)
ZI (ms)
8
30
AZ (ms) INT (ms) DINT (ms)
11
40
44
Note: reference voltage = -100 mV.
Voltge+PEAK:
CR (times/sec)
ZI (ms)
8
30
AZ (ms) INT (ms) DINT (ms)
11
40
60
Note: reference voltage = -100 mV.
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ES51993
11,000 Counts ADC
2. Component Value Selection for ADC
For various application requirements on conversion rate and input full range, we
suggest nominal values for external components of ADC in Figure 1 to obtain better
performance. Under default condition with operating clock = 12 MHz:
(1) conversion rate = 8 times/sec
(2) reference voltage = -100 mV
(3) input signal full scale = 110 mV (sensitivity = 10 uV)
We suggest that Cint = 68 nF, Buf = 56 kΩ
If a user selects a different conversion rate rather than default, the integration
capacitor Cint value must be changed according to the following rule for better
performance:
Cint × (conversion rate) = (68 nF) × (8 times/sec).
A smaller Cint reduces the input full range. However a larger Cint might have
weaker noise immunity than the suggested one.
A user could enlarge the input full range by changing reference voltage (Vref) and
the amount of integration resistor (Buf). For example, if Vref & Buf are enlarged as
twice than the default values then the input full range becomes 220 mV. The input full
range can be enlarged up to 1.1V (10 times than the default case). We list general rules
in below which might be helpful in determining component values.
Buf / (reference voltage) = 56 kΩ / (-100 mV)
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ES51993
11,000 Counts ADC
3. Multi Channel Input
ES51993 provides VIN+, VIN1+, VIN2+ and Vin- pins to achieve the multi channel
input (multiplexer) feature. Because ES51993 is a single core A-to-D converter, it can
only process one pack of data per conversion period. Although it has four input pins, it
would take only one pair as input channel from the four pins. The actual input channel
is determined by the bits CH1/CH0 of STATUS Byte1 as the following table:
Input Channel CH1 CH0
ch1
0
0
ch2
0
1
ch3
1
0
ch4
1
1
High Input
VIN+
VIN1+
VIN2+
VIN2+
Low Input
VINVINVINVIN1+
ES51993 also configures an input channel rotation (polling) feature. Setting the ROT
bit of STATUS Byte2 to high can activate the rotation feature. In the rotation mode, the
actual input channel will be changed by ES51993 sequentially and automatically. The
rotation feature has two types, one is for three input channel rotation with the same low
input, another one is for two independent differential channel rotation. The following
table presents the configuration of the rotation type.
Rotation Type Table:
ROT
CH1,CH0
0,0
0,1
H
1,0
1,1
L
-
Rotation Type
ch1 → ch2 → ch3 → ch1 …
ch1 → ch4 → ch1 …
Not Rotating
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ES51993
11,000 Counts ADC
4. Special function
4.1 Peak Hold
ES51993 provide a Peak Hold function to capture the REAL peak value for voltage or
current measurement mode. In a case of a 1V sine wave input voltage, the Peak Hold
function gets a PMAX value of 1.414V and PMIN value of –1.414V. Set the bit PEAK
of STATUS byte3 to high to force the ES51993 enter PEAK mode.. In the PEAK mode,
ES51993 takes high input from PHin and low input from AGND. Peak Hold function is
divided into two parts of peak maximum and peak minimum conversion. ES51993
performs peak maximum and peak minimum conversion by turns, not at the same time.
The bit PMAX and PMIN of STATUS Byte2 present which type the peak value is.
4.2 Peak Calibration
In PEAK mode, the offset voltage of internal OP Amps will cause an error. To obtain a
more accurate value, this offset effect must be canceled. ES51993 provides the Peak
Calibration feature to remove the influence on accuracy by internal offset voltage. Set
the bit PCAL of STATUS Byte2 to high to enter Peak Calibration mode. In this mode,
ES51993 will output the calibration value of peak maximum and minimum conversion
by turns. The calibration value is the error rise from offset voltage, and it muse be
recorded. In PEAK mode, the peak value must minus the calibration value to remove
the error.
Note:
1. After entering Peak or PCAL mode, it is recommended to leave the Peak or PCAL
mode first. Then wait one conversion time delay before change mode to PCAL or
Peak mode, respectively. The time delay is necessary for normalizing the charge of
PMAX/PMIN capacitor.
2.
When buzzer control bit is active, the Peak & PCAL mode are not allowed.
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11,000 Counts ADC
4.3 Zero and RZero Calibration
The Zero and RZero calibration are designed for removing the error rise from the
propagation delay of internal component. In Zero or RZero calibration mode, ES51993
outputs a calibration value. The normal measurement value must minus the calibration
value to cancel the error and obtain a more accurate value. The following block
diagram performs the difference between basic structures of normal mode, Zero
calibration and RZero Calibration. We suggest users to do zero-calibration in most
applications.
V IN +
IN +
(a ) N o rm a l m o d e
D u a l S lo p e
ADC
IN -
V IN -
IN +
V IN +
D u a l S lo p e
ADC
(b ) Z ero m o d e
IN -
V IN -
IN +
V IN +
D u a l S lo p e
ADC
(c ) R Z ero m o d e
V IN -
IN -
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11,000 Counts ADC
4.4 Buzzer Setup
When the bit BUZ of ID Byte is set to “H”, the BUZOUT will output a square signal of
MPU I/O swing level to drive a external buzzer. The buzzer frequency is determined by
the bits B0/B1/B2 of STATUS Byte3. The configuration of buzzer frequency is listed at
the following table.
B2/B1/B0
BUZout (kHz)
111
110
101
100
011
010
001
000
4.00
3.33
3.08
2.67
2.22
2.00
1.33
1.00
4.5 Low Battery Detection
In a case of 3V battery power, the pin LBAT must be shorted to AGND. And the system
will have low battery detection level about 2.3V. In another case of 9V or other battery
power, the low battery detection happens when the voltage of LBAT is less than –1.23V
below GND. And the bit LBAT of STATUS Byte3 will be set to high. A recommended
application is shown as following:
Low battery test (9V)
9V
BA
680K
LBAT
TT
230K
0.1u AGND
V-
0V
The low battery detection level is around 7V
4.6 Sleep Mode
When the pin CS is connected to V- or GND (depended on I/O_control level), the
ES51993 will enter sleep mode. In Sleep mode, the chip draws a little supply current. It
could extend the battery life. To leave sleep mode or stay in normal mode, the pin CS
must be connected to AGND or floating.
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11,000 Counts ADC
5. MPU I/O functional definition
Write command:
ID byte, Status byte1, Status byte2, Status byte3
START BIT
1
1
0 0 0
1
B
U
Z 0
A
C
K
A
C
K
A
C
K
A
C
K
WRITE
STOP BIT
Read command:
ID byte, Status byte1, Status byte2, Status byte3, Data byte1, Data byte2
START BIT
1
1
0 0 0
B
U
1 Z 1
A
C
K
A
C
K
A
C
K
A
C
K
READ
A
C
K
N
A
K
STOP BIT
ID byte:
1
1
0
Status byte1:
CH0
CH1
C0
Status byte2:
S60 RZERO ZERO
Status byte3:
PEAK PCAL
B0
Data byte1:
D0
D1
D2
Data byte2:
D8
D9
D10
0
0
1
BUZ
R/W
C1
C2
SIGN
SEL4M
X
ROT
PMAX
PMIN
X
X
B1
B2
LBAT
X
X
D3
D4
D5
D6
D7
D11
D12
D13
X
X
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11,000 Counts ADC
R/W: set to “H” is in read mode, set to “L” is in write mode
CH1/CH0: ADC input channel selection, the default is [00].
Code
VIN(+)
VIN(-)
00
VIN0 channel
VIN- channel
01
VIN1 channel
VIN- channel
10
VIN2 channel
VIN- channel
11
VIN2 channel
VIN1 channel
C2/C1/C0/S60: Conversion rate selection, the default is [0000]
S60
C2/C1/C0
L
H
101
128/s
128/s
100
96/s
96/s
011
64/s
76.8/s
010
32/s
38.4/s
001
16/s!
19.2/s*
000
8/s!
9.6/s*
!*
110
3.2/s
3.84/s*
111
1.6/s!*
1.92/s*
Crystal: 12MHz
!: 50Hz line noise rejection, *: 60Hz line noise rejection
SEL4M: “H” is XTAL is 4MHz version, “L” is default 12MHz XTAL
S60
C2/C1/C0
X
101
128/s
100
64/s
011
64/s
010
32/s
001
16/s!
000
8/s!
110
3.2/s!*
111
1.6/s!*
Crystal :4MHz
SIGN: “H” is negative, “L” is positive
PMAX: “H” is maximum peak value, the default is “L”
PMIN: “H” is minimum peak value, the default is “L”
LBAT: “H” is low battery detection flag active, the default is “L”
PEAK: “H” is peak hold function turn on, the default is “L”
PCAL: “H” is peak hold function calibration mode is active, the default is “L”
RZERO: “H” is RZero calibration mode “ON”, the default is “L”
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11,000 Counts ADC
ZERO: “H” is Zero calibration mode “ON”, the default is “L”
ROT: Set to ”H” to enable multi channel rotating feature
B2/B1/B0: Buzzer frequency selection (independent with conversion rate)
BUZ: “H” is buzzer turn on and “L” is turn off, the default is turn off.
Buzzer ON
START BIT
1
1
0 0 0
1
1
A
C
K
STOP BIT
Buzzer OFF
START BIT
1
1
0 0 0
1
0
A
C
K
STOP BIT
D13-D0: ADC output data according channel multiplex [CH1/CH0]. Binary code
format.
6. Power and I/O output level selection
Power
z Charge pump output for positive supply voltage(V+)
z External DC source to V+ is available by floating the charge pump capacitor
I/O output level selectable
z uP_VCC provided by external DC source (the same high level with MPU)
z A control pin (I/O_control) selects the low level to –3V(V-) or 0V(DGND)
I/O level
uP_VCC I/O_control
Example
H
L
3
H
+3V
0V
Ex.1
3
L
+3V
-3V
Ex.2
0
L
0V
-3V
Ex.3
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ES51993
11,000 Counts ADC
ES5199X
V+
C-
uP_VCC
+3V
C+
I/O_control
SCLK
SDATA
EOC
BUZOUT
CS
+3V
0V
GND
V-
Ex.1
-3V
ES5199X
C-
V+
uP_VCC
+3V
C+
I/O_control
SCLK
SDATA
EOC
BUZOUT
CS
+3V
-3V
GND
V-
Ex.2
-3V
ES5199X
C-
V+
uP_VCC
C+
I/O_control
SCLK
SDATA
EOC
BUZOUT
CS
0V
-3V
GND
V-
Ex.3
-3V
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ES51993
11,000 Counts ADC
Absolute Maximum Ratings
Characteristic
Supply Voltage (V- to AGND)
Analog Input Voltage
V+
AGND/DGND
Digital Input
Power Dissipation. Flat Package
Operating Temperature
Storage Temperature
Rating
-3.6V
V- -0.6 to V+ +0.6
V+ ≥ (AGND/DGND+0.5V)
AGND/DGND ≥ (V- -0.5V)
V- -0.6 to DGND +0.6 or V+ +0.6
500mW
0℃ to 70℃
-25℃ to 125℃
DC Electrical Characteristics
TA=25℃, VCM = 0V, V-=-3V
Parameter
Power supply
Operating supply current
Conversion rate = 8/sec.
Voltage roll-over error
Voltage nonlinearity
Symbol
Test Condition
VIDD
Normal operation
(XTAL=12MHz)
ISS
In sleep mode
REV
NLV
Input Leakage
Low battery flag voltage
Internal pull-high to uP_Vcc current
Internal pull-low to V- current
Zero input reading
Reference voltage and open circuit
voltage for 110Ω measurement
VREF
Reference voltage temperature
coefficient
TCRF
Minimum pulse width for Peak
Hold feature
TPW
Best case straight
line
V- to AGND
CS (uP_Vcc=3V)
CS(uP_Vcc=0V)
I/O_control
(V-=-3V)
10MΩ input resistor
zero cal. by MPU
100KΩ resistor
between VRH and
AGND
100KΩ resister
Between VRH
0℃<TA<70℃
Min.
-3.3
Typ.
-3.0
Max
-2.5
Units
V
—
2.0
2.2
mA
—
2.5
5
µA
—
—
±0.05
%F.S1
—
—
±0.05
%F.S
1
-2.3
5
1.5
10
-2.2
pA
V
-2.4
uA
1.5
uA
-000
000
+000
counts
-1.33
-1.23
-1.13
V
—
50
—
ppm/℃
100
µs
Note:
1.Full Scale
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ES51993
11,000 Counts ADC
AC Electrical Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
SCLK clock frequency
SCLK clock time “L”
SLCK clock time “H”
SDATA output delay time
SDATA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCLK/SDATA rising time
SCLK/SDATA falling time
Bus release time
EOC setup time in read mode
EOC hold time in read mode
fSCLK
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSU.EOC
tHD.EOC
4.7
4.0
0.1
100
4.7
4.0
200
0
4.7
4.7
0
0
-
100
3.5
1.0
0.3
-
kHz
-
-
us
ns
us
ns
us
ns
ns
I/O timing diagram
SCLK
SDATA IN
SDATA OUT
Read mode EOC timing diagram
EOC
t
t
S U .E O C
H D .E O C
SD A TA
SCLK
S tart co n d itio n
S to p co n d itio n
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ES51993
11,000 Counts ADC
Application example
7.5V ZD
10uF
+
5.6V ZD
+
*2
MPU power
*1
MPU
*3
10uF
0.1uF
V- or DGND
470 nF
32
CAZ
31
30
29
28
27
I/O
port
26
25
C+
1
24
2
23
CINT
**68nF
91k
CREF+
22
ES51993
CREFREF+
5
REF-
OSC2
12M or 4MHz
21
uP_VCC
20
BUZOUT
6
19
BUF
*4
EOC
7
18
8
17
RAZ
SCLK
15
10 nF 10 nF
16
5.6V ZD
15k
V-
SDATA
VIN-
14
VIN2+
13
VIN1+
12
VIN+
PHIN
11
PMIN
10
PMAX
9
1 uF
***R
OSC1
4
**56k
470nF
C-
3
220 nF
VSS
CS
IO_control
LBAT
DGND
V+
V-
V12
AGND
0.1uF
10k VR
VDD
Input
100k
**10nF
Note:
Zener diodes in above circuit are used for IC protection, so MUST be soldered on
PCB first.
*1*2*3*4: Depend on power design
** Depends on conversion rates setting: V-= -3.0V
(a)Conversion rate
128/s
96/s
76.8/s
64/s
38.4/s
32/s
19.2/s
(b)CINT(uF)
0.01
0.01
0.01
0.022
0.022
0.033
0.033
(c)RBUF(kΩ)
22
30
39
22
36
27
47
(a)Conversion rate
16/s
9.6/s
8/s
3.84/s
3.2/s
1.92/s
1.6/s
(b)CINT(uF)
0.068
0.047
0.068
0.1
0.1
0.22
0.22
(c)RBUF(kΩ)
27
68
56
82
91
68
91
*** R=10~22MΩ resistor is optional
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ES51993
11,000 Counts ADC
Product Outline: LQFP-32
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