HOLTEK HT82V46

HT82V46
16-Bit, 45MSPS, 3-Channel
CCD/CIS Analog Signal Processor
Features
General Description
• Operating voltage: 3.3V
The HT82V46 is a complete analog signal processor
for CCD imaging applications. It features a 3-channel
architecture designed to sample and condition the
outputs of tri-linear color CCD arrays. Each channel
consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC and Programmable Gain
Amplifier (PGA), and a high performance 16-bit A/
D converter. The CDS amplifiers may be disabled for
use with sensors such as Contact Image Sensors (CIS)
and CMOS active pixel sensors, which do not require
CDS. The 16-bit digital output is available in 8-bit
wide multiplexed format. The internal registers are
programmed through a 4-wire serial interface, which
provides gain, offset and operating mode adjustments.
The HT82V46 operates from a single 3.3V power
supply, typically consumes 528mW of power.
• Guaranteed won’t miss codes
• 9-bit programmable gain
• Correlated Double Sampling
• 8-bit programmable offset
• Programmable clamp voltage
• 8-bit wide multiplexed data output format
• 8-bit only output mode
• 4-bit multiplexed nibble mode
• Internal voltage reference
• Programmable 4-wire serial interface
• Maximum Conversation rate up to 45 MSPS
• 28-pin SSOP package
Applications
• Flatbed document scanners
• Film scanners
• Digital color copiers
• Multifunction peripherals
Block Diagram
CDS1
CDS2
CLP
VINR
VING
VINB
ADCK
C1S C2S
RLC
CDS
RLC
CDS
RLC
CDS
+
+
Offset
DAC
RLC
DAC
AVDD
AVSS
PGA
+
PGA
+
PGA
+
OEB
3:1
9
Red
Green
Blue
8
Red
Green
Blue
2
1
8
OD[0:6]
PGA
REG
SCK
Serial
Control
Interface
Offset
REG
SEN
SDI
Setup
REG1 ~ REG6
DVDD
AVSS
16:8:4
MUX
OD[7]/SDO
DAC
4
16
16-bit
ADC
MUX
Offset Offset
DAC
CML
REFB
Bandgap
Reference
Timing Control
+
VRLC/VBIAS
Rev. 1.10
REFT
DVDD
DVSS
November 24, 2011
HT82V46
Pin Assignment
V IN R
1
2 8
V IN G
A V S S
2
2 7
V IN B
D V D D
3
2 6
V R L C /V B IA S
O E B
4
2 5
C M L
C D S 2
5
2 4
R E F T
C D S 1
6
2 3
R E F B
A D C K
7
2 2
A V S S
D V S S
8
2 1
A V D D
S E N
9
2 0
O D 7 /S D O
1 0
1 9
O D 6
1 1
1 8
O D 5
S C K
1 2
1 7
O D 4
O D 0
1 3
1 6
O D 3
O D 1
1 4
1 5
O D 2
D V D D
S D I
Pin Description
Pin Name
I/O
VINR
AI
Analog Input, Red Channel
Description
AVSS
P
Analog Ground
DVDD
P
Digital Driver Power
OEB
DI
Output Enable, Active Low
CDS2
DI
CDS Video Level Sampling Clock
CDS1
DI
CDS Reference Level Sampling Clock
ADCK
DI
ADC Sampling Clock
DVSS
P
Digital Driver Ground
SEN
DI
Serial Interface Enable, Active High
DVDD
P
Digital Driver Power
SDI
DI
Serial Data Input for Serial Control Interface
SCK
DI
Clock Input for Serial Control Interface
OD0~OD6
DO
Digital Data Output
OD7/SDO
DO
When register bit OEB= 0, OPD= 0 and SEN has been pulsed high, this pin
use as Serial Data Output for Serial Control Interface. Otherwise, this pin use
as Digital Data Output.
AVDD
P
Analog Supply
Analog Ground
AVSS
P
REFB
AO
ADC Bottom Reference Voltage Decoupling
REFT
AO
ADC Top Reference Voltage Decoupling
CML
AO
Internal Bias Level Decoupling
VRLC/VBIAS
AIO
Selectable analog output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
VING
AI
Analog Input, Green Channel
VINB
AI
Analog Input , Blue Channel
TYPE: AI= Analog Input; AO= Analog Output; AIO=Analog In/out, DI= Digital Input; DO= Digital Output; P= Power.
Rev. 1.10
2
November 24, 2011
HT82V46
Absolute Maximum Ratings
Supply Voltage ������������������������������������������������������������������������������������������������������������������������� VSS -0.3V to VSS +4.3V
Input Voltage ��������������������������������������������������������������������������������������������������������������������������� VSS -0.3V to VDD +0.3V
Storage Temperature ��������������������������������������������������������������������������������������������������������������������������� -50°C to 125°C
Operating Temperature �����������������������������������������������������������������������������������������������������������������������������0°C to 70°C
Analogue Supply Power ��������������������������������������������������������������������������������������������������������������������������3.0V to 3.6V
Digital Supply Power �������������������������������������������������������������������������������������������������������������������������������3.0V to 3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
D.C. Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Power Supply
AVDD
Analogue Supply Power
―
3.0
3.3
3.6
V
DVDD
Digital Supply Power
―
3.0
3.3
3.6
V
Digital Inputs
VIH
High Level Input Voltage
―
0.7*DVDD
―
―
V
VIL
Low Level Input Voltage
―
―
―
0.2*DVDD
V
IIH
High Level Input Current
―
―
―
1
μA
IIL
Low Level Input Current
―
―
―
1
μA
CI
Input Capacitance
―
―
5
―
pF
Digital Outputs
VOH
High Level Output Voltage
IOH= 1mA
DVDD-0.5
―
―
V
VOL
Low Level Output Voltage
IOL= 1mA
―
―
0.5
V
IOZ
High Impedance Output Current
―
―
―
1
μA
―
0.7*DVDD
―
―
V
Digital I/O Pins
VIH
Applied High Level Input Voltage
VIL
Applied Low Level Input Voltage
VOH
High Level Output Voltage
IOH=1mA
VOL
Low Level Output Voltage
IOL=1mA
IIL
Low Level Input Current
―
IIH
High Level Input Current
IOZ
High Impedance Output Current
Rev. 1.10
―
3
―
―
0.2*DVDD
V
DVDD-0.5
―
―
V
―
―
0.5
V
―
―
1
μA
―
―
―
1
μA
―
―
―
1
μA
November 24, 2011
HT82V46
A.C. Characteristics
AVDD=DVDD=3.3V, AVSS=DVSS=0V, Ta=25°C, 3-channel mode, ADCK=45MHz unless otherwise stated.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
―
MSPS
Overall system specification (including 16-bit ADC, PGA, Offset and CDS functions)
Maximum Conversion Rate
Full-scale Input Voltage Range
(See Note 1)
Full-scale Input Voltage Range
(See Note 1)
VIN
―
LOWREF= 0,
GMAX=7.5 typ.
LOWREF= 0,
GMIN=0.65 typ.
LOWREF= 0,
GMAX=7.5 typ.
LOWREF= 0,
GMIN=0.65 typ.
Input Signal Limits (See Note 2)
―
―
45
0.25
―
VP-P
―
3.03
VP-P
0.15
―
VP-P
―
1.82
VP-P
AVSS-0.3
―
AVDD+0.3
V
Full-scale Transition Error
Gain=0dB;
PGA[8:0]=1A(hex)
―
30
―
mV
Zero-scale Transition Error
Gain=0dB;
PGA[8:0]=1A(hex)
―
30
―
mV
DNL
Differential Non-linearity
―
―
2
―
LSB
INL
Integral Non-linearity
―
―
50
―
LSB
Channel to Channel Gain Matching
―
―
1.5
―
%
Total Output Noise
Min Gain
Max Gain
―
30
300
―
LSB rms
LSB rms
References
VRT
Upper Reference Voltage
VRB
Lower Reference Voltage
CML
Input Return Bias Voltage
VRTB
Diff. Reference Voltage
(VRT - VRB)
LOWREF=0
LOWREF=1
LOWREF=0
LOWREF=1
―
LOWREF=0
LOWREF=1
1.95
0.95
―
0.90
2.05
1.85
1.05
1.25
1.5
1.0
0.6
2.25
1.25
―
1.10
V
V
V
V
V
V
V
RLC DAC (Reset-Level Clamp D/A Converter)
Resolution
VCSTEP
VCBOT
Step Size
Output Voltage at Code 0h
―
CDACRNG=0
CDACRNG=1
CDACRNG=0
CDACRNG=1
CDACRNG=0
―
―
―
0.110
0.4
0.4
3.00
―
―
―
V/step
V
V
V
Output Voltage at Code Fh
DNL
Differential Non-linearity
―
-0.5
―
+0.5
LSB
INL
Integral Non-linearity
―
―
+/-1
―
LSB
Resolution
―
―
8
―
bits
Step Size
―
―
2.04
―
mV/step
2.05
―
bits
V/step
VCTOP
CDACRNG=1
―
4
0.173
V
Offset DAC
Output Voltage
Rev. 1.10
Code 00(hex)
Code FF(hex)
4
―
-260
+260
―
mV
mV
November 24, 2011
HT82V46
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Resolution
―
―
9
―
bits
Gain Equation
―
GMAX
Max Gain, Each Channel
―
―
7.5
―
V/V
GMIN
Min Gain, Each Channel
―
―
0.65
―
V/V
Channel Matching
―
―
1
5
%
Resolution
―
―
16
―
bits
Speed
―
―
45
―
MSPS
Programmable Gain Amplifier
0.66 + PGA[8:0] * 7.34 / 511
V/V
A/D Converter
LOWREF=0
Full-scale Input Range
2*(VRT - VRB)
LOWREF=1
―
2.0
1.2
―
V
V
Supply Currents
Total Supply Current
―
―
160
―
mA
Analogue Supply Current
―
―
130
―
mA
Digital Supply Current
―
―
30
―
mA
Power Down Mode
―
―
130
―
μA
Note: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC fullscale input range.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
Timing Specification
AVDD=DVDD=3.3V, AVSS=DVSS=0V, TA=25°C, ADCK=45MHz unless otherwise stated.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Clock Parameter
tADC
ADCK Period
―
22
―
―
ns
tADH
ADCK High Period
―
10
11
―
ns
tADL
ADCK Low Period
―
10
11
―
ns
tC1
CDS1 Pulse High
―
5
―
―
ns
tC2
CDS2 Pulse High
―
5
―
―
ns
tC1FC2R
CDS1 Falling to CDS2 Rising
―
0
―
―
ns
tADFC2R
ADCK Falling to CDS2 Rising
―
4
―
―
ns
tADRC2R
ADCK Rising to CDS2 Rising
―
2.5
―
―
ns
tADFC2F
ADCK Falling to CDS2 Falling
―
4
―
―
ns
2
tC2FADR
CDS2 Falling to ADCK Rising
―
1
―
―
ns
tADFC1R
1st ADCK Falling after CDS2
Falling to CDS1 Rising
―
1
―
―
ns
tPR3
3-channel Mode Pixel Rate
―
66
―
―
ns
tPR2
2-channel Mode Pixel Rate
―
44
―
―
ns
tPR1
1-channel Mode Pixel Rate
―
22
―
―
ns
tOD
Output Propagation Delay
―
―
8
12
ns
LAT
Output Latency. From 1st ADCK Rising
Edge after CDS2 Falling to Data Output
―
ADCK
periods
Rev. 1.10
―
5
―
7
November 24, 2011
HT82V46
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Serial Control Interface
tSCK
SCK Period
―
83.3
―
―
ns
tSCKH
SCK High
―
37.5
―
―
ns
tSCKL
SCK Low
―
37.5
―
―
ns
tSDIS
SDI Set-up Time
―
6
―
―
ns
tSDIH
SDI Hold Time
―
6
―
―
ns
tCKFENR
SCK Falling to SEN Rising
―
12
―
―
ns
tENFCKR
SEN Falling to SCK Rising
―
12
―
―
ns
tSEN
SEN Pulse Width
―
60
―
―
ns
tENFSD7
SEN Falling to OD7/SDO Output the
D7 of Register Data
―
―
―
30
ns
tCKFSD6
SCK Falling to OD7/SDO Output the
D6 of Register Data
―
―
―
30
ns
tCKFOD7
SCK Falling to OD7/SDO Output OD7
―
―
―
30
ns
Note: 1. Parameters are measured at 50% of the rising/falling edge.
2. In 1-channel mode, if the CDS2 falling edge is placed more than 3ns before the rising edge of ADCK, the
output amplitude of the HT82V46 will decrease.
Function Description
Power Management
The device default is fully enabled. The Register Bit
EN allows the device to be fully powered down when
set low. Individual blocks can be powered down using
the bits in Setup Register 5. When in 1CH or 2CH
mode the unused input channels are automatically
disabled to reduce power consumption.
Introduction
The HT82V46 can sample up to three inputs, namely
VINR, VING and VINB, simultaneously. The device
then processes the sampled video signal with respect
to the video reset level or an internally/externally
generated reference level for signal processing. Each
processing channel consists of an Input Sampling
block with optional Reset Level Clamping (RLC)
and Correlated Double Sampling (CDS), an 8-bit
programmable offset DAC and a 9-bit Programmable
Gain Amplifier (PGA). The ADC then converts each
resulting analogue signal to a 16-bit digital word.
The digital output from the ADC is presented on an
8-bit wide bus. On-chip control registers determine
the configuration of the device, including the offsets
and gains applied on each channel. These registers are
programmable via a serial interface.
References
The ADC reference voltages are derived from an
internal bandgap reference, and buffered to pins
REFT and REFB, where they must be decoupled to
ground. Pin CML is driven by a similar buffer, and
also requires decoupling. The output buffer from the
RLCDAC also requires decoupling at pin VRLC/
VBIAS.
CDS/Non-CDS Processing
For CCD type input signals, containing a fixed
reference level, the signal may be processed using
Correlated Double Sampling (CDS), which will
remove pixel-by-pixel common mode noise. With
CDS processing the input waveform is sampled at
two different points in time for each pixel, once
during the reference level and once during the video
level. To sample using CDS, register bit CDS must
be set to 1 (default). This causes the signal reference
to come from the video reference level as shown in
Figure 1. The video sample is always taken on the
falling edge of the input CDS2 signal (C2S). In CDSmode the reference level is sampled on the falling
Internal Power-On-Reset (POR) Circuit
Internal POR Circuit is powered by AVDD and used
reset digital logic into a default state after powerup. POR active from 0.6VTyp. of AVDD and release
at 1.2V Typ. of AV DD (or 0.7V Typ. of DV DD if AV DD
powered before DV DD). And when AV DD or DV DD
back to 0.6VTyp. then POR will active again. To ensure
the contents of the control registers are at their default
values before carrying out any other register writes it
is recommended software reset for every time power
is cycled.
Rev. 1.10
6
November 24, 2011
HT82V46
edge of the CDS1 input signal (C1S). For input signals
that do not contain a reference level (e.g. CIS sensor
signals), non-CDS processing is used (CDS=0). In
this case, the video level is processed with respect to
the voltage on pin VRLC/VBIAS. The VRLC/VBIAS
voltage is sampled at the same time as CDS2 samples
the video level in this mode. In “WS” mode the input
video signal is always sampled on the 1st rising edge
of ADCK after CDS2 has gone low (Video Sample)
regardless of the operating mode. If in non-CDS mode
(CDS=0) the voltage on the VRLC/VBIAS pin is also
sampled at this point. In CDS-mode (CDS=1) the
position of the reference sample (C1S) can be varied,
under control of the CDSREF[1:0] register bits, as
shown in Figure11.
be connected to the VINR pin. The offset and gain
values that are applied to the Red input channel can
be selected, by internal multiplexers, to come from
the Red, Green or Blue offset and gain registers.
This allows the gain and offset values for each of
the input colours to be setup individually at the start
of a scan. When register bit ACYC=0 the gain and
offset multiplexers are controlled via the INTM[1:0]
register bits. When INTM=00 the red offset and gain
control registers are used to control the Red input
channel, INTM=01 selects the green offset and gain
registers and INTM=10 selects the blue offset and
gain registers to control the Red input channel. When
register bit ACYC=1, ‘auto-cycling’ is enabled, and
the input channel switches to the next offset and gain
registers in the sequence when a pulse is applied to
the CDS1 input pin. The sequence is Red → Green
→ Blue → Red… offset and gain registers applied
to the single input channel. A write to the Auto-cycle
reset register (address 05h) will reset the sequence to
a known state (Red registers selected). When autocycling is enabled, the CDS1 pin cannot be used to
control reset level clamping. The CLPCTL bit may be
used instead (enabled when high, disabled when low).
Line-by-Line Operation
Certain linear sensors give colour output on a lineby-line basis. i.e. a full line of red pixels followed
by a line of green pixels followed by a line of blue
pixels. Often the sensor will have only a single output
onto which these outputs are time multiplexed. The
HT82V46 can accommodate this type of input by
setting the LNBYLN register bit high. When in this
mode the green and blue input PGAs are disabled
to save power. The analogue input signal should
When auto-cycling is enabled, the CDS1 pin cannot
be used for reference sampling (i.e. CDS must be set
to 0).
C2S
CIN
Video Sample
Capacitor
VINR
C1S (CDS = 1) or
C2S (CDS = 0)
CLP
Reference Sample
Capacitor
=1
CDS
=0
VRLC/VBIAS
CDACPD
RLC
DAC
4
CDAC[3:0]
Figure 1 CDS/non-CDS Input Configuration
Rev. 1.10
7
November 24, 2011
HT82V46
See Figure 2 , Figure 3 and Figure 4.
A programmable detect circuit allows the sampling
point derived from CDS2 pin. When set C2DET to
1, the circuit detects either a rising or falling edge
(determined by C2POS control bit) on the CDS2 input
pin and generates an internal INTC2 pulse. When
C2POS=1, a positive edge transition is detected and
when C2POS=0, a falling edge transition is detected.
INTC2 can optionally be delayed by a number of
ADCK periods, specified by the C2DLY[2:0] bits.
Figure 5 shows the sampling point occurs on the first
rising ADCK edge after this internal CDS2 pulse.
“WS” Mode (WS=1)
“WS” Mode Timing Diagram
It requires double rate ADCK and pixel rate CDS2
input. CDS1 pin performs same function as RLC/
ACYC pin.
See Figure 6 , Figure 7, Figure 8 and Figure 9.
Analog Input Signal Sampling
There are “NM” and “WS” two operating modes of
HT82V46. It can be selected by register bit WS.
“NM” Mode (WS=0; Normal Mode)
The ADCK speed can be specified along with the
ADCK:CDS2 ratio to achieve the desired sample rate
as table 1.
“NM” Mode Timing Diagram
ADCK: 45MHz; CDS: available
Register Bit
R/G/B of PGA
ADCK:CDS2
Max. Sample
Rate (MSPS)
1CH
2CH
CH[1:0]
Red
Green
Blue
3:1
15
0
0
XX
V1
V1
V1
3-channel
2:1
22.5
0
1
XX
V1
V1
X1
2-channel
00
V1
X1
X1
1:1
45
1
0
01
X1
V1
X1
10
X1
X1
V1
―
―
1
0
11
―
―
―
Invalid
―
―
1
1
XX
―
―
―
Invalid
Mode
1-channel
Where X1 : Disable; V1 : Enable
Table 1 “NM” Operating Modes
Pixel n
Analog
Input
Pixel n+1
Pixel n+2
(R, G, B)
t ADFC1R
t PR3
t C1
CDS1
t C1FC2R
t C2
CDS2
t
t C2FADR
ADFC2R
ADCK
t ADH
OD[7:0]
t ADC
t ADL
t
t
OD
OD
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
n-3
n-4
n-2
n-1
HB : High Byte; LB : Low Byte
Figure 2 3-channel CDS Analog Input Timing
Rev. 1.10
8
November 24, 2011
HT82V46
Pixel n+1
Pixel n
Analog
Input
Pixel n+2
Pixel n+3
(R, G)
t C1
t ADFC1R
t PR2
CDS1
t C1FC2R
t C2
CDS2
t ADFC2R
t C2FADR
ADCK
t ADH
OD[7:0]
t OD
t ADL
t
OD
G
G
R
R
G
G
R
R
G
G
R
R
G
G
R
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
LB
HB
n-3
n-4
n-5
n-2
n-1
HB : High Byte; LB : Low Byte
Figure 3 2-channel CDS Analog Input Timing
Pixel n+1
Pixel n
Analog
Input
Pixel n+2
Pixel n+3
(R)
t ADFC1R
t PR1
t C1
CDS1
t C1FC2R
t C2
ADFC2R
CDS2
t C2FADR
t
ADFC2F
ADCK
OD[7:0]
t
t ADH
t ADL
R
R
R
R
R
R
R
R
HB
LB
HB
LB
HB
LB
HB
LB
n-8
t ADC
n-7
OD
t
n-6
OD
n-5
HB : High Byte; LB : Low Byte
Figure 4 1-channel CDS Analog Input Timing
Note: 1. The relationship between input video and sampling is controlled by CDS2 and CDS1.
2. When CDS2 is high the input video signal is connected to the Video level sampling capacitors.
3. When CDS1 is high the analog input video signal is connected to the Reference level sampling capacitors.
4. CDS1 must not go high before the first falling edge of ADCK after CDS2 goes low.
5. It is required that the falling edge of CDS2 should occur before the rising edge of ADCK.
6. In 1-channel CDS mode it is not possible to have a equally spaced Video and Reference sample points
with a 45MHz ADCK.
7. Non-CDS operation is also possible; CDS1 is not required in this mode.
Rev. 1.10
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HT82V46
ADCK
CDS2
C2POS = 1
INTC2
C2S
C2DLY[2:0] = 001
C2DLY[2:0] = 111
C2S
C2S
C2DLY[2:0] = 000
C2S
C2S
C2S
C2POS = 0
INTC2
C2S
C2S
C2DLY[2:0] = 000
C2S
C2S
C2DLY[2:0] = 001
C2S
C2S
C2DLY[2:0] = 111
Figure 5 Internal CDS2 Pulses Generated by Programmable CDS2 Detect Circuit
ADCK : 45MHz
Mode
Timing REQ.
ADCK:CDS2
Sample Rate
(MSPS)
Register Bit
CDSREF[1:0]
WS
MODE4
2CH
1CH
MODE1:
3-CH Pixel-by-Pixel
2n:1, n ≥ 3
7.5
―
0
0
MODE2:
1-CH Line-by-Line
2n:1, n ≥ 3
7.5
―
0
1
MODE3:
1-CH Line-by-Line
3:1
22.5
00
0
0
MODE4:
1-CH Line-by-Line
2:1
22.5
―
1
0
1
CDS
0
EN
1
0
1
0
1
1
0
0
0
Table 2 “WS” Operating Modes
Note: 1. In 1-channel mode, Setup Register 3 bits 7:6 CH[1:0] determine which input is to be sampled.
2. For Colour Line-by-Line, set Register Bit LNBYLN. For input selection, refer to Table 1, Colour
Selection Description in Line-by-Line mode.
Rev. 1.10
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November 24, 2011
HT82V46
16.5 ADCK
ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
DLY[1:0] = 00
B R R G G B B R R G G B B R R G G B B R R G G B B R R G G B B R R G G B
LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB
DLY[1:0] = 01
R R G G B B
HB LB HB LB HB LB
DLY[1:0] = 10
R R G G B B
HB LB HB LB HB LB
DLY[1:0] = 11
R R G G B B
HB LB HB LB HB LB
HB : High Byte; LB : Low Byte
Figure 6 MODE1 : 3-channel Pixel-by-Pixel
16.5 ADCK
ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
DLY[1:0] = 00
X HB LB X
X
X
X HB LB X
X
X
X HB LB X
X
X
X HB LB X
X
X
X HB LB X
X
X
X HB LB X
X
X
DLY[1:0] = 01
HB LB
DLY[1:0] = 10
HB LB
DLY[1:0] = 11
HB LB
HB : High Byte; LB : Low Byte; X : Invalid Data
Figure 7 MODE2 : 1-channel Line-by-Line
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HT82V46
23.5 ADCK
ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
DLY[1:0] = 00
LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB
HB
LB
HB LB
HB
LB
HB
LB
HB
LB HB
DLY[1:0] = 01
HB LB
DLY[1:0] = 10
HB
LB
DLY[1:0] = 11
HB : High Byte; LB : Low Byte
Figure 8 MODE3 : 1-channel Line-by-Line
16.5 ADCK
ADCK
CDS2
Analog
Input
(R, G, B)
OD[7:0]
DLY[1:0] = 00
HB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB
DLY[1:0] = 01
HB LB
DLY[1:0] = 10
HB LB
DLY[1:0] = 11
HB LB
HB : High Byte; LB : Low Byte
Figure 9 MODE4 : 1-channel Line-by-Line
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HT82V46
is low at this point then the RLC switch will not be
closed for that input sample. If RLC is required on
every pixel then the CDS1 pin can be constantly
held high in “WS” mode.
Reset Level Clamping (RLC)
There are Pixel-Clamping and Line-Clamping two
operating modes of HT82V46. It can be selected by
register bit CLPCTL. The clamp switch controlled
by an internal CLP signal, and must set the RLCEN
(default=1) register bit to 1 to enable clamping.
Line-clamping (CLPCTL=1)
• WS=0 (Normal Mode) and CDS=0 (Non-CDS
mode) only.
Pixel-clamping (CLPCTL=0)
In situations where the input video signal does not
have a stable reference level it may be necessary
to clamp only during those pixels which have a
known state (e.g. the Dummy, or Black pixels at
the start or end of a line of most image sensors).
This is known as line-clamping and relies on
the input capacitor to hold the DC level between
clamp intervals. In non-CDS mode (CDS=0) this
can be done directly by controlling the CDS1
input pin to go high during the black pixels only.
Alternatively it is possible to use CDS1 to identify
the black pixels and enable the clamp at the same
time as the input is being sampled (i.e. when CDS2
is high and CDS1 is high). This mode is enabled
by setting CLPCTL=1 and the operation is shown
in Figure 12.
• When WS=0 (Normal Mode) and CDS=X (both
for CDS mode and non-CDS mode).
The RLC switch is closed whenever the CDS1
input pin is high, as shown in Figure 10.
• When WS=1 and CDS=1 (CDS mode only)
Reset Level Clamping in “WS” mode is only
possible in CDS mode and the time at which the
clamp switch is closed is concurrent with the
reference sample period, C1S, as shown in Figure
11. RLC can be enabled on a pixel by pixel basis
under control of the CDS1 input pin. If CDS1 is
high when CDS2 is high and is sampled by ADCK
then clamping will be enabled for that input sample
at the time determined by CDSREF[1:0]. If CDS1
Analog
Input
ADCK
CDS2
CDS1
CLP
Figure 10 Pixel-Clamping RLC Operation, with CDS (Non-CDS also Possible)
ADCK
CDS2
C2S
C1S
CDSREF[1:0] = 00
C1S
CDSREF[1:0] = 01
C1S
CDSREF[1:0] = 10
C1S
CDSREF[1:0] = 11
CDS1
RLC switch closed when CDS1 = 1
CLP
CDSREF[1:0] = 00
CLP
CDSREF[1:0] = 01
CLP
CDSREF[1:0] = 10
CLP
CDSREF[1:0] = 11
C2S : Video Sample; C1S : Reference Sample
Figure 11 “WS” Mode (WS=1) RLC and Sampling
Rev. 1.10
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HT82V46
Video level
unstable Ref. level
Analog
Input
Dummy or Black pixel
ADCK
CDS2
CDS1
CLP
Figure 12 Line-Clamping RLC Operation (Non-CDS Only)
Summaries of the RLC Switch Control
Option
Register Bit
RLC control
WS
CLPCTL RLCEN ACYC LNBYLN
Input is DC coupled
RLC is not enabled.
and within supply
RLC switch is always open.
range
X
X
0
X
X
Input video signal
has a suitable
reference level
RLC switch is controlled by CDS1 pin.
CDS1=0/1 : switch is open/closed
0
0
1
X
X
Pixel reference level
not stable or need
to clamp the black
pixels of video period
CDS2 is normal, and CDS1 is used to indicate
black pixels location. RLC switch is controlled
by CDS1 and CDS2 logical combination.
CDS1 & CDS2=0/1: switch is open/closed
0
1
1
X
X
Using “WS” mode
CDS1 pin as RLC/ACYC pin, and the
reference sample clock is gated by the “WS”
internal timing generator, see Figure 11.
CLP is an internal clamp switch control signal.
CLP=0/1 : clamp switch open/closed
1
X
1
X
X
Using auto-cycling
in “WS” mode
CDS1 pin as auto-cycling control and can’t be
clamp control signal.
CLPCTL controls whether RLC is enabled or
not. CLPCTL=0/1 : RLC is disabled/ enabled;
see Figure 11.
1
X
1
1
0
1
Table 3 The Options for the Control of RLC Switch
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HT82V46
Offset Adjust and Programmable Gain
♦♦
If CDACPD=1
VRLC is an externally applied voltage on pin
The output from the CDS block is a differential
signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by
a 8-bit PGA. The gain and offset for each channel are
independently programmable by writing to control
bits DAC[7:0] and PGA[7:0]. In colour line-by-line
mode the gain and offset coefficients for each colour
can be multiplexed in order (Red → Green → Blue →
Red…) by pulsing the CDS1 pin, or controlled via the
ACYC and INTM[1:0] bits. Refer to the Line-by-Line
Operation section for more details.
VRLC/VBIAS.
♦♦
If CDACPD=0
VRLC is the output from the internal RLC DAC.
VRLC= ( VCSTEP x CDAC[3:0] ) + VCBOT
Where VCSTEP: the step size of the RLC DAC;
VCBOT: the minimum output of the RLC DAC
Offset DAC Block
The resultant signal V1 is added to the Offset DAC
output.
ADC Input Black Level Adjust
V2= V1 + (260mV x (DAC[7:0] − 127.5) ) / 127.5
The output from the PGA can be offset to match the
full-scale range of the differential ADC (2 * (VRT VRB)).
PGA Block
The signal is then multiplied by the PGA gain.
Negative-going Input Cideo Signals
V3= V2 + (0.66 + PGA[8:0] x 7.34 / 511)
The black level (zero differential) output from the
PGA should be offset to the top of the ADC range by
setting register bits PGAFS[1:0]=10. This will give
an output code of FFFF (hex) from the HT82V46 for
zero input. If code zero is required for zero differential
input then the INVOD bit should be set.
ADC Block
The analogue signal is then converted to a 16-bit
unsigned number, with input range configured by
PGAFS[1:0].
• PGAFS[1:0]=0X
Positive-going Input Video Signals
D1 [15:0]=INT ( (V3 / VFS) x 65535) + 32767
The black level should be offset to the bottom of the
ADC range by setting PGAFS[1:0]=11. This will give
an output code of 0000 (hex) from the HT82V46 for
zero input.
• PGAFS[1:0]=10
D1 [15:0]=INT ( (V3 / VFS) x 65535) + 65535
• PGAFS[1:0]=11
Bipolar Input Video Signals
D1 [15:0]=INT ( (V3 / VFS) x 65535) + 0
It’s accommodated by setting PGAFS[1:0]=00 or
PGAFS[1:0]=01. Zero differential input voltage gives
mid-range ADC output, 7FFF (hex).
Where VFS: the ADC full-scale range
(LOWREF=0 / 1 then VFS= 2V / 1.2V)
Output Invert Block
Signal Flow Summary
See Figure13 for overall signal flow diagram.
The polarity of the digital output may be inverted by
control bit INVOD.
Input Sampling Block
• INVOD=0
• When CDS=1
D2 [15:0]= D1 [15:0]
The previously sampled reference level VRL is
subtracted from the input video VIN.
• INVOD=1
D2 [15:0]= 65535 − D1 [15:0]
V1= VIN − VRL
Output Formats
• When CDS=0
The simultaneously sampled voltage on pin
VRLC/VBIAS is subtracted instead.
The output from the HT82V46 can be presented
in several different formats under control of the
ODFM[1:0] register bits as shown in Figure 14.
V1= VIN − VRLC
Rev. 1.10
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November 24, 2011
HT82V46
Input
Sampling
Block
+
VIN
Offset
DAC
Block
V1
+
V2
+
+
-
+
Output
Invert
Block
ADC
Block
PGA
Block
V3
+
x
+
D2
D1
* 65535 / VFS
OD[7:0]
VRL
CDS
=1
Offset
DAC
=0
2
VRLC
9
CDACPD
RLC
DAC
8
4
= 0 : D2 = D1
= 1 : D2 = 65535 – D1
= 0X : + 32768
= 10 : + 65535
= 11 : + 0
INVOD
PGAFS[1:0]
0.66 + PGA[8:0] * 7.34 / 511
260mV * (DAC[7:0]–127.5) / 127.5
CDAC[3:0]
Where
VIN = VINR or VING or VINB
VRL = VIN sampled during Ref. clamp
VRLC = voltage applied to VRLC/VBIAS pin
Figure 13 Overall Signal Flow
ADCK
WS = 0
t
ODFM[1:0] = X0
HB
OD[7:0]
LB
t
OD
HB
LB
HB
OD
LB
HB
LB
HB
LB
HB
LB
ODFM[1:0] = 01
HB
OD[7:0]
HB
HB
HB
HB
HB
WS = 1
ODFM[1:0] = X0
OD[7:0]
HB
LB
HB
LB
HB
LB
ODFM[1:0] = 01
HB
HB
OD[7:0]
HB
ODFM[1:0] = 11
OD[7:4]
NB4
NB3
NB2
NB1
NB4
HB : High Byte; LB : Low Byte
NB3
NB2
NB1
NB4
NB3
NB2
NB4~NB1 : Nibble (NB4 is the most significant)
Figure 14 Output Data Format
Rev. 1.10
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November 24, 2011
HT82V46
Serial Control Interface
Register Read-back (A4=1 and D[7:0] is don’t Cared
at Register Write Cycle)
The internal control registers are programmable and
can be read-back via the serial control interface and
pin OD[7]/SDO.
Read-back is initiated by Register Write as described
above but with A4 set to 1, followed by an 8-bit
dummy data word. Writing address (A5, 1, A3,
A2, A1, A0) will cause the contents D[7:0] of
corresponding register(A5, 1, A3, A2, A1, A0) to be
output D[7:0] on pin SDO/OD[7] at the falling edge
of SCK. SDO/OD[7] is shared pin, therefore OEB
pin should always be held low and the OPD register
bit should be set low when register read-back data is
expected on this pin. The next word may be read in to
SDI while the previous word is still being output on
SDO/OD[7] pin.
Register Write (A4=0)
SCK, SDI and SEN are used for register writing. A
address A[5:0] is clocked in through SDI, followed by
a data word D[7:0]. Each bit is latched on the rising
edge of SCK. When the data has been shifted into the
device, a pulse is applied to SEN to transfer the data
to the appropriate internal register.
Note: To ensure all registers are set to their default
values it is recommended that a software-reset
is carried out after the power-up sequence,
before writing to any other register.
Register Write Cycle
t SCK
SCK
t SDIS
SDI
t SDIH
A5
A4
A[3:0]
D[7:0]
t CKFENR
t ENFCKR
SEN
t ENFSD7
SDO/OD[7]
t CKFSD6
D7
OD[7]
D6
D[5:1]
t CKFOD7
D0
OEB
Register Write: A4=0
Register read-back: A4=1 (D[7:0] don´t care at write cycle)
Figure 15 Serial Control Interface Timing
Rev. 1.10
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HT82V46
Control Registers
Register Mapping
A[5:0] Description POR
R/W
D7
D6
01h
Setup
Register 1
D5
D4
D3
D2
D1
D0
03h
RW
WS
MODE4
PGAFS[1:0]
2CH
1CH
CDS
EN
02h
Setup
Register 2
20h
RW
DLY[1:0]
CDACRNG LOWREF
OPD
INVOD
03h
Setup
Register 3
1Fh
RW
CH[1:0]
CDSREF [1:0]
04h
Software
Reset
00h
W
―
05h
Auto-cycle
Reset
00h
W
―
06h
Setup
Register 4
00h
RW
0
0
0
07h
Setup
Register 5
00h
RW
0
CMLPD
REFPD
08h
Setup
Register 6
20h
RW
0
CLPCTL
RLCEN
ODFM[1:0]
CDAC[3:0]
0
INTM[1:0]
CDACPD ADCPD
C2POS
BPD
ACYC
LNBYLN
GPD
RPD
C2DLY[2:0]
C2DET
09h
Reserved
00h
RW
0
0Ah
Reserved
00h
RW
0
0Bh
Reserved
00h
RW
0
0Ch
ID
00h
RW
0Dh
Reserved
00h
RW
0
20h
DAC value
(Red)
80h
RW
DACR[7:0]
21h
DAC value
(Green)
80h
RW
DACG[7:0]
22h
DAC value
(Blue)
80h
RW
DACB[7:0]
23h
DAC value
(RGB)
80h
W
DAC[7:0]
24h
PGA gain
(Red)
00h
RW
0
PGAR[0]
25h
PGA gain
(Green)
00h
RW
0
PGAG[0]
26h
PGA gain
(Blue)
00h
RW
0
PGAB[0]
27h
PGA gain
(RGB)
00h
W
0
PGA[0]
28h
PGA gain
(Red)
0Dh
RW
PGAR[8:1]
29h
PGA gain
(Green)
0Dh
RW
PGAG[8:1]
2Ah
PGA gain
(Blue)
0Dh
RW
PGAB[8:1]
2Bh
PGA gain
(RGB)
00h
W
PGA[8:1]
Rev. 1.10
0
18
ID[3:0]
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HT82V46
Register Description
Register
Bit No.
Name
POR.
0
EN
1
Global Enable
0= complete power down
1= fully active
1
CDS
1
Sampling mode select
0= 2 or 3 channel
1= 1 channel. Input channel selected by CH[1:0] bits and unused
channels are powered down.
0
Sampling mode select
0= 1 or 3 channel
1= 2 channel mode. Input channels are Red and Green. Blue channel
is powered down.
0
Sampling mode select
0= 1 or 3 channel
1= 2 channel mode. Input channels are Red and Green. Blue channel
is powered down.
2
3
1CH
2CH
Setup
Register 1
Rev. 1.10
Description
5:4
PGAFS[1:0]
00
Offsets PGA output to optimize the ADC range for different polarity
sensor output signals. Zero differential PGA input signal gives:
0x= Zero output from the PGA, output=32767
10= Full-scale positive output, output=65535; use for negative going
video. Set INVOD=1 if zero differential input should give a
zero output code with negative going video.
11= Full-scale negative output, output=0;
use for positive going video
6
MODE4
0
This bit has no effect when WS=0.
Set this bit when operating in “WS” MODE 4.
0= Other mode
1= “WS” MODE 4
7
WS
0
Makes the HT82V46 timing to the other operating mode selection
0= Normal timing
1= Enable “WS” timing. Requires double rate ADCK and pixel rate
CDS2 input. CDS1 pin performs same function as RLC/ACYC pin.
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HT82V46
Register
Bit No.
Name
POR.
Description
1:0
ODFM[1:0]
0
Determines the output data format
X0= 8 bits multiplexed (8+8 bits)
01= 8 bits parallel (8-MSB only)
11= 4-bit multiplexed mode (4+4+4+4 bits). This mode is only valid
when WS=1.
2
INVOD
0
Digitally inverts the polarity of output data
Output disable. This works with the OEB pin to control the output pins.
0= Digital outputs enabled
1= Digital outputs high impedence
3
Setup
Register 2
OPD
0
OEB
OPD
OD
0
0
Enabled
0
1
Hi-Z
1
0
Hi-Z
1
1
Hi-Z
4
LOWREF
0
Reduces the ADC reference range 2*(VRT – VRB), thus changing the
max/min input voltages.
0= ADC reference range=2V
1= ADC reference range=1.2V
5
CDACRNG
1
Sets the output range of the RLCDAC
0= RLCDAC ranges from 0 to AVDD
1= RLCDAC ranges from 0 to VRT
Controls the latency from sample to data appearing on output pins
WS
7:6
DLY[1:0]
00
=0
=1
=1
Timing modes
All
1-2, 4-6
3
DLY=00
7T
16.5T
23.5T
DLY=01
8T
18.5T
26.5T
DLY=10
9T
20.5T
29.5T
DLY=11
10T
22.5T
31.5T
Where T=ADCK periods
Setup
register 3
―
3:0
5:4
CDAC[3:0]
CDSREF[1:0]
1111
Controls RLCDAC driving VRLC/VBIAS pin to define ended signal
reference voltage or reset level clamp voltage.
01
When WS=0 these register bit have no effect.
CDS mode timing adjust.
00= Advance reference sample by 1 ADCK period
01= Default reference sample position
10= Delay reference sample by 1 ADCK period
11= Delay reference sample by 2 ADCK period
―
7:6
CH[1:0]
00
When 1CH=0 these register bits have no effect.
Monochrome mode channel select.
00= Select red channel
01= Select green channel
10= Select blue channel
11= Reserved
Software
―
―
―
Write this register will causes all function to be reset.
It is recommended that a software reset be performed after a power
on before any other register writes.
Auto-cycle
reset
―
―
―
Write this register will causes the auto-cycle counter to reset to VINR.
This function is only required when LNBYLN=1.
Rev. 1.10
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HT82V46
Register
Bit No.
Name
POR.
Description
0
LNBYLN
0
Selects line by line operation. Line by line operation is intended for use
with systems which operate one line at a time but with up to three color
shared on the one output.
0
If LNBYLN=0 then ACYC bit no effect.
ACYC bit determines CDS1 pin and offset/gain register controls
0= CDS1 pin is for Reference Sampling or Reset Level Clamp
control. And INTM[1:0] bits are for gain/offset multiplexers control.
1= Auto-cycling enabled by pulsing CDS1 pin and input signal
switched to next gain/offset register sequentially. And sequence is
Red -> Green -> Blue -> Red etc. At this mode, it must set
CDS=0 and use CLPCTL bit instead CDS1 pin to control RLC.
When LNBYLN=0 or ACYC=1 this bit has no effect.
When LNBYLN=1 and ACYC=0.
Controls the offset/gain mux selector.
00= Red offset/gain registers applied to input channel.
01= Green offset/gain registers applied to input channel.
10= Blue offset/gain registers applied to input channel.
11= Reserved.
1
ACYC
Setup
register 4
Setup
register 5
Rev. 1.10
3:2
INTM[1:0
00
7:4
Reserved
0000
0
REDPD
0
When set powers down red S/H, PGA
1
GRNPD
0
When set powers down green S/H, PGA
2
BLUPD
0
When set powers down blue S/H, PGA
3
ADCPD
0
When set powers down ADC, allows reduced power consumption
without powering down the references which have a long time constant
when switching on/off due to the external decoupling capacitors.
4
CDACPD
0
When set powers down 4-bit RLCDAC, setting the output to a high
impedance state and allowing an external reference to be driven in on
the VRLC/VBIAS pin.
5
REFPD
0
When set disables REFT, REFB buffers to allow external references to
be used.
6
CMLPD
0
When set disable CML buffer to allow an externa reference to be used.
7
Reserved
0
Must be set to 0
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HT82V46
Register
Bit No.
0
3:1
Setup
register 6
4
5
Name
C2DET
C2DLY[2:0]
C2POS
RLCEN
POR.
Description
0
When WS=0 this register bit has no effect.
When WS=1.
0= Normal operation, signal on CDS2 input pin is applied directly to
timing control block.
1= Programmable CDS2 detect circuit is enabled. An internal
synchronization pulse is generated from signal applied to CDS2
input pin and is applied to timing control block on place of CDS2.
000
When WS=0 or C2DET=0 these bits have no effect.
The C2DLY bits set a programmable delay from the detected edge of
the signal applied to the CDS2 pin. The internally generated pulse is
delayed by C2DLY ADCK periods from the detected edge.
0
When WS=0 or C2DET=0 this bit has no effect
When WS=1 and C2DET=1 this bit controls whether positive or
negative edges on the CDS2 input pin are detected.
0= Negative edge on CDS2 pin is detected and used to generate
internal timing pulse.
1= Positive edge on CDS2 pin is detected and used to generate
internal timing pulse.
1
Reset level clamping enable. When set RLCEN is enabled. The
method of clamping is determined by CLPCTL and WS.
In “WS” mode clamping will still occur on every pixel at a time defined
by the CDSREF[1:0] bits.
6
CLPCTL
0
This bit has no effect if WS=1. See Table 3 for more information.
0= RLC switch is controlled directly from CDS1 input pin.
CDS1= 0: switch is open
CDS1= 1: switch is close
1= RLC switch is controlled by logical combination of CDS1 and
CDS2.
CDS1 & CDS2=0 : switch is open.
CDS1 & CDS2=1 : switch is close.
7
Reserved
0
Must be set to 0.
7:4
Reserved
0
Must be set to 0.
3:0
ID[3:0]
DAC value
(Red)
7:0
DACR[7:0]
0
Red channel 8-bit offset DAC MSB value.
DAC value
(Green)
7:0
DACG[7:0]
0
Green channel 8-bit offset DAC MSB value.
DAC value
(Blue)
7:0
DACB[7:0]
0
Blue channel 8-bit offset DAC MSB value.
DAC value
(RGB)
7:0
DAC[7:0]
0
Write to this register will cause the R, G and B offset DAC MSB
registers to be overwritten by the new value.
PGA gain
(Red)
0
PGAR[0]
0
This register bit forms the LSB of the red channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 28 hex.
PGA gain
(Green)
0
PGAG[0]
0
This register bit forms the LSB of the green channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 29 hex.
PGA gain
(Blue)
0
PGAB[0]
0
This register bit forms the LSB of the blue channel PGA gain code.
PGA gain is determined by combining this register bit and the 8 MSBs
contained in register address 2A hex.
PGA gain
(RGB)
0
PGA[0]
0
Writing a value to this location causes red, green and blue PGA LSB
gain values to be overwritten by the new value.
PGA gain
(Red)
7:0
PGAR[8:1]
0D
Red PGA gain setting register. 0.66+PGAR[8:0]*7.34/511
PGA gain
(Green)
7:0
PGAG[8:1]
0D
Green PGA gain setting register. 0.66+PGAG[8:0]*7.34/511
ID
Rev. 1.10
ID[3:0] these bits are storable and can be written from 0000 to 1111
0000 values. But note that ID[3:0] will be cleared to 0000 after Power-OnReset.
22
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HT82V46
Register
Bit No.
Name
POR.
PGA gain
(Blue)
7:0
PGAB[8:1]
0D
PGA gain
(RGB)
7:0
PGA[8:1]
0
Description
Blue PGA gain setting register. 0.66+PGAB[8:0]*7.34/511
A write to this register will cause R, G and B PGA gain registers to be
overwritten by the new value.
Application Circuits
AVDD
0.1uF
0.1uF
0.1uF
0.01uF
1uF
0.1uF
VINR
28
VING
27
VINB
26
VRLC/VBIAS
24
REFT
25
CML
23
REFB
AVDD
21
AVSS
22
AVSS
2
DVDD
3
DVDD
10
DVSS
8
Timing
Control
Interface
Control
ADCK
6
CDS1
OD[7]/SDO
20
5
CDS2
OD[6]
19
OD[5]
18
12
SCK
OD[4]
17
11
SDI
OD[3]
16
9
SEN
OD[2]
15
OD[1]
14
4
OEB
OD[0]
13
10uF
DVDD
0.1uF
0.1uF
DVDD
Reservoir
DVDD
HT82V46
7
0.1uF
AVDD
Reservoir
Video
Input
1
10uF
ADC
Data
Output
Note: 1. All de-coupling capacitors should be fitted as close to HT82V46 as possible.
2. AVSS and DVSS should be connected as close to HT82V46 as possible.
Rev. 1.10
23
November 24, 2011
HT82V46
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/
literature/package.pdf) for the latest version of the package information.
28-pin SSOP (209mil) Outline Dimensions
MS-150
Symbol
Min.
Nom.
Max.
A
0.291
―
0.323
B
0.197
―
0.220
C
0.009
―
0.013
C'
0.390
―
0.413
D
―
―
0.079
E
―
0.026
―
F
0.002
―
―
G
0.022
―
0.037
H
0.004
―
0.008
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
7.40
―
8.20
B
5.00
―
5.60
C
0.22
―
0.33
C'
9.90
―
10.50
D
―
―
2.00
E
―
0.65
―
F
0.05
―
―
G
0.55
―
0.95
H
0.09
―
0.21
α
0°
―
8°
24
November 24, 2011
HT82V46
Reel Dimensions
SSOP 28S (209mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0 +0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
28.4 +0.3/-0.2
T2
Reel Thickness
31.1 (max.)
Rev. 1.10
2.0±0.5
25
November 24, 2011
HT82V46
Carrier Tape Dimensions
 SSOP 28S (209mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5 +0.1/-0.00
D1
Cavity Hole Diameter
1.50 +0.25/-0.00
P0
Perforation Pitch
4.0±0.2
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
8.4±0.1
B0
Cavity Width
10.65±0.10
K0
Cavity Depth
2.4±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.10
26
November 24, 2011
HT82V46
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-5631999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright © 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications
mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation
that such applications will be suitable without further modification, nor recommends the use of its products for
application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not
authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web site at http://www.
holtek.com.tw.
Rev. 1.10
27
November 24, 2011