INTEL 410

Intel® Celeron® M Processor
on 65 nm Process
Datasheet
January 2007
Document Number: 312726-004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details.
Intel, Celeron, Pentium, MMX, and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States
and other countries.
* Other brands and names are the property of their respective owners.
Copyright © 2006 – 2007, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction .............................................................................................................. 7
1.1
Terminology ....................................................................................................... 8
1.2
References ......................................................................................................... 9
2
Low Power Features ................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 12
2.1.2 Package Low Power States ...................................................................... 13
2.2
FSB Low Power Enhancements ............................................................................ 15
2.3
Processor Power Status Indicator (PSI#) Signal..................................................... 16
3
Electrical Specifications ........................................................................................... 17
3.1
FSB (Front Side Bus) and GTLREF........................................................................ 17
3.2
Power and Ground Pins ...................................................................................... 17
3.3
Decoupling Guidelines ........................................................................................ 17
3.3.1 VCC Decoupling...................................................................................... 18
3.3.2 FSB AGTL+ Decoupling ........................................................................... 18
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 18
3.4
Voltage Identification and Power Sequencing ........................................................ 18
3.5
Catastrophic Thermal Protection .......................................................................... 22
3.6
Signal Terminations and Unused Pins ................................................................... 22
3.7
FSB Frequency Select Signals (BSEL[2:0])............................................................ 23
3.8
FSB Signal Groups............................................................................................. 23
3.9
CMOS Signals ................................................................................................... 25
3.10 Maximum Ratings.............................................................................................. 25
3.11 Processor DC Specifications ................................................................................ 25
4
Package Mechanical Specifications and Pin Information .......................................... 31
4.1
Processor Component Keep-Out Zones ................................................................. 31
4.2
Package Loading Specifications ........................................................................... 31
4.3
Processor Mass Specifications ............................................................................. 31
4.4
Processor Pinout and Pin List .............................................................................. 36
4.5
Alphabetical Signals Reference ............................................................................ 55
5
Thermal Specifications and Design Considerations .................................................. 63
5.1
Thermal Specifications ....................................................................................... 65
5.1.1 Thermal Diode ....................................................................................... 65
5.1.2 Thermal Diode Offset .............................................................................. 68
5.1.3 Intel® Thermal Monitor........................................................................... 68
5.1.4 Digital Thermal Sensor............................................................................ 70
5.1.5 Out of Specification Detection .................................................................. 70
5.1.6 PROCHOT# Signal Pin ............................................................................. 70
Datasheet
3
Figures
1
2
3
4
5
6
7
8
Package-Level Low Power States ................................................................................11
Core Low Power States..............................................................................................12
Active VCC and ICC Loadline for the Celeron M Processor Standard Voltage .......................28
Active VCC and ICC Loadline for the Celeron M Processor Ultra Low Voltage .......................28
Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................32
Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................33
Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................34
Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ................................................35
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
4
Coordination of Core-Level Low Power States at the Package Level for the Celeron M
Processor ................................................................................................................11
Voltage Identification Definition ..................................................................................19
BSEL[2:0] Encoding for BCLK Frequency......................................................................23
FSB Pin Groups ........................................................................................................24
Processor DC Absolute Maximum Ratings.....................................................................25
Voltage and Current Specifications for the Celeron M Processor Standard Voltage..............26
Voltage and Current Specifications for the Celeron M Processor Ultra Low Voltage .............27
FSB Differential BCLK Specifications ............................................................................29
AGTL+ Signal Group DC Specifications ........................................................................29
CMOS Signal Group DC Specifications..........................................................................30
Open Drain Signal Group DC Specifications ..................................................................30
The Coordinates of the Processor Pins As Viewed from the Top of the Package .................36
Pin Listing by Pin Name .............................................................................................39
Pin Listing by Pin Number ..........................................................................................46
Signal Description.....................................................................................................55
Power Specifications for the Celeron M Processor Standard Voltage .................................64
Power Specifications for the Celeron M Processor Ultra Low Voltage.................................65
Thermal Diode Interface ............................................................................................66
Thermal Diode Parameters using Diode Model ..............................................................66
Thermal Diode Parameters using Transistor Mode .........................................................67
Thermal Diode ntrim and Diode Correction Toffset..........................................................68
Datasheet
Revision History
Revision
-001
Description
Initial release
•
Date
April 2006
-002
•
Chapter 3, “Electrical Specifications”
— Added 440 and 450 processor specifications to Table 6.
Chapter 5, “Thermal Specifications and Design Considerations”
— Added power specifications for the 440 and 450 processor
to Table 16.
-003
•
Corrected page numbering in Chapter 5
September 2006
•
Chapter 3, “Electrical Specifications”
— Added 443 ULV processor specifications to Table 7.
Chapter 5, “Thermal Specifications and Design Considerations”
Added power specifications for the 443 ULV processor to Table 17.
January 2007
-004
•
•
September 2006
§
Datasheet
5
6
Datasheet
Introduction
1
Introduction
The Intel® Celeron® M processor based on 65 nm process technology is a highperformance, low-power mobile processor with several enhancements over previous
mobile Celeron processors.
Throughout this document, the term “Celeron M processor” refers to the Intel®
Celeron® M processor based on 65 nm process technology.
This document contains specifications for both the Intel® Celeron® M processor 450,
440, 430, 420, 410 and Intel® Celeron® M processor Ultra Low Voltage 443 and 423Δ.
Note:
ΔIntel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details.
The following list provides some of the key features on this processor:
• On-die, 1-MB second level cache with Advanced Transfer Cache Architecture
• Supports Intel Architecture with Dynamic Execution
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache
• Data Prefetch Logic
• Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)
• The Celeron M processor and the Celeron M processor Ultra Low Voltage are offered
at 533-MHz FSB
• Digital Thermal Sensor
• The Celeron M is a single core processor offered in both Micro-FCPGA and MicroFCBGA packages
• The Celeron M processor Ultra Low Voltage is a single core processor offered only in
a Micro-FCBGA package
• Execute Disable Bit support for enhanced security
The Celeron M processor will be manufactured on Intel’s 65 nanometer process
technology with copper interconnect. The processor maintains support for MMX™
technology, Streaming SIMD instructions, and full compatibility with IA-32 software.
The Celeron M processor features on-die, 32-kB level 1 instruction and data caches and
a 1-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data
Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests
occurs, resulting in reduced bus cycle penalties. The Celeron M processor includes the
Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by
requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced
to help with the write-back latency performance.
In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are
13 new instructions which further extend the capabilities of Intel processor technology.
These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics
and other entertainment applications such as gaming will have the opportunity to take
advantage of these new instructions as platforms with the Celeron M processor based
on 65 nm process and SSE3 become available in the market place.
The Celeron M processor’s front side bus (FSB) utilizes a split-transaction, deferred
reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data
to improve performance by transferring data four times per bus clock. The 4X data bus
can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data
Datasheet
7
Introduction
bus, the address bus can deliver addresses two times per bus clock and is referred to
as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X
address bus provide a data bus bandwidth of up to 4.26 GB/second. The FSB uses
Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+
signaling technology with low power enhancements. The processor features the Auto
Halt, Stop Grant and Deep Sleep low power C-states.
The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (MicroFCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package
technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero
Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket.
Celeron M processor supports the Execute Disable Bit capability. This feature combined
with a support operating system allows memory to be marked as executable or non
executable. If code attempts to run in non-executable memory the processor raises an
error to the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the IA-32 Intel® Architecture Software Developer's Manual
for more detailed information.
1.1
Terminology
Term
8
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Datasheet
Introduction
1.2
References
Document
Number
Document
Intel® Celeron® M Processor Specification Update
300303
Mobile Intel® 945 Express Chipset Family Datasheet
309219
Mobile Intel® 945 Express Chipset Family Specification Update
309220
Intel® I/O Controller Hub 7 (ICH7) Family Datasheet
307013
Intel® I/O Controller Hub 7 (ICH7) Family Specification Update
307014
IA-32 Intel® Architecture Software Developer's Manual
http://
www.intel.com/
design/
pentium4/
manuals/
index_new.htm
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A- M
Volume 2B: Instruction Set Reference. N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
AP-485, Intel® Processor Identification and CPUID Instruction Application
Note
241618
§
Datasheet
9
Introduction
10
Datasheet
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Celeron M processor supports the C1/AutoHALT, C1/MWAIT, Stop Grant, Sleep, and
Deep Sleep for power management. See Figure 1 for a visual representation of package
level low-power states for the Celeron M processor. Package low power states include
Normal, Stop Grant, Stop Grant Snoop, Sleep and Deep Sleep. Refer Figure 2 for a
visual representation of the core low-power states for the Celeron M processor.
The Celeron M processor implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx
I/O reads are converted to equivalent MWAIT C-state requests inside the processor and
do not directly result in I/O reads on the processor FSB. The monitor address does not
need to be setup before using the P_LVLx I/O read interface. The sub-state hints used
for each P_LVLx read can be configured through the IA32_MISC_ENABLES model
specific register (MSR).
If the processor encounters a chipset break event while STPCLK# is asserted, it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that the processor should return to the Normal state.
Table 1.
Coordination of Core-Level Low Power States at the Package Level for the
Celeron M Processor
Core States
C0
Package States
Normal
C1(1)
Normal
C2
Stop Grant
C3
Deep Sleep
NOTE: (1)AutoHALT or MWAIT/C1
Figure 1.
Package-Level Low Power States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
SLP# de-asserted
STPCLK# de-asserted
Snoop
serviced
DPSLP# asserted
Deep
Sleep
Sleep
DPSLP# de-asserted
Snoop
occurs
Stop
Grant
Snoop
Datasheet
11
Low Power Features
Figure 2.
Core Low Power States
Stop
Grant
STPCLK#
asserted
STPCLK#
de-asserted
C1/
MWAIT
STPCLK#
de-asserted
STPCLK#
de-asserted
STPCLK#
asserted
Core state
break
STPCLK#
asserted
C1/Auto
Halt
HLT instruction
MWAIT(C1)
Halt break
C0
Core
state
break
P_LVL3 or
MWAIT(C3)
†
C3
P_LVL2 or
MWAIT(C2)
Core state
break
†
C2
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no affect if a core is in C2, or C3.
2.1.1
Core Low-Power States
2.1.1.1
C0 State
This is the normal operating state for the core of the Celeron M processor.
2.1.1.2
C1/AutoHALT Powerdown State
C1/AutoHALT is a low power state entered when the processor core executes the HALT
instruction. The processor core will transition to the C0 state upon the occurrence of
SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the
processor to immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the IA-32 Intel® Architecture Software
Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
will return execution to the HALT state.
While in AutoHALT Powerdown state the Celeron M processor will process only the bus
snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to
process the snoop and then return to the AutoHALT Powerdown state.
12
Datasheet
Low Power Features
2.1.1.3
C1/MWAIT Powerdown State
MWAIT is a low power state entered when the processor core executes the MWAIT
instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state
except that there is an additional event that can cause the processor core to return to
the C0 state: the Monitor event. See the IA-32 Intel® Architecture Software
Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.
2.1.1.4
Core C2 State
The core of the Celeron M processor can enter the C2 state by initiating a P_LVL2 I/O
read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop
Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
While in C2 state, the Celeron M processor will process only the bus snoops. The
processor core will enter a snoopable sub-state (not shown in Figure 2) to process the
snoop and then return to the C2 state.
2.1.1.5
Core C3 State
Core C3 state is a very low power state the processor core can enter while maintaining
context. The core of the Celeron M processor can enter the C3 state by initiating a
P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3
state the processor core flushes the contents of its L1 caches into the processor’s L2
cache. Except for the caches, the processor core maintains all its architectural state in
the C3 state. The Monitor remains armed if it is configured. All of the clocks in the
processor core are stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB. The processor core will transition to
the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI,
INTR), or FSB interrupt message. RESET# will cause the processor core to immediately
initialize itself.
2.1.2
Package Low Power States
The package level low power states are applicable for the Celeron M processor. All
package level low power states are described as follows:
2.1.2.1
Normal State
This is the normal operating state for the processor. The Celeron M processor enters the
Normal state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted the core of the Celeron M processor enters the StopGrant state within 20 bus clocks after the response phase of the processor-issued Stop
Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core
returns to the previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#,
DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET#
Datasheet
13
Low Power Features
deassertion (AC Specification T45). When re-entering the Stop-Grant state from the
Sleep state, STPCLK# should be deasserted ten or more bus clocks after the
deassertion of SLP# (AC Specification T75).
While in the Stop-Grant State, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT#, LINT[1:0] interrupts and
will serviced only upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch
interrupts delivered on the FSB.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the processor
should return to the Normal state.
A transition to the Stop Grant Snoop state will occur when the processor detects a
snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see
Section 2.1.2.4) will occur with the assertion of the SLP# signal.
2.1.2.3
Stop Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor will return
to the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
2.1.2.4
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through Stop-Grant State. If RESET# is driven active while the processor
is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately
after RESET# is asserted to ensure the processor correctly executes the Reset
sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
14
Datasheet
Low Power Features
2.1.2.5
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset based platforms with
the CK410M clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
2.2
FSB Low Power Enhancements
The Celeron M processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low VCCP (I/O termination voltage)
The Celeron M processor incorporates the DPWR# signal that controls the data bus
input buffers on the processor. The DPWR# signal disables the buffers when not used
and activates them only when data bus activity occurs, resulting in significant power
savings with no performance impact. BPRI# control also allows the processor address
and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic
Bus Parking allows a reciprocal power reduction in chipset address and control input
buffers when the processor deasserts its BR0# pin. The On Die Termination on the
processor FSB buffers is disabled when the signals are driven low, resulting in
additional power savings. The low I/O termination voltage is on a dedicated voltage
plane independent of the core voltage, enabling low I/O switching power at all times.
Datasheet
15
Low Power Features
2.3
Processor Power Status Indicator (PSI#) Signal
The Celeron M processor incorporates the PSI# signal that is asserted when the
processor is in a reduced power consumption state. PSI# can be used to improve
intermediate and light load efficiency of the voltage regulator, resulting in platform
power savings and extended battery life. The algorithm that the Celeron M processor
uses for determining when to assert PSI# is different from the algorithm used in
previous Celeron M processors. For more information, contact your Intel
Representative.
§
16
Datasheet
Electrical Specifications
3
Electrical Specifications
3.1
FSB (Front Side Bus) and GTLREF
Most Celeron M processor FSB signals use Advanced Gunning Transceiver Logic
(AGTL+) signalling technology. This signalling technology provides improved noise
margins and reduced ringing through low-voltage swings and controlled edge rates.
The termination voltage level for the Celeron M processor AGTL+ signals is VCCP =
1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity
and platform design methods have become more critical than with previous processor
families. Contact your Intel representative for more information on design guidelines
for the Celeron M processor FSB.
The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
system board. Termination resistors are provided on the processor silicon and are
terminated to its I/O voltage (VCCP). Intel® 945GMS and 940GML Express Chipsets will
also provide on-die termination, thus eliminating the need to terminate the bus on the
system board for most AGTL+ signals.
Refer to your Intel representative for board level termination resistor requirements.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system.
3.2
Power and Ground Pins
For clean, on-chip power distribution, the Celeron M processor will have a large number
of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power
planes while all VSS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. Please contact your
Intel representative for more details. The processor VCC pins must be supplied the
voltage determined by the VID (Voltage ID) pins.
3.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate.
Caution:
Datasheet
Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 6. Failure to do so can result
in timing violations or reduced lifetime of the component. For further information and
design guidelines, contact your Intel representative.
17
Electrical Specifications
3.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low effective series
resistance (ESR) and keep a low interconnect resistance from the regulator to the
socket. Bulk decoupling for the large current swings when the part is powering on, or
entering/exiting low-power states, must be provided by the voltage regulator solution.
It is strongly recommended that the layout and decoupling recommendations be
followed - for more details, contact your Intel representative.
3.3.2
FSB AGTL+ Decoupling
Celeron M processors integrate signal termination on the die as well as incorporate high
frequency decoupling capacitance on the processor package. Decoupling must also be
provided by the system motherboard for proper AGTL+ bus operation. For more
information, contact your Intel representative.
3.3.3
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the Celeron M processor core
frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor bus ratio
multiplier will be set at its default ratio at manufacturing. The Celeron M processor uses
a differential clocking implementation. For more information on Celeron M processor
clocking, contact your Intel representative.
3.4
Voltage Identification and Power Sequencing
Information regarding the VID specification for the Celeron M processor is available
from your Intel representative.
The Celeron M processor uses seven voltage identification pins, VID[6:0], to support
automatic selection of power supply voltages. The VID pins for Celeron M processor are
CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level
corresponding to the state of VID[6:0]. For more details about VR design to support the
Celeron M processor power supply requirements, please contact your Intel
representative.
Power source characteristics must be stable whenever the supply to the voltage
regulator is stable. Refer to the Figure 3 for timing details of the power-up sequence.
Figure 4 shows the power-down sequencing requirements.
18
Datasheet
Electrical Specifications
Table 2.
Datasheet
Voltage Identification Definition (Sheet 1 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC(V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
1
1
1.4625
0
0
0
0
1
0
0
1.4500
0
0
0
0
1
0
1
1.4375
0
0
0
0
1
1
0
1.4250
0
0
0
0
1
1
1
1.4125
0
0
0
1
0
0
0
1.4000
0
0
0
1
0
0
1
1.3875
0
0
0
1
0
1
0
1.3750
0
0
0
1
0
1
1
1.3625
0
0
0
1
1
0
0
1.3500
0
0
0
1
1
0
1
1.3375
0
0
0
1
1
1
0
1.3250
0
0
0
1
1
1
1
1.3125
0
0
1
0
0
0
0
1.3000
0
0
1
0
0
0
1
1.2875
0
0
1
0
0
1
0
1.2750
0
0
1
0
0
1
1
1.2625
0
0
1
0
1
0
0
1.2500
0
0
1
0
1
0
1
1.2375
0
0
1
0
1
1
0
1.2250
0
0
1
0
1
1
1
1.2125
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
19
Electrical Specifications
Table 2.
20
Voltage Identification Definition (Sheet 2 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC(V)
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
0
1
0
1
0
0
0
1.0000
0
1
0
1
0
0
1
0.9875
0
1
0
1
0
1
0
0.9750
0
1
0
1
0
1
1
0.9625
0
1
0
1
1
0
0
0.9500
0
1
0
1
1
0
1
0.9375
0
1
0
1
1
1
0
0.9250
0
1
0
1
1
1
1
0.9125
0
1
1
0
0
0
0
0.9000
0
1
1
0
0
0
1
0.8875
0
1
1
0
0
1
0
0.8750
0
1
1
0
0
1
1
0.8625
0
1
1
0
1
0
0
0.8500
0
1
1
0
1
0
1
0.8375
0
1
1
0
1
1
0
0.8250
0
1
1
0
1
1
1
0.8125
0
1
1
1
0
0
0
0.8000
0
1
1
1
0
0
1
0.7875
0
1
1
1
0
1
0
0.7750
0
1
1
1
0
1
1
0.7625
0
1
1
1
1
0
0
0.7500
0
1
1
1
1
0
1
0.7375
0
1
1
1
1
1
0
0.7250
0
1
1
1
1
1
1
0.7125
1
0
0
0
0
0
0
0.7000
1
0
0
0
0
0
1
0.6875
1
0
0
0
0
1
0
0.6750
1
0
0
0
0
1
1
0.6625
1
0
0
0
1
0
0
0.6500
1
0
0
0
1
0
1
0.6375
1
0
0
0
1
1
0
0.6250
1
0
0
0
1
1
1
0.6125
1
0
0
1
0
0
0
0.6000
1
0
0
1
0
0
1
0.5875
1
0
0
1
0
1
0
0.5750
Datasheet
Electrical Specifications
Table 2.
Datasheet
Voltage Identification Definition (Sheet 3 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC(V)
1
0
0
1
0
1
1
0.5625
1
0
0
1
1
0
0
0.5500
1
0
0
1
1
0
1
0.5375
1
0
0
1
1
1
0
0.5250
1
0
0
1
1
1
1
0.5125
1
0
1
0
0
0
0
0.5000
1
0
1
0
0
0
1
0.4875
1
0
1
0
0
1
0
0.4750
1
0
1
0
0
1
1
0.4625
1
0
1
0
1
0
0
0.4500
1
0
1
0
1
0
1
0.4375
1
0
1
0
1
1
0
0.4250
1
0
1
0
1
1
1
0.4125
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
1
1
0
0
0
0
0
0.3000
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
1
1
0
1
1
0
1
0.1375
1
1
0
1
1
1
0
0.1250
1
1
0
1
1
1
1
0.1125
1
1
1
0
0
0
0
0.1000
21
Electrical Specifications
Table 2.
Voltage Identification Definition (Sheet 4 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC(V)
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
1
1
1
0
1
1
0
0.0250
1
1
1
0
1
1
1
0.0125
1
1
1
1
0
0
0
0.0000
NOTE: A “1” in this table refers to a high-voltage level and a “0” refers to low-voltage level. Contact your Intel
representative for further information on BIOS VID programming.
3.5
Catastrophic Thermal Protection
The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal
protection. An external thermal sensor should also be used to protect the processor
and the system against excessive temperatures. Even with the activation of
THERMTRIP#, which halts all processor internal clocks and activity, leakage current can
be high enough such that the processor cannot be protected in all conditions without
the removal of power to the processor. If the external thermal sensor detects a
catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal
is asserted, the VCC supply to the processor must be turned off within 500 ms to
prevent permanent silicon damage due to thermal runaway of the processor.
3.6
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future Celeron M processors. See Section 4.4 for a pin listing of
the processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected.
Please contact your Intel representative for details on signal terminations and TAP
signal termination requirements.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via
1-kΩ, pull-down resistors. The TEST2 pin must have a 51-Ω ±5%, pull-down resistor to
VSS.
22
Datasheet
Electrical Specifications
3.7
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and Intel 945GMS
and 940GML Express Chipsets on the platform. The BSEL encoding for BCLK[1:0] is
shown in Table 3.
Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
3.8
BSEL[1]
BSEL[0]
BCLK
Frequency
L
L
L
RESERVED
L
L
H
133 MHz
L
H
L
RESERVED
L
H
H
RESERVED
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+
Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 4 identifies which signals are common clock, source synchronous,
and asynchronous.
Datasheet
23
Electrical Specifications
Table 4.
FSB Pin Groups
Signals1
Signal Group
Type
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, DPWR#, PREQ#, RESET#,
RS[2:0]#, TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#,
DRDY#, HIT#, HITM#, LOCK#, PRDY#3
Signals
AGTL+ Source Synchronous
I/O
Synchronous
to assoc.
strobe
Associated Strobe
REQ[4:0]#,
A[16:3]#
ADSTB[0]#
A[31:17]#
ADSTB[1]#
D[15:0]#, DINV0#
DSTBP0#, DSTBN0#
D[31:16]#, DINV1#
DSTBP1#, DSTBN1#
D[47:32]#, DINV2#
DSTBP2#, DSTBN2#
D[63:48]#, DINV3#
DSTBP3#, DSTBN3#
AGTL+ Strobes
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input
Asynchronous
A20M#, DPRSTP# (not used), DPSLP#, IGNNE#,
INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD,
SMI#, SLP#, STPCLK#
Open Drain Output
Asynchronous
FERR#, IERR#, THERMTRIP#
Open Drain I/O
Asynchronous
PROCHOT#4
CMOS Output
Asynchronous
PSI#, VID[6:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
FSB Clock
Clock
Power/Other
TDO
BCLK[1:0]
COMP[3:0], DBR#2, GTLREF, RSVD, TEST2,
TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP,
VCCSENSE, VSS, VSSSENSE
NOTES:
1.
Refer to Chapter 4 for signal descriptions and termination requirements.
2.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
BPM[2:1]# and PRDY# are AGTL+ output only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
24
Datasheet
Electrical Specifications
3.9
CMOS Signals
CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for at least three BCLKs in order for
the processor to recognize them. See Section 3.11 for the DC specifications for the
CMOS signal groups.
3.10
Maximum Ratings
Table 5 specifies absolute maximum and minimum ratings. Only within specified
operation limits, can functionality and long-term reliability be expected.
At condition outside functional operation condition limits, but within absolute maximum
and minimum ratings, neither functionality nor long term reliability can be expected. If
a device is returned to conditions within functional operation limits after having been
subjected to conditions outside these limits, but within the absolute maximum and
minimum ratings, the device may be functional, but with its lifetime degraded on
exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from electro static
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
Table 5.
Symbol
Processor DC Absolute Maximum Ratings
Parameter
TSTORAGE
Processor Storage Temperature
Min
Max
Unit
-40
85
°C
Notes
2
VCC
Any Processor Supply Voltage with Respect to VSS
-0.3
1.6
V
1
VinAGTL+
AGTL+ Buffer DC Input Voltage with Respect to VSS
-0.3
1.6
V
1, 2
VinAsynch_CMOS
CMOS Buffer DC Input Voltage with Respect to VSS
-0.3
1.6
V
1, 2
NOTES:
1.
This rating applies to any processor pin.
2.
Contact Intel for storage requirements in excess of one year.
3.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and
signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group.
The DC specifications for these signals are listed in Table 9. DC specifications for the
CMOS group are listed in Table 10.
Table 9 through Table 11 list the DC specifications for the Celeron M processor and are
valid only while meeting specifications for junction temperature, clock frequency, and
input voltages. Active mode load line specifications apply in all states except in the
Deep Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at
Datasheet
25
Electrical Specifications
power up in order to set the VID values. Unless specified otherwise, all specifications
for the Celeron M processor are at Tjunction = 100°C. Care should be taken to read all
notes associated with each parameter.
Table 6.
Voltage and Current Specifications for the Celeron M Processor Standard
Voltage
Symbol
Parameter
VCC
VCC of Core
VCC,BOOT
Default VCC Voltage for Initial Power Up
VCCP
AGTL+ Termination Voltage
VCCA
ICCDES
Min
Typ
1.0
PLL Supply Voltage
ICC for Processors
Recommended Design Target
Max
Unit
1.3
V
1, 2
V
2, 8
2
1.20
Notes
0.997
1.05
1.102
V
1.425
1.5
1.575
V
36
A
5
A
3,4
A
3,4
ICC Core Processors
ICC
Processor
Number:
Core Frequency/Voltage
450
2.00 GHz and VCC
29
1.86 GHz and VCC
29
1.73 GHz and VCC
29
1.60 GHz and VCC
29
1.46 GHz and VCC
29
440
430
420
410
IAH,
ISGNT
ICC Auto-Halt & Stop-Grant
16.5
ISLP
ICC Sleep
16.4
A
3,4
IDSLP
ICC Deep Sleep
14.7
A
3,4
dICC/DT
VCC Power Supply Current Slew Rate at CPU
Package Pin
600
A/µs
6, 7
ICCA
ICC for VCCA Supply
120
mA
ICC for VCCP Supply before VCC Stable
6.0
A
9
ICC for VCCP Supply after VCC Stable
2.5
A
10
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during
manufacturing such that two processors at the same frequency may have different settings within the VID
range.
2.
The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a
100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled in the scope probe.
3.
Specified at 100°C Tj.
4.
Specified at the VID voltage.
5.
The ICCDES(max) specification of 36 A comprehends only Celeron M processor on 65 nm process.
6.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7.
Measured at the bulk capacitors on the motherboard.
8.
VCC, BOOT tolerance is shown in Figure 3.
9.
This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC_CORE are high.
10.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
11.
Specified at the nominal VCC.
26
Datasheet
Electrical Specifications
Table 7.
Voltage and Current Specifications for the Celeron M Processor Ultra Low
Voltage
Symbol
Parameter
VCC
VCC
VCC,BOOT
Default VCC Voltage for Initial Power Up
VCCP
AGTL+ Termination Voltage
VCCA
ICCDES
Min
Typ
0.85
PLL Supply Voltage
ICC for Recommended Design Target
Max
Unit
1.10
V
1, 2
1.20
Notes
V
2, 8
0.997
1.05
1.102
V
2
1.425
1.5
1.575
V
8
A
5
A
3,4
ICC
ICC
Processor
Number:
Core Frequency/Voltage:
443
1.20 GHz at VCC
423
IAH,
1.06 GHz at VCC
8.2
8.2
ICC Auto-Halt & Stop-Grant
4.6
A
3,4
ISLP
ICC Sleep
4.5
A
3,4
IDSLP
ICC Deep Sleep
3.6
A
3,4
dICC/DT
VCC Power Supply Current Slew Rate at CPU
Package Pin
600
A/µs
6, 7
ICCA
ICC for VCCA Supply
120
mA
ICC for VCCP Supply before Vcc Stable
6.0
A
9
ICC for VCCP Supply after Vcc Stable
2.5
A
10
ISGNT
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during
manufacturing such that two processors at the same frequency may have different settings within the VID
range.
2.
The voltage specifications are assumed to be measured across VCCSENSE and VSSSENSE pins at socket with a
100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled in the scope probe.
3.
Specified at 100 °C Tj.
4.
Specified at the VID voltage.
5.
The ICCDES(max) specification of 8 A comprehends only the Celeron M processor ULV and the value is
based on pre-silicon estimates.
6.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7.
Measured at the bulk capacitors on the motherboard.
8.
VCC, BOOT tolerance is shown in Figure 3.
9.
This is a steady-state ICCP current specification, which is applicable when both VCCP and VCC_CORE are high.
10.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
Datasheet
27
Electrical Specifications
Figure 3.
Active VCC and ICC Loadline for the Celeron M Processor Standard Voltage
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC [V]
VCC max
VCC, DC max
10mV= RIPPLE
VCC nom
VCC, DC min
VCC min
+/-VCC nom * 1.5%
= VR St. Pt. Error 1/
ICC [A]
0
ICC max
Note 1/ V C C Set Poi nt Error Tol erance i s per below :
Tolerance
--------------+/-1.5%
+/ -11.5mV
Figure 4.
V C C Active Mode VID Code Range
-------------------------------------------------------V C C > 0.7500 V (VID 0111100).
V C C < 0.7500 V (VID 0111100)
Active VCC and ICC Loadline for the Celeron M Processor Ultra Low Voltage
V CC-CORE [V]
Slope = -5.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
V CC max
V CC- DC max
10mV= RIPPLE
V CC nom
V CC-DC min
V CC min
+/-V CC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
N ote 1/ VCC Set Point Error Tolerance is per below :
T oleranc e
V CC V ID V o ltage R an ge
--------------- -------------------------------------------------------+/-1.5%
V CC > 0.7500V
+/-11.5m V
28
0.75000 V < VCC < 0.5000V
Datasheet
Electrical Specifications
Table 8.
Symbol
FSB Differential BCLK Specifications
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
VCROSS
Crossing Voltage
ΔVCROSS
Range of Crossing Points
VTH
Threshold Region
ILI
Input Leakage Current
Cpad
Pad Capacitance
Min
Typ
0.660
0.25
Notes1
Max
Unit
0.710
0.85
V
0.35
0.55
V
2
0.14
V
6
VCROSS+0.100
V
3
±100
µA
4
1.45
pF
5
0
VCROSS -0.100
0.95
1.2
V
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3.
Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
4.
For Vin between 0 V and VIH.
5.
Cpad includes die capacitance only. No package parasitics are included.
6.
ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Table 9.
Symbol
VCCP
AGTL+ Signal Group DC Specifications
Parameter
I/O Voltage
Typ
Max
Unit
0.997
1.05
1.102
V
V
6
VCCP+0.1
V
3,6
GTLREF-0.1
V
2,4
GTLREF
Reference Voltage
VIH
Input High Voltage
GTLREF+0.1
VIL
Input Low Voltage
-0.1
VOH
Output High Voltage
RTT
Termination Resistance
RON
Buffer on Resistance
ILI
Input Leakage Current
Cpad1
Pad Capacitance
Notes1
Min
2/3 VCCP
0
VCCP
6
50
55
61
Ω
7,10
22.3
25.5
28.7
Ω
5
±100
µA
8
2.75
pF
9
1.8
2.3
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4.
VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications.
5.
This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT.
6.
GTLREF should be generated from VCCP with a 1% tolerance resistor divider. Tolerance of resistor divider
decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP.
7.
RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
8.
Specified with on die RTT and RON are turned off.
9.
Cpad includes die capacitance only. No package parasitics are included.
10.
This spec applies to all AGTL+ signals except for PREQ#. RTT for PREQ# is between 1.5 kΩ to 6.0 kΩ.
Datasheet
29
Electrical Specifications
.
Table 10.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
1.05
1.10
V
Notes1
VCCP
I/O Voltage
1.0
VIL
Input Low Voltage - CMOS
-0.1
0.0
0.33
V
2, 3
VIH
Input High Voltage
0.7
1.05
1.20
V
2
VOL
Output Low Voltage
-0.1
0
0.11
V
2
VOH
Output High Voltage
0.9
VCCP
1.20
V
2
IOL
Output Low Current
1.3
4.1
mA
4
IOH
Output High Current
1.3
4.1
mA
5
ILI
Input Leakage Current
±100
µA
6
Cpad1
Pad Capacitance
Cpad2
Pad Capacitance for CMOS Input
1.8
2.3
2.75
pF
7
0.95
1.2
1.45
pF
8
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The VCCP referred to in these specifications refers to instantaneous VCCP.
3.
Refer to the processor I/O Buffer Models for I/V characteristics.
4.
Measured at 0.1*VCCP.
5.
Measured at 0.9*VCCP.
6.
For Vin between 0 V and VCCP. Measured when the driver is tristated.
7.
Cpad1 includes die capacitance only for DPSLP#,PWRGOOD. No package parasitics are included.
8.
Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
Table 11.
Symbol
Open Drain Signal Group DC Specifications
Parameter
Min
Typ
Max
Unit
Notes1
1.05
1.10
V
3
VOH
Output High Voltage
1.0
VOL
Output Low Voltage
0
0.20
V
IOL
Output Low Current
11.40
50
mA
±200
µA
4
2.75
pF
5
ILeak
Output Leakage Current
Cpad
Pad Capacitance
1.8
2.3
2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at 0.2*VCCP.
3.
VOH is determined by value of the external pull-up resistor to VCCP. Please contact your Intel representative
for details.
4.
For Vin between 0 V and VOH.
5.
Cpad includes die capacitance only. No package parasitics are included.
§
30
Datasheet
Package Mechanical Specifications and Pin Information
4
Package Mechanical
Specifications and Pin
Information
The Celeron M processor is available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA
packages. The package mechanical dimensions, keep-out zones, loading specifications,
and mass specifications are shown in Figure 5 through Figure 8. Table 12 shows a topview of package pinout with their functionalities.
Caution:
The Micro-FCBGA package incorporates land-side capacitors. Avoid contacting the
capacitors with other electrically conductive materials on the motherboard. Doing so
may short the capacitors, and possibly damage the device or render it inactive.
4.1
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. The location and quantity of capacitors may change, but
will remain within the component keep-in.
4.2
Package Loading Specifications
Maximum package loading specifications are static compressive loading in the direction
normal to the processor. This maximum load limit should not be exceeded during
shipping conditions, standard use condition, or by thermal solution. In addition, there
are additional load limitations against transient bend, shock, and tensile loading, all of
which can be obtained by contacting your field support. Moreover, the processor
package substrate should not be used as a mechanical reference or load-bearing
surface for thermal and mechanical solution.
4.3
Processor Mass Specifications
The typical mass of the processor is given in Figure 5 and Figure 8. This mass includes
all the components that are included in the package.
Datasheet
31
Package Mechanical Specifications and Pin Information
Figure 5.
32
Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
Datasheet
Package Mechanical Specifications and Pin Information
Figure 6.
Datasheet
Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
33
Package Mechanical Specifications and Pin Information
Figure 7.
34
Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)
Datasheet
Package Mechanical Specifications and Pin Information
Figure 8.
Datasheet
Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)
35
Package Mechanical Specifications and Pin Information
4.4
Processor Pinout and Pin List
Table 12 shows the top view pinout of the Celeron M processor. The pin list arranged in
two different formats is shown in the following pages.
Table 12.
The Coordinates of the Processor Pins As Viewed from the Top of the Package
(Sheet 1 of 2)
1
2
3
SMI#
RESET#
RSVD
INIT#
RSVD
IGNNE
#
A
B
C
D
RSVD
VSS
VSS
RSVD
RSVD
4
5
6
7
8
9
10
11
12
13
VSS
FERR#
A20M#
VCC
VSS
VCC
VCC
VSS
VCC
VCC
A
LINT1
DPSLP#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
B
VSS
LINT0
THERM
TRIP#
VSS
VCC
VCC
VSS
VCC
VCC
C
VSS
STPCLK
#
PWRGO
OD
SLP#
VSS
VCC
VCC
VSS
VCC
VSS
D
E
DBSY#
BNR#
VSS
HITM#
DPRSTP
#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
E
F
BR0#
VSS
RS[0]#
RS[1]#
VSS
RSVD
VCC
VSS
VCC
VCC
VSS
VCC
VSS
F
G
VSS
TRDY#
RS[2]#
VSS
BPRI#
HIT#
G
ADS#
REQ[1]
#
VSS
LOCK#
DEFER#
VSS
H
A[9]#
VSS
REQ[3]
#
A[3]#
VSS
VCCP
J
VSS
REQ[2]
#
REQ[0]
#
VSS
A[6]#
VCCP
K
L
A[13]#
ADSTB[
0]#
VSS
A[4]#
REQ[4]
#
VSS
L
M
A[7]#
VSS
A[5]#
RSVD
VSS
VCCP
M
N
VSS
A[8]#
A[10]#
VSS
RSVD
VCCP
N
P
A[15]#
A[12]#
VSS
A[14]#
A[11]#
VSS
P
R
A[16]#
VSS
A[19]#
A[24]#
VSS
VCCP
R
H
J
K
T
VSS
RSVD
A[26]#
VSS
A[25]#
VCCP
T
U
COMP[2]
A[23]#
VSS
A[21]#
A[18]#
VSS
U
V
COMP[3]
VSS
RSVD
ADSTB
[1]#
VSS
VCCP
V
W
VSS
A[30]#
A[27]#
VSS
A[28]#
A[20]#
W
Y
A[31]#
A[17]#
VSS
A[29]#
A[22]#
VSS
Y
AA
RSVD
VSS
RSVD
RSVD
VSS
TDI
VCC
VSS
VCC
VCC
VSS
VCC
VCC
AA
AB
VSS
RSVD
TDO
VSS
TMS
TRST#
VCC
VSS
VCC
VCC
VSS
VCC
VSS
AB
PRDY#
VSS
BPM[3]
#
TCK
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
AC
VSS
BPM[1]
#
BPM[0]
#
VSS
VID[0]
VCC
VSS
VCC
VCC
VSS
VCC
VSS
AD
PSI#
VSS
SENSE
VSS
VCC
VCC
VSS
VCC
VCC
AE
VSS
VCC
VCC
VSS
VCC
VSS
AF
8
9
10
11
12
13
AC
AD
AE
AF
36
PREQ#
BPM[2]#
VSS
VID[6]
VID[4]
VSS
VID[2]
RSVD
VID[5]
VSS
VID[3]
VID[1]
VSS
VCC
SENSE
1
2
3
4
5
6
7
Datasheet
Package Mechanical Specifications and Pin Information
Table 12. The Coordinates of the Processor Pins As Viewed from the Top of the Package
(Sheet 2 of 2)
14
15
16
17
18
19
20
21
22
23
24
25
26
A
VSS
VCC
VSS
VCC
VCC
VSS
VCC
BCLK[1]
BCLK[0]
VSS
THRMDA
THRMDC
VSS
A
B
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
BSEL[0]
BSEL[1]
VSS
RSVD
VCCA
B
C
VSS
VCC
VSS
VCC
VCC
VSS
DBR#
BSEL[2]
VSS
RSVD
RSVD
VSS
TEST1
C
RSVD
VSS
DPWR#
TEST2
VSS
D
D[0]#
D[7]#
VSS
D[6]#
D[2]#
E
D
VCC
VCC
VSS
VCC
VCC
VSS
IERR#
PROC
HOT#
E
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
F
VCC
VCC
VSS
VCC
VCC
VSS
VCC
DRDY#
VSS
D[4]#
D[1]#
VSS
D[13]#
F
VCCP
DSTBP[0]
#
VSS
D[9]#
D[5]#
VSS
G
G
H
VSS
D[3]#
DSTBN[0]
#
VSS
D[15]#
D[12]#
H
J
VCCP
VSS
D[11]#
D[10]#
VSS
DINV[0
]#
J
K
VCCP
D[14]#
VSS
D[8]#
D[17]#
VSS
K
L
VSS
D[21]#
D[22]#
VSS
D[20]#
D[29]#
L
M
M
VCCP
VSS
D[23]#
DSTBN[1]
#
VSS
DINV[1
]#
N
VCCP
D[16]#
VSS
D[31]#
DSTBP[1]
#
VSS
N
P
VSS
D[25]#
D[26]#
VSS
D[24]#
D[18]#
P
VSS
COMP
[0]
R
R
VCCP
VSS
D[19]#
D[28]#
T
VCCP
RSVD
VSS
D[27]#
D[30]#
VSS
T
U
VSS
D[39]#
D[37]#
VSS
D[38]#
COMP
[1]
U
V
VCCP
VSS
DINV[2]#
D[34]#
VSS
D[35]#
V
VSS
DSTBN[2]
#
D[36]#
VSS
W
D[44]#
Y
W
VCCP
Y
D[41]#
VSS
D[45]#
D[42]#
VSS
DSTBP[2]
#
AA
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[51]#
VSS
D[32]#
D[47]#
VSS
D[43]#
A
A
AB
VCC
VCC
VSS
VCC
VCC
VSS
VCC
D[52]#
D[50]#
VSS
D[33]#
D[40]#
VSS
A
B
AC
VSS
VCC
VSS
VCC
VCC
VSS
DINV[3
]#
VSS
D[48]#
D[49]#
VSS
D[53]#
D[46]#
AC
A
D
VCC
VCC
VSS
VCC
VCC
VSS
D[54]#
D[59]#
VSS
DSTBN[3]
#
D[57]#
VSS
GTLREF
A
D
AE
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[58]#
D[55]#
VSS
DSTBP[3]
#
D[60]#
VSS
AE
AF
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[62]#
D[56]#
VSS
D[61]#
D[63]#
AF
14
15
16
17
18
19
20
21
22
23
24
25
26
Datasheet
37
Package Mechanical Specifications and Pin Information
This page intentionally left blank.
38
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
A[3]#
J4
Source Synch
Input/
Output
A[4]#
L4
Source Synch
Input/
Output
A[5]#
M3
Source Synch
Input/
Output
Source Synch
Input/
Output
A[6]#
K5
A[7]#
M1
Source Synch
Input/
Output
A[8]#
N2
Source Synch
Input/
Output
A[9]#
J1
Source Synch
Input/
Output
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
A[25]#
T5
Source Synch
Input/
Output
A[26]#
T3
Source Synch
Input/
Output
A[27]#
W3
Source Synch
Input/
Output
A[28]#
W5
Source Synch
Input/
Output
A[29]#
Y4
Source Synch
Input/
Output
A[30]#
W2
Source Synch
Input/
Output
A[31]#
Y1
Source Synch
Input/
Output
A20M#
A6
CMOS
Input
ADS#
H1
Common
Clock
Input/
Output
A[10]#
N3
Source Synch
Input/
Output
A[11]#
P5
Source Synch
Input/
Output
ADSTB[0]#
L2
Source Synch
A[12]#
P2
Source Synch
Input/
Output
Input/
Output
ADSTB[1]#
V4
Source Synch
A[13]#
L1
Source Synch
Input/
Output
Input/
Output
BCLK[0]
A22
Bus Clock
Input
BCLK[1]
A21
Bus Clock
Input
BNR#
E2
Common
Clock
Input/
Output
BPM[0]#
AD4
Common
Clock
Input/
Output
BPM[1]#
AD3
Common
Clock
Output
BPM[2]#
AD1
Common
Clock
Output
BPM[3]#
AC4
Common
Clock
Input/
Output
BPRI#
G5
Common
Clock
Input
BR0#
F1
Common
Clock
Input/
Output
BSEL[0]
B22
CMOS
Output
BSEL[1]
B23
CMOS
Output
BSEL[2]
C21
CMOS
Output
COMP[0]
R26
Power/Other
Input/
Output
A[14]#
A[15]#
A[16]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
Source Synch
Source Synch
Input/
Output
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
A[23]#
U2
Source Synch
Input/
Output
A[24]#
R4
Source Synch
Input/
Output
Datasheet
39
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
COMP[1]
U26
Power/Other
Input/
Output
D[19]#
R23
Source Synch
Input/
Output
COMP[2]
U1
Power/Other
Input/
Output
D[20]#
L25
Source Synch
Input/
Output
COMP[3]
V1
Power/Other
Input/
Output
D[21]#
L22
Source Synch
Input/
Output
D[0]#
E22
Source Synch
Input/
Output
D[22]#
L23
Source Synch
Input/
Output
D[1]#
F24
Source Synch
Input/
Output
D[23]#
M23
Source Synch
Input/
Output
D[2]#
E26
Source Synch
Input/
Output
D[24]#
P25
Source Synch
Input/
Output
D[3]#
H22
Source Synch
Input/
Output
D[25]#
P22
Source Synch
Input/
Output
D[4]#
F23
Source Synch
Input/
Output
D[26]#
P23
Source Synch
Input/
Output
D[5]#
G25
Source Synch
Input/
Output
D[27]#
T24
Source Synch
Input/
Output
D[6]#
E25
Source Synch
Input/
Output
D[28]#
R24
Source Synch
Input/
Output
D[7]#
E23
Source Synch
Input/
Output
D[29]#
L26
Source Synch
Input/
Output
D[8]#
K24
Source Synch
Input/
Output
D[30]#
T25
Source Synch
Input/
Output
D[9]#
G24
Source Synch
Input/
Output
D[31]#
N24
Source Synch
Input/
Output
D[10]#
J24
Source Synch
Input/
Output
D[32]#
AA23
Source Synch
Input/
Output
D[11]#
J23
Source Synch
Input/
Output
D[33]#
AB24
Source Synch
Input/
Output
D[12]#
H26
Source Synch
Input/
Output
D[34]#
V24
Source Synch
Input/
Output
D[13]#
F26
Source Synch
Input/
Output
D[35]#
V26
Source Synch
Input/
Output
D[14]#
K22
Source Synch
Input/
Output
D[36]#
W25
Source Synch
Input/
Output
D[15]#
H25
Source Synch
Input/
Output
D[37]#
U23
Source Synch
Input/
Output
D[16]#
N22
Source Synch
Input/
Output
D[38]#
U25
Source Synch
Input/
Output
D[17]#
K25
Source Synch
Input/
Output
D[39]#
U22
Source Synch
Input/
Output
D[18]#
P26
Source Synch
Input/
Output
D[40]#
AB25
Source Synch
Input/
Output
40
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
D[41]#
W22
Source Synch
Input/
Output
D[42]#
Y23
Source Synch
Input/
Output
D[43]#
AA26
Source Synch
Input/
Output
D[44]#
Y26
Source Synch
Input/
Output
Source Synch
Input/
Output
Source Synch
Input/
Output
D[45]#
D[46]#
Y22
AC26
D[47]#
AA24
Source Synch
Input/
Output
D[48]#
AC22
Source Synch
Input/
Output
Source Synch
Input/
Output
D[49]#
AC23
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Input/
Output
D[63]#
AF26
Source Synch
DBR#
C20
CMOS
Output
DBSY#
E1
Common
Clock
Input/
Output
DEFER#
H5
Common
Clock
Input
DINV[0]#
J26
Source Synch
Input/
Output
DINV[1]#
M26
Source Synch
Input/
Output
DINV[2]#
V23
Source Synch
Input/
Output
DINV[3]#
AC20
Source Synch
Input/
Output
DPRSTP#
E5
CMOS
Not used
DPSLP#
B5
CMOS
Input
Input
D[50]#
AB22
Source Synch
Input/
Output
DPWR#
D24
Common
Clock
D[51]#
AA21
Source Synch
Input/
Output
DRDY#
F21
Common
Clock
Input/
Output
D[52]#
AB21
Source Synch
Input/
Output
DSTBN[0]#
H23
Source Synch
Input/
Output
D[53]#
AC25
Source Synch
Input/
Output
DSTBN[1]#
M24
Source Synch
Input/
Output
D[54]#
AD20
Source Synch
Input/
Output
DSTBN[2]#
W24
Source Synch
Input/
Output
D[55]#
AE22
Source Synch
Input/
Output
DSTBN[3]#
AD23
Source Synch
Input/
Output
D[56]#
AF23
Source Synch
Input/
Output
DSTBP[0]#
G22
Source Synch
Input/
Output
D[57]#
AD24
Source Synch
Input/
Output
DSTBP[1]#
N25
Source Synch
Input/
Output
D[58]#
AE21
Source Synch
Input/
Output
DSTBP[2]#
Y25
Source Synch
Input/
Output
D[59]#
AD21
Source Synch
Input/
Output
DSTBP[3]#
AE24
Source Synch
Input/
Output
A5
Open Drain
Output
AE25
Source Synch
Input/
Output
FERR#
D[60]#
GTLREF
AD26
Power/Other
Input
HIT#
G6
Common
Clock
Input/
Output
HITM#
E4
Common
Clock
Input/
Output
D[61]#
AF25
Source Synch
Input/
Output
D[62]#
AF22
Source Synch
Input/
Output
Datasheet
41
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
IERR#
D20
Open Drain
Output
RSVD
AA1
Reserved
IGNNE#
C4
CMOS
Input
RSVD
AA4
Reserved
INIT#
B3
CMOS
Input
RSVD
AB2
Reserved
LINT0
C6
CMOS
Input
RSVD
AA3
Reserved
LINT1
B4
CMOS
Input
RSVD
M4
Reserved
LOCK#
H4
Common
Clock
Input/
Output
RSVD
N5
Reserved
RSVD
T2
Reserved
AC2
Common
Clock
Output
RSVD
V3
Reserved
RSVD
B2
Reserved
RSVD
C3
Reserved
RSVD
T22
Reserved
RSVD
B25
Reserved
SLP#
D7
CMOS
Input
SMI#
A3
CMOS
Input
STPCLK#
D5
CMOS
Input
PRDY#
PREQ#
AC1
Common
Clock
Input
PROCHOT#
D21
Open Drain
Input/
Output
PSI#
AE6
CMOS
Output
PWRGOOD
D6
CMOS
Input
REQ[0]#
K3
Source Synch
Input/
Output
REQ[1]#
H2
Source Synch
Input/
Output
REQ[2]#
K2
Source Synch
Input/
Output
Source Synch
Input/
Output
REQ[3]#
J3
REQ[4]#
L5
Source Synch
Input/
Output
RESET#
B1
Common
Clock
Input
RS[0]#
F3
Common
Clock
Input
F4
Common
Clock
Input
RS[2]#
G3
Common
Clock
Input
RSVD
D2
Reserved
RS[1]#
RSVD
F6
Reserved
RSVD
D3
Reserved
RSVD
C1
Reserved
RSVD
AF1
Reserved
RSVD
D22
Reserved
RSVD
C23
Reserved
RSVD
C24
Reserved
42
TCK
AC5
CMOS
Input
TDI
AA6
CMOS
Input
TDO
AB3
Open Drain
Output
TEST1
C26
Test
TEST2
D25
Test
THERMDA
A24
Power/Other
THERMDC
A25
Power/Other
THERMTRIP
#
C7
Open Drain
Output
TMS
AB5
CMOS
Input
TRDY#
G2
Common
Clock
Input
TRST#
AB6
CMOS
Input
VCC
AB20
Power/Other
VCC
AA20
Power/Other
VCC
AF20
Power/Other
VCC
AE20
Power/Other
VCC
AB18
Power/Other
VCC
AB17
Power/Other
VCC
AA18
Power/Other
VCC
AA17
Power/Other
VCC
AD18
Power/Other
VCC
AD17
Power/Other
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
VCC
AC18
Power/Other
VCC
AA7
Power/Other
VCC
AC17
Power/Other
VCC
AD7
Power/Other
VCC
AF18
Power/Other
VCC
AC7
Power/Other
VCC
AF17
Power/Other
VCC
B20
Power/Other
VCC
AE18
Power/Other
VCC
A20
Power/Other
VCC
AE17
Power/Other
VCC
F20
Power/Other
VCC
AB15
Power/Other
VCC
E20
Power/Other
VCC
AA15
Power/Other
VCC
B18
Power/Other
VCC
AD15
Power/Other
VCC
B17
Power/Other
VCC
AC15
Power/Other
VCC
A18
Power/Other
VCC
AF15
Power/Other
VCC
A17
Power/Other
VCC
AE15
Power/Other
VCC
D18
Power/Other
VCC
AB14
Power/Other
VCC
D17
Power/Other
VCC
AA13
Power/Other
VCC
C18
Power/Other
VCC
AD14
Power/Other
VCC
C17
Power/Other
VCC
AC13
Power/Other
VCC
F18
Power/Other
VCC
AF14
Power/Other
VCC
F17
Power/Other
VCC
AE13
Power/Other
VCC
E18
Power/Other
VCC
AB12
Power/Other
VCC
E17
Power/Other
VCC
AA12
Power/Other
VCC
B15
Power/Other
VCC
AD12
Power/Other
VCC
A15
Power/Other
VCC
AC12
Power/Other
VCC
D15
Power/Other
VCC
AF12
Power/Other
VCC
C15
Power/Other
VCC
AE12
Power/Other
VCC
F15
Power/Other
VCC
AB10
Power/Other
VCC
E15
Power/Other
VCC
AB9
Power/Other
VCC
B14
Power/Other
VCC
AA10
Power/Other
VCC
A13
Power/Other
VCC
AA9
Power/Other
VCC
D14
Power/Other
VCC
AD10
Power/Other
VCC
C13
Power/Other
VCC
AD9
Power/Other
VCC
F14
Power/Other
VCC
AC10
Power/Other
VCC
E13
Power/Other
VCC
AC9
Power/Other
VCC
B12
Power/Other
VCC
AF10
Power/Other
VCC
A12
Power/Other
VCC
AF9
Power/Other
VCC
D12
Power/Other
VCC
AE10
Power/Other
VCC
C12
Power/Other
VCC
AE9
Power/Other
VCC
F12
Power/Other
VCC
AB7
Power/Other
VCC
E12
Power/Other
Datasheet
Direction
43
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
VCC
B10
Power/Other
VID[3]
AF4
CMOS
Output
VCC
B9
Power/Other
VID[4]
AE3
CMOS
Output
VCC
A10
Power/Other
VID[5]
AF2
CMOS
Output
VCC
A9
Power/Other
VID[6]
AE2
CMOS
Output
VCC
D10
Power/Other
VSS
AB26
Power/Other
VCC
D9
Power/Other
VSS
AA25
Power/Other
VCC
C10
Power/Other
VSS
AD25
Power/Other
VCC
C9
Power/Other
VSS
AE26
Power/Other
VCC
F10
Power/Other
VSS
AB23
Power/Other
VCC
F9
Power/Other
VSS
AC24
Power/Other
VCC
E10
Power/Other
VSS
AF24
Power/Other
VCC
E9
Power/Other
VSS
AE23
Power/Other
VCC
B7
Power/Other
VSS
AA22
Power/Other
VCC
A7
Power/Other
VSS
AD22
Power/Other
VCC
F7
Power/Other
VSS
AC21
Power/Other
VCC
E7
Power/Other
VSS
AF21
Power/Other
VCCA
B26
Power/Other
VSS
AB19
Power/Other
VCCP
K6
Power/Other
VSS
AA19
Power/Other
VCCP
J6
Power/Other
VSS
AD19
Power/Other
VCCP
M6
Power/Other
VSS
AC19
Power/Other
VCCP
N6
Power/Other
VSS
AF19
Power/Other
VCCP
T6
Power/Other
VSS
AE19
Power/Other
VCCP
R6
Power/Other
VSS
AB16
Power/Other
VCCP
K21
Power/Other
VSS
AA16
Power/Other
VCCP
J21
Power/Other
VSS
AD16
Power/Other
VCCP
M21
Power/Other
VSS
AC16
Power/Other
VCCP
N21
Power/Other
VSS
AF16
Power/Other
VCCP
T21
Power/Other
VSS
AE16
Power/Other
VCCP
R21
Power/Other
VSS
AB13
Power/Other
VCCP
V21
Power/Other
VSS
AA14
Power/Other
VCCP
W21
Power/Other
VSS
AD13
Power/Other
VCCP
V6
Power/Other
VSS
AC14
Power/Other
VCCP
G21
Power/Other
VSS
AF13
Power/Other
VCCSENSE
AF7
Power/Other
VSS
AE14
Power/Other
VID[0]
AD6
CMOS
Output
VSS
AB11
Power/Other
VID[1]
AF5
CMOS
Output
VSS
AA11
Power/Other
VID[2]
AE5
CMOS
Output
VSS
AD11
Power/Other
44
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
VSS
AC11
Power/Other
VSS
H3
Power/Other
VSS
AF11
Power/Other
VSS
G4
Power/Other
VSS
AE11
Power/Other
VSS
K4
Power/Other
VSS
AB8
Power/Other
VSS
L3
Power/Other
VSS
AA8
Power/Other
VSS
P3
Power/Other
VSS
AD8
Power/Other
VSS
N4
Power/Other
VSS
AC8
Power/Other
VSS
T4
Power/Other
VSS
AF8
Power/Other
VSS
U3
Power/Other
VSS
AE8
Power/Other
VSS
Y3
Power/Other
VSS
AA5
Power/Other
VSS
W4
Power/Other
VSS
AD5
Power/Other
VSS
D1
Power/Other
VSS
AC6
Power/Other
VSS
C2
Power/Other
VSS
AF6
Power/Other
VSS
F2
Power/Other
VSS
AB4
Power/Other
VSS
G1
Power/Other
VSS
AC3
Power/Other
VSS
K1
Power/Other
VSS
AF3
Power/Other
VSS
J2
Power/Other
VSS
AE4
Power/Other
VSS
M2
Power/Other
VSS
AB1
Power/Other
VSS
N1
Power/Other
VSS
AA2
Power/Other
VSS
T1
Power/Other
VSS
AD2
Power/Other
VSS
R2
Power/Other
VSS
AE1
Power/Other
VSS
V2
Power/Other
VSS
B6
Power/Other
VSS
W1
Power/Other
VSS
C5
Power/Other
VSS
A26
Power/Other
VSS
F5
Power/Other
VSS
D26
Power/Other
VSS
E6
Power/Other
VSS
C25
Power/Other
VSS
H6
Power/Other
VSS
F25
Power/Other
VSS
J5
Power/Other
VSS
B24
Power/Other
VSS
M5
Power/Other
VSS
A23
Power/Other
VSS
L6
Power/Other
VSS
D23
Power/Other
VSS
P6
Power/Other
VSS
E24
Power/Other
VSS
R5
Power/Other
VSS
B21
Power/Other
VSS
V5
Power/Other
VSS
C22
Power/Other
VSS
U6
Power/Other
VSS
F22
Power/Other
VSS
Y6
Power/Other
VSS
E21
Power/Other
VSS
A4
Power/Other
VSS
B19
Power/Other
VSS
D4
Power/Other
VSS
A19
Power/Other
VSS
E3
Power/Other
VSS
D19
Power/Other
Datasheet
Direction
45
Package Mechanical Specifications and Pin Information
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
Direction
Table 13.
Pin Name
Pin Listing by Pin Name
Pin
Number
Signal
Buffer Type
VSS
C19
Power/Other
VSS
G23
Power/Other
VSS
F19
Power/Other
VSS
K23
Power/Other
VSS
E19
Power/Other
VSS
L24
Power/Other
VSS
B16
Power/Other
VSS
P24
Power/Other
VSS
A16
Power/Other
VSS
N23
Power/Other
VSS
D16
Power/Other
VSS
T23
Power/Other
VSS
C16
Power/Other
VSS
U24
Power/Other
VSS
F16
Power/Other
VSS
Y24
Power/Other
VSS
E16
Power/Other
VSS
W23
Power/Other
VSS
B13
Power/Other
VSS
H21
Power/Other
VSS
A14
Power/Other
VSS
J22
Power/Other
VSS
D13
Power/Other
VSS
M22
Power/Other
VSS
C14
Power/Other
VSS
L21
Power/Other
VSS
F13
Power/Other
VSS
P21
Power/Other
VSS
E14
Power/Other
VSS
R22
Power/Other
VSS
B11
Power/Other
VSS
V22
Power/Other
VSS
A11
Power/Other
VSS
U21
Power/Other
VSS
D11
Power/Other
VSS
Y21
Power/Other
VSS
C11
Power/Other
VSSSENSE
AE7
Power/Other
VSS
F11
Power/Other
VSS
E11
Power/Other
VSS
B8
Power/Other
VSS
A8
Power/Other
VSS
D8
Power/Other
A3
Table 14.
Pin
Number
Direction
Output
Pin Listing by Pin Number
Signal
Buffer Type
Direction
SMI#
CMOS
Input
VSS
Power/Other
Pin Name
VSS
C8
Power/Other
A4
VSS
F8
Power/Other
A5
FERR#
Open Drain
Output
VSS
E8
Power/Other
A6
A20M#
CMOS
Input
VSS
G26
Power/Other
A7
VCC
Power/Other
VSS
Power/Other
VSS
K26
Power/Other
A8
VSS
J25
Power/Other
A9
VCC
Power/Other
VSS
M25
Power/Other
A10
VCC
Power/Other
VSS
N26
Power/Other
A11
VSS
Power/Other
VCC
Power/Other
VSS
T26
Power/Other
A12
VSS
R25
Power/Other
A13
VCC
Power/Other
VSS
V25
Power/Other
A14
VSS
Power/Other
VSS
W26
Power/Other
A15
VCC
Power/Other
Power/Other
A16
VSS
Power/Other
VSS
46
H24
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
A17
VCC
Power/Other
A18
VCC
Power/Other
A19
VSS
Power/Other
Direction
VCC
Power/Other
A21
BCLK[1]
Bus Clock
Input
A22
BCLK[0]
Bus Clock
Input
A23
VSS
Power/Other
THERMDA
Power/Other
A25
THERMDC
Power/Other
A26
VSS
Power/Other
AA1
RSVD
Reserved
AA2
VSS
Power/Other
AA3
RSVD
Reserved
AA4
RSVD
Reserved
AA5
VSS
Power/Other
AA6
TDI
CMOS
AA7
VCC
Power/Other
AA8
VSS
Power/other
AA9
VCC
Power/Other
AA10
VCC
Power/Other
AA11
VSS
Power/Other
AA12
VCC
Power/Other
AA13
VCC
Power/Other
AA14
VSS
Power/Other
AA15
VCC
Power/Other
AA16
VSS
Power/Other
AA17
VCC
Power/Other
AA18
VCC
Power/Other
AA19
VSS
Power/Other
AA20
VCC
Power/Other
AA21
D[51]#
Source Synch
AA22
VSS
Power/Other
Input
Input/
Output
AA23
D[32]#
Source Synch
Input/
Output
AA24
D[47]#
Source Synch
Input/
Output
AA25
VSS
Power/Other
Datasheet
Pin
Number
AA26
A20
A24
Table 14.
Pin Listing by Pin Number
Pin Name
D[43]#
Signal
Buffer Type
Direction
Source Synch
Input/
Output
AB1
VSS
Power/Other
AB2
RSVD
Reserved
AB3
TDO
Open Drain
AB4
VSS
Power/Other
AB5
TMS
CMOS
Input
AB6
TRST#
CMOS
Input
AB7
VCC
Power/Other
AB8
VSS
Power/Other
Output
AB9
VCC
Power/Other
AB10
VCC
Power/Other
AB11
VSS
Power/Other
AB12
VCC
Power/Other
AB13
VSS
Power/Other
AB14
VCC
Power/Other
AB15
VCC
Power/Other
AB16
VSS
Power/Other
AB17
VCC
Power/Other
AB18
VCC
Power/Other
AB19
VSS
Power/Other
AB20
VCC
Power/Other
AB21
D[52]#
Source Synch
Input/
Output
AB22
D[50]#
Source Synch
Input/
Output
AB23
VSS
Power/Other
AB24
D[33]#
Source Synch
Input/
Output
AB25
D[40]#
Source Synch
Input/
Output
AB26
VSS
Power/Other
AC1
PREQ#
Common
Clock
Input
AC2
PRDY#
Common
Clock
Output
AC3
VSS
Power/Other
AC4
BPM[3]#
Common
Clock
Input/
Output
AC5
TCK
CMOS
Input
47
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
AC6
VSS
Power/Other
AD12
VCC
Power/Other
AC7
VCC
Power/Other
AD13
VSS
Power/Other
AC8
VSS
Power/Other
AD14
VCC
Power/Other
AC9
VCC
Power/Other
AD15
VCC
Power/Other
AC10
VCC
Power/Other
AD16
VSS
Power/Other
AC11
VSS
Power/Other
AD17
VCC
Power/Other
AC12
VCC
Power/Other
AD18
VCC
Power/Other
AC13
VCC
Power/Other
AD19
VSS
Power/Other
AC14
VSS
Power/Other
AD20
D[54]#
Source Synch
AC15
VCC
Power/Other
Input/
Output
AC16
VSS
Power/Other
AD21
D[59]#
Source Synch
Input/
Output
AC17
VCC
Power/Other
AD22
VSS
Power/Other
AC18
VCC
Power/Other
AC19
VSS
Power/Other
AD23
DSTBN[3]#
Source Synch
Input/
Output
AC20
DINV[3]#
Source Synch
AD24
D[57]#
Source Synch
Input/
Output
AC21
VSS
Power/Other
AD25
VSS
Power/Other
AC22
D[48]#
Source Synch
Input/
Output
AD26
GTLREF
Power/Other
AE1
VSS
Power/Other
AC23
D[49]#
Source Synch
Input/
Output
AE2
VID[6]
CMOS
Output
AC24
VSS
Power/Other
AE3
VID[4]
CMOS
Output
VSS
Power/Other
D[53]#
Source Synch
Input/
Output
AE4
AC25
AE5
VID[2]
CMOS
Output
D[46]#
Source Synch
Input/
Output
AE6
PSI#
CMOS
Output
AE7
VSSSENSE
Power/Other
Output
AD1
BPM[2]#
Common
Clock
Output
AE8
VSS
Power/Other
AD2
VSS
Power/Other
AE9
VCC
Power/Other
AE10
VCC
Power/Other
AE11
VSS
Power/Other
AE12
VCC
Power/Other
AE13
VCC
Power/Other
AE14
VSS
Power/Other
AE15
VCC
Power/Other
AE16
VSS
Power/Other
AE17
VCC
Power/Other
AE18
VCC
Power/Other
AE19
VSS
Power/Other
AC26
Input/
Output
AD3
BPM[1]#
Common
Clock
Output
AD4
BPM[0]#
Common
Clock
Input/
Output
AD5
VSS
Power/Other
AD6
VID[0]
CMOS
AD7
VCC
Power/Other
AD8
VSS
Power/Other
AD9
VCC
Power/Other
AD10
VCC
Power/Other
AD11
VSS
Power/Other
48
Output
Input
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
AE20
VCC
Power/Other
AE21
D[58]#
Source Synch
Input/
Output
Input/
Output
AE22
D[55]#
Source Synch
AE23
VSS
Power/Other
AE24
DSTBP[3]#
Source Synch
Input/
Output
Input/
Output
AE25
D[60]#
Source Synch
AE26
VSS
Power/Other
AF1
RSVD
Reserved
AF2
VID[5]
CMOS
AF3
VSS
Power/Other
AF4
VID[3]
CMOS
AF5
VID[1]
CMOS
AF6
VSS
Power/Other
AF7
VCCSENSE
Power/Other
AF8
VSS
Power/Other
AF9
VCC
Power/Other
AF10
VCC
Power/Other
AF11
VSS
Power/Other
AF12
VCC
Power/Other
AF13
VSS
Power/Other
AF14
VCC
Power/Other
AF15
VCC
Power/Other
AF16
VSS
Power/Other
AF17
VCC
Power/Other
AF18
VCC
Power/Other
AF19
VSS
Power/Other
AF20
VCC
Power/Other
Output
Output
Output
AF21
VSS
Power/Other
AF22
D[62]#
Source Synch
Input/
Output
AF23
D[56]#
Source Synch
Input/
Output
AF24
AF25
Datasheet
VSS
D[61]#
Table 14.
Pin
Number
Source Synch
Pin Name
Signal
Buffer Type
Direction
AF26
D[63]#
Source Synch
Input/
Output
B1
RESET#
Common
Clock
Input
B2
RSVD
Reserved
B3
INIT#
CMOS
Input
B4
LINT1
CMOS
Input
B5
DPSLP#
CMOS
Input
B6
VSS
Power/Other
B7
VCC
Power/Other
B8
VSS
Power/Other
B9
VCC
Power/Other
B10
VCC
Power/Other
B11
VSS
Power/Other
B12
VCC
Power/Other
B13
VSS
Power/Other
B14
VCC
Power/Other
B15
VCC
Power/Other
B16
VSS
Power/Other
B17
VCC
Power/Other
B18
VCC
Power/Other
B19
VSS
Power/Other
B20
VCC
Power/Other
B21
VSS
Power/Other
B22
BSEL[0]
CMOS
Output
B23
BSEL[1]
CMOS
Output
B24
VSS
Power/Other
B25
RSVD
Reserved
B26
VCCA
Power/Other
C1
RSVD
Reserved
C2
VSS
Power/Other
C3
RSVD
Reserved
C4
IGNNE#
CMOS
Input
C5
VSS
Power/Other
C6
LINT0
CMOS
Input
C7
THERMTRIP
#
Open Drain
Output
C8
VSS
Power/Other
Power/Other
Input/
Output
Pin Listing by Pin Number
49
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
C9
VCC
Power/Other
C10
VCC
Power/Other
C11
VSS
Power/Other
C12
VCC
Power/Other
C13
VCC
Power/Other
C14
VSS
Power/Other
C15
VCC
Power/Other
C16
VSS
Power/Other
C17
VCC
Power/Other
C18
VCC
Power/Other
C19
VSS
Power/Other
Direction
C20
DBR#
CMOS
Output
C21
BSEL[2]
CMOS
Output
C22
VSS
Power/Other
C23
RSVD
Reserved
C24
RSVD
Reserved
C25
VSS
Power/Other
C26
TEST1
Test
D1
VSS
Power/Other
D2
RSVD
Reserved
D3
RSVD
Reserved
D4
VSS
Power/Other
D5
STPCLK#
CMOS
Input
D6
PWRGOOD
CMOS
Input
D7
SLP#
CMOS
Input
D8
VSS
Power/Other
D9
VCC
Power/Other
D10
VCC
Power/Other
D11
VSS
Power/Other
D12
VCC
Power/Other
D13
VSS
Power/Other
D14
VCC
Power/Other
D15
VCC
Power/Other
D16
VSS
Power/Other
D17
VCC
Power/Other
D18
VCC
Power/Other
D19
VSS
Power/Other
50
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
D20
IERR#
Open Drain
Output
D21
PROCHOT#
Open Drain
Input/
Output
D22
RSVD
Reserved
D23
VSS
Power/Other
D24
DPWR#
Common
Clock
D25
TEST2
Test
D26
VSS
Power/Other
E1
DBSY#
Common
Clock
Input/
Output
E2
BNR#
Common
Clock
Input/
Output
E3
VSS
Power/Other
E4
HITM#
Common
Clock
Input/
Output
E5
DPRSTP#
CMOS
Not used
E6
VSS
Power/Other
E7
VCC
Power/Other
E8
VSS
Power/Other
E9
VCC
Power/Other
E10
VCC
Power/Other
E11
VSS
Power/Other
E12
VCC
Power/Other
E13
VCC
Power/Other
E14
VSS
Power/Other
E15
VCC
Power/Other
E16
VSS
Power/Other
E17
VCC
Power/Other
E18
VCC
Power/Other
E19
VSS
Power/Other
E20
VCC
Power/Other
E21
VSS
Power/Other
E22
D[0]#
Source Synch
Input/
Output
E23
D[7]#
Source Synch
Input/
Output
E24
VSS
Power/Other
E25
D[6]#
Source Synch
Input
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Listing by Pin Number
Signal
Buffer Type
Direction
D[2]#
Source Synch
Input/
Output
F1
BR0#
Common
Clock
Input/
Output
F2
VSS
Power/Other
F3
RS[0]#
Common
Clock
F4
RS[1]#
Common
Clock
F5
VSS
Power/Other
F6
RSVD
Reserved
F7
VCC
Power/Other
F8
VSS
Power/Other
F9
VCC
Power/Other
F10
VCC
Power/Other
F11
VSS
Power/Other
F12
VCC
Power/Other
F13
VSS
Power/Other
F14
VCC
Power/Other
F15
VCC
Power/Other
F16
VSS
Power/Other
F17
VCC
Power/Other
F18
VCC
Power/Other
F19
VSS
Power/Other
F20
VCC
Power/Other
F21
DRDY#
Common
Clock
F22
VSS
Power/Other
F23
D[4]#
Source Synch
F24
D[1]#
Source Synch
F25
VSS
Power/Other
Pin
Number
E26
Pin Name
Direction
G5
BPRI#
Common
Clock
Input
G6
HIT#
Common
Clock
Input/
Output
G21
VCCP
Power/Other
G22
DSTBP[0]#
Source Synch
G23
VSS
Power/Other
G24
D[9]#
Source Synch
Input/
Output
G25
D[5]#
Source Synch
Input/
Output
G26
VSS
Power/Other
H1
ADS#
Common
Clock
Input/
Output
H2
REQ[1]#
Source Synch
Input/
Output
H3
VSS
Power/Other
H4
LOCK#
Common
Clock
Input/
Output
H5
DEFER#
Common
Clock
Input
H6
VSS
Power/Other
H21
VSS
Power/Other
H22
D[3]#
Source Synch
Input/
Output
H23
DSTBN[0]#
Source Synch
Input/
Output
H24
VSS
Power/Other
Input/
Output
H25
D[15]#
Source Synch
Input/
Output
Input/
Output
H26
D[12]#
Source Synch
Input/
Output
J1
A[9]#
Source Synch
Input/
Output
J2
VSS
Power/Other
J3
REQ[3]#
Source Synch
Input/
Output
J4
A[3]#
Source Synch
Input/
Output
J5
VSS
Power/Other
Input
Input
Input/
Output
Input/
Output
VSS
Power/Other
TRDY#
Common
Clock
Input
Common
Clock
Input
Datasheet
Signal
Buffer Type
Power/Other
G1
RS[2]#
Pin Name
VSS
D[13]#
G3
Pin
Number
Pin Listing by Pin Number
G4
F26
G2
Source Synch
Table 14.
Input/
Output
51
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
J6
VCCP
Power/Other
J21
VCCP
Power/Other
J22
VSS
Power/Other
J23
D[11]#
Source Synch
J24
D[10]#
Source Synch
J25
VSS
Power/Other
J26
DINV[0]#
Source Synch
K1
VSS
Power/Other
K2
REQ[2]#
Source Synch
Input/
Output
K3
REQ[0]#
Source Synch
Input/
Output
K4
VSS
Power/Other
K5
A[6]#
Source Synch
K6
VCCP
Power/Other
K21
VCCP
Power/Other
K22
D[14]#
Source Synch
K23
VSS
Power/Other
K24
D[8]#
Source Synch
Input/
Output
K25
D[17]#
Source Synch
Input/
Output
K26
VSS
Power/Other
L1
A[13]#
Source Synch
Input/
Output
Input/
Output
L2
ADSTB[0]#
Source Synch
L3
VSS
Power/Other
Direction
Input/
Output
L24
VSS
Power/Other
Input/
Output
L25
D[20]#
Source Synch
Input/
Output
Input/
Output
L26
D[29]#
Source Synch
Input/
Output
M1
A[7]#
Source Synch
Input/
Output
M2
VSS
Power/Other
M3
A[5]#
Source Synch
M4
RSVD
Reserved
M5
VSS
Power/Other
Input/
Output
Input/
Output
Input/
Output
Source Synch
L5
REQ[4]#
Source Synch
Input/
Output
L6
VSS
Power/Other
L21
VSS
Power/Other
52
Signal
Buffer Type
Source Synch
A[4]#
Source Synch
Pin Name
D[22]#
L4
D[21]#
Pin
Number
Pin Listing by Pin Number
L23
Input/
Output
L22
Table 14.
Input/
Output
Input/
Output
M6
VCCP
Power/Other
M21
VCCP
Power/Other
M22
VSS
Power/Other
M23
D[23]#
Source Synch
Input/
Output
M24
DSTBN[1]#
Source Synch
Input/
Output
M25
VSS
Power/Other
M26
DINV[1]#
Source Synch
N1
VSS
Power/Other
N2
A[8]#
Source Synch
Input/
Output
N3
A[10]#
Source Synch
Input/
Output
N4
VSS
Power/Other
N5
RSVD
Reserved
N6
VCCP
Power/Other
N21
VCCP
Power/Other
N22
D[16]#
Source Synch
N23
VSS
Power/Other
N24
D[31]#
Source Synch
Input/
Output
N25
DSTBP[1]#
Source Synch
Input/
Output
N26
VSS
Power/Other
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
P1
Pin Listing by Pin Number
Pin Name
A[15]#
Signal
Buffer Type
Direction
Source Synch
Input/
Output
Input/
Output
P2
A[12]#
Source Synch
P3
VSS
Power/Other
P4
A[14]#
Source Synch
Input/
Output
P5
A[11]#
Source Synch
Input/
Output
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
T4
VSS
Power/Other
T5
A[25]#
Source Synch
T6
VCCP
Power/Other
T21
VCCP
Power/Other
T22
RSVD
Reserved
T23
VSS
Power/Other
T24
D[27]#
Source Synch
Input/
Output
T25
D[30]#
Source Synch
Input/
Output
T26
VSS
Power/Other
U1
COMP[2]
Power/Other
Input/
Output
U2
A[23]#
Source Synch
Input/
Output
U3
VSS
Power/Other
Input/
Output
P6
VSS
Power/Other
P21
VSS
Power/Other
P22
D[25]#
Source Synch
Input/
Output
P23
D[26]#
Source Synch
Input/
Output
P24
VSS
Power/Other
P25
D[24]#
Source Synch
Input/
Output
P26
D[18]#
Source Synch
Input/
Output
U4
A[21]#
Source Synch
Input/
Output
R1
A[16]#
Source Synch
Input/
Output
U5
A[18]#
Source Synch
Input/
Output
R2
VSS
Power/Other
U6
VSS
Power/Other
U21
VSS
Power/Other
R3
A[19]#
Source Synch
U22
D[39]#
Source Synch
Input/
Output
U23
D[37]#
Source Synch
Input/
Output
U24
VSS
Power/Other
U25
D[38]#
Source Synch
Input/
Output
U26
COMP[1]
Power/Other
Input/
Output
V1
COMP[3]
Power/Other
Input/
Output
V2
VSS
Power/Other
V3
RSVD
Reserved
V4
ADSTB[1]#
Source Synch
V5
VSS
Power/Other
V6
VCCP
Power/Other
V21
VCCP
Power/Other
R4
A[24]#
Source Synch
R5
VSS
Power/Other
R6
VCCP
Power/Other
R21
VCCP
Power/Other
R22
VSS
Power/Other
Input/
Output
Input/
Output
R23
D[19]#
Source Synch
Input/
Output
R24
D[28]#
Source Synch
Input/
Output
R25
VSS
Power/Other
R26
COMP[0]
Power/Other
T1
VSS
Power/Other
T2
RSVD
Reserved
T3
A[26]#
Source Synch
Datasheet
Input/
Output
Input/
Output
Input/
Output
53
Package Mechanical Specifications and Pin Information
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
V22
VSS
Power/Other
V23
DINV[2]#
Source Synch
V24
D[34]#
Source Synch
V25
VSS
Power/Other
V26
D[35]#
Source Synch
W1
VSS
Power/Other
W2
A[30]#
Source Synch
Input/
Output
W3
A[27]#
Source Synch
Input/
Output
W4
VSS
Power/Other
W5
A[28]#
Source Synch
Input/
Output
W6
A[20]#
Source Synch
Input/
Output
W21
VCCP
Power/Other
W22
D[41]#
Source Synch
W23
VSS
Power/Other
W24
DSTBN[2]#
Source Synch
Input/
Output
W25
D[36]#
Source Synch
Input/
Output
W26
VSS
Power/Other
Y1
A[31]#
Source Synch
Input/
Output
Y2
A[17]#
Source Synch
Input/
Output
Y3
VSS
Power/Other
Y4
A[29]#
Source Synch
Input/
Output
Y5
A[22]#
Source Synch
Input/
Output
Y6
VSS
Power/Other
Y21
VSS
Power/Other
Y22
D[45]#
Source Synch
Input/
Output
Y23
D[42]#
Source Synch
Input/
Output
54
Table 14.
Pin
Number
Pin Listing by Pin Number
Pin Name
Signal
Buffer Type
Direction
Y24
VSS
Power/Other
Input/
Output
Y25
DSTBP[2]#
Source Synch
Input/
Output
Input/
Output
Y26
D[44]#
Source Synch
Input/
Output
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
4.5
Alphabetical Signals Reference
Table 15.
Signal Description (Sheet 1 of 8)
Name
A[31:3]#
A20M#
Type
Description
Input/
Output
A[31:3]# (Address) define a 232-byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the Intel® Celeron® M processor
FSB. A[31:3]# are source synchronous signals and are latched into
the receiving buffers by ADSTB[1:0]#. Address signals are used as
straps which are sampled before RESET# is deasserted.
Input
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
ADSTB[1:0]#
BCLK[1:0]
Input/
Output
Input
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[31:17]#
ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR#
BPM[2:1]#
BPM[3,0]#
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
Output
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[3:0]# should connect the
appropriate pins of all Celeron M processor FSB agents.This includes
debug or performance monitoring tools.
Input/
Output
Please contact your Intel representative for more detailed
information.
Datasheet
55
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 2 of 8)
Name
Type
Description
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are completed, then releases
the bus by deasserting BPRI#.
BR0#
Input/
Output
BR0# is used by the processor to request the bus. The arbitration is
done between the Celeron M processor (Symmetric Agent) and
Intel® 945GMS and Intel 940GML Express Chipset (High Priority
Agent).
Output
BSEL[2:0] (Bus Select) are used to select the processor input clock
frequency. Table 3 on page 23 defines the possible combinations of
the signals and the frequency associated with each combination. The
required frequency is determined by the processor, chipset and clock
synthesizer. All agents must operate at the same frequency. The
Celeron M processor operates 533 MHz system bus frequency
(133-MHz BCLK[1:0] frequency).
BSEL[2:0]
COMP[3:0]
Analog
COMP[3:0] must be terminated on the system board using precision
(1% tolerance) resistors.
Please contact your Intel representative for more implementation
details.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data
strobes and DINV#.
Quad-Pumped Signal Groups
D[63:0]#
Input/
Output
Data
Group
DSTBN#/
DSTBP#
DINV#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBR#
56
Output
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 3 of 8)
Name
DBSY#
DEFER#
Type
Description
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be guaranteed in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or Input/
Output agent. This signal must connect the appropriate pins of both
FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DINV[3:0]# Assignment to Data Bus
DINV[3:0]#
DPRSTP#
Input/
Output
Not used
Bus Signal
Data Bus
Signals
DINV[3]#
D[63:48]#
DINV[2]#
D[47:32]#
DINV[1]#
D[31:16]#
DINV[0]#
D[15:0]#
DPRSTP# is not used by the Celeron M processor.
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. In order to
return to the Sleep State, DPSLP# must be deasserted. DPSLP# is
driven by the ICH7-M chipset.
DPWR#
Input
DPWR# is a control signal from the Intel 945GMS and Intel 940GML
Express Chipsets used to reduce power on the Celeron M data bus
input buffers.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Data strobe used to latch in D[63:0]#.
Signals
DSTBN[3:0]#
Datasheet
Input/
Output
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
57
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 4 of 8)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
FERR#/PBE#
Input/
Output
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#
FERR# (Floating-point Error)PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel 387 coprocessor,
and is included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will
remain asserted until STPCLK# is deasserted. Assertion of PREQ#
when STPCLK# is active will also cause an FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volume 3 of the IA 32 Intel® Architecture
Software Developer’s Manual and the Intel® Processor Identification
and CPUID Instruction application note.
For termination requirements, please contact your Intel
representative.
GTLREF
HIT#/
HITM#
IERR#
Input
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may optionally
be converted to an external error signal (e.g., NMI) by system core
logic. The processor will keep IERR# asserted until the assertion of
RESET#, BINIT#, or INIT#.
For termination requirements, please contact your Intel
representative.
58
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 5 of 8)
Name
IGNNE#
Type
Description
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is deasserted, the processor generates
an exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect
when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output Write
instruction, it must be valid along with the TRDY# assertion of the
corresponding Input/Output Write bus transaction. INIT# must
connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
For termination requirements, please contact your Intel
representative.
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Intel® Pentium®
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
PRDY#
PREQ#
Datasheet
Input/
Output
Output
Input
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of the
last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the FSB throughout the bus
locked operation and ensure the atomicity of lock.
Probe Ready signal used by debug tools to determine processor
debug readiness.
Please contact your Intel representative for more implementation
details.
Probe Request signal used by debug tools to request debug
operation of the processor.
Please contact your Intel representative for more implementation
details.
59
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 6 of 8)
Name
PROCHOT#
Type
Input/
Output
Description
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This indicates
that the processor Thermal Control Circuit (TCC) has been activated,
if enabled. As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled. The TCC will remain active until the
system deasserts PROCHOT#.
By default PROCHOT# is configured as an output only. Bidirectional
PROCHOT# must be enabled via the BIOS.
For termination requirements, please contact your Intel
representative.
This signal may require voltage translation on the motherboard.
Please contact your Intel representative for more detailed
information.
PSI#
PWRGOOD
Output
Input
Processor Power Status Indicator signal. This signal is asserted when
the processor is in a lower state (Deep Sleep).
Please contact your Intel representative for more details on the
PSI# signal.
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. “Clean”
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
transition monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
For termination requirements, please contact your Intel
representative.
REQ[4:0]#
RESET#
Input/
Output
Input
REQ[4:0]# (Request Command) must connect the appropriate pins
of both FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least two milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both FSB agents will
deassert their outputs within two clocks. All processor straps must
be valid within the specified setup time before RESET# is
deasserted.
There is a 55-Ω (nominal) on die pull-up resistor on this signal.
RS[2:0]#
RSVD
60
Input
Reserved
/No
Connect
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
These pins are RESERVED and must be left unconnected on the
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
Please contact your Intel representative for more detailed
information.
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 7 of 8)
Name
SLP#
SMI#
Type
Description
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the processor
stops providing internal clock signals to all units, leaving only the
Phase-Locked Loop (PLL) still operating. Processors in this state will
not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of
the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state,
restarting its internal clock signals to the bus and processor core
units. If DPSLP# is asserted while in the Sleep state, the processor
will exit the Sleep state and transition to the Deep Sleep state.
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor
will tristate its outputs.
STPCLK#
TCK
TDI
TDO
Input
Input
Input
Output
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
Please contact your Intel representative for termination
requirements and implementation details.
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
Please contact your Intel representative for termination
requirements and implementation details.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
Please contact your Intel representative for termination
requirements and implementation details.
TEST1
Datasheet
Input
TEST1 must have a stuffing option of separate pull-down resistor to
VSS.
Please contact your Intel representative for more detailed
information.
TEST2 must have a 51-Ω ±5% pull-down resistor to VSS.
TEST2
Input
THERMDA
Other
Thermal Diode Anode.
THERMDC
Other
Thermal Diode Cathode.
Please contact your Intel representative for more detailed
information.
61
Package Mechanical Specifications and Pin Information
Table 15.
Signal Description (Sheet 8 of 8)
Name
THERMTRIP#
Type
Output
Description
The processor protects itself from catastrophic overheating by use of
an internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature
exceeds approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
For termination requirements, please contact your Intel
representative.
TMS
TRDY#
Input
Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
Please contact your Intel representative for termination
requirements and implementation details.
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
Please contact your Intel representative for termination
requirements and implementation details.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
TRST#
Input
VCC
Input
Processor core power supply.
VCCA
Input
VCCA provides isolated power for the internal processor core PLL’s.
Please contact your Intel representative for complete
implementation details.
VCCP
Input
Processor I/O Power Supply.
VCCSENSE
VID[6:0]
VSSSENSE
Please contact your Intel representative for termination
requirements and implementation details.
Output
VCCSENSE is an isolated low impedance connection to processor core
power (VCC). It can be used to sense or measure power near the
silicon with little noise. Please contact your Intel representative for
termination requirements and routing recommendations.
Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (VCC). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Celeron M
processor. The voltage supply for these pins must be valid before the
VR can supply Vcc to the processor. Conversely, the VR output must
be disabled until the voltage supply for the VID pins becomes valid.
The VID pins are needed to support the processor voltage
specification variations. See Table 2 for definitions of these pins. The
VR must supply the voltage that is requested by the pins, or disable
itself.
Output
VSSSENSE is an isolated low impedance connection to processor core
VSS. It can be used to sense or measure ground near the silicon with
little noise.
Please contact your Intel representative for termination
requirements and routing recommendations.
§
62
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
The Celeron M processor requires a thermal solution to maintain temperatures within
operating limits as set forth in Section 5.1. Any attempt to operate that processor
outside these operating limits may result in permanent damage to the processor and
potentially other components in the system. As processor technology changes, thermal
management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation. A complete thermal solution includes both component and system level
thermal management features. Component level thermal solutions include active or
passive heatsinks or heat exchangers attached to the processor exposed die. The
solution should make firm contact to the die while maintaining processor mechanical
specifications such as pressure. A typical system level thermal solution may consist of a
processor fan ducted to a heat exchanger that is thermally coupled to the processor via
a heat pipe or direct die attachment. A secondary fan or air from the processor fan may
also be used to cool other platform components or to lower the internal ambient
temperature within the system.
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum junction temperature (Tj)
specifications at the corresponding thermal design power (TDP) value listed in Table 16
and Table 17. Thermal solutions not designed to provide this level of thermal capability
may affect the long-term reliability of the processor and system.
Contact your Intel representative for more details on processor and system level
cooling approaches.
The maximum junction temperature is defined by an activation of the processor Intel®
Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real
applications are unlikely to cause the processor to consume the theoretical maximum
power dissipation for sustained time periods. Intel recommends that complete thermal
solution designs target the TDP indicated in Table 16 and Table 17. The Intel Thermal
Monitor feature is designed to help protect the processor in the unlikely event that an
application exceeds the TDP recommendation for a sustained period of time. For more
details on the usage of this feature, refer to Section 5.1.3. In all cases the Intel
Thermal Monitor feature must be enabled for the processor to remain within
specification.
Datasheet
63
Thermal Specifications and Design Considerations
Table 16.
Power Specifications for the Celeron M Processor Standard Voltage
Processor
Number
Symbol
TDP
Symbol
Core Frequency
& Voltage
Thermal Design
Power
450
2.00 GHz & HFM VCC
27
440
1.86 GHz & HFM VCC
27
430
1.73 GHz & HFM VCC
27
420
1.60 GHz & HFM VCC
27
410
1.46 GHz & HFM VCC
27
1, 4
Auto Halt, Stop Grant Power
10.1
W
At
50°C
2
PSLP
Sleep Power at VCC
10.0
W
At
50°C
2
PDSLP
Deep Sleep Power at VCC
6.5
W
At
35°C
2
TJ
Junction Temperature
100
°C
3, 4
0
Typ
W
Unit
PSGNT
Min
Notes
Max
PAH,
Parameter
Unit
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for more details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
64
Datasheet
Thermal Specifications and Design Considerations
Table 17.
Power Specifications for the Celeron M Processor Ultra Low Voltage
Processor
Number
Symbol
TDP
Core Frequency
& Voltage
443
1.20 GHz & HFM VCC
423
1.06 GHz & HFM VCC
Symbol
Unit
Notes
5.5
W
1, 4
Max
Unit
Auto Halt, Stop Grant Power
3.0
W
At
50°C
2
PSLP
Sleep Power at VCC
2.9
W
At
50°C
2
PDSLP
Deep Sleep Power at VCC
1.5
W
At
35°C
2
TJ
Junction Temperature
100
°C
3, 4
PAH,
PSGNT
Parameter
Thermal Design
Power
Min
0
Typ
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for more details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
5.1
Thermal Specifications
The Celeron M processor incorporates three methods of monitoring die temperature,
the Digital thermal sensor, Intel Thermal Monitor and the thermal diode. The Intel
Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the
maximum specified processor junction temperature has been reached.
5.1.1
Thermal Diode
The processor incorporates an on-die PNP transistor whose base emitter junction is
used as a thermal diode, with its collector shorted to Ground. The thermal diode, can
be read by an off-die analog/digital converter (a thermal sensor) located on the
motherboard, or a stand-alone measurement kit. The thermal diode may be used to
monitor the die temperature of the processor for thermal management or
instrumentation purposes but is not a reliable indication that the maximum operating
temperature of the processor has been reached. When using the thermal diode, a
temperature offset value must be read from a processor model specific register (MSR)
and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal
diode usage recommendation when the PROCHOT# signal is not asserted.
Note:
Datasheet
The reading of the external thermal sensor (on the motherboard) connected to the
processor thermal diode signals, will not necessarily reflect the temperature of the
hottest location on the die. This is due to inaccuracies in the external thermal sensor,
65
Thermal Specifications and Design Considerations
on-die temperature gradients between the location of the thermal diode and the hottest
location on the die, and time based variations in the die temperature measurement.
Time based variations can occur when the sampling rate of the thermal diode (by the
thermal sensor) is slower than the rate at which the TJ temperature can change.
Offset between the thermal diode-based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic
mode activation of thermal control circuit. This temperature offset must be taken into
account when using the processor thermal diode to implement power management
events. This offset is different than the diode Toffset value programmed into the Intel
Core Duo and Intel Core Solo processors’ MSR.
Table 18, Table 19, Table 20, and Table 21 provide the diode interface and
specifications. Two different sets of diode parameters are listed in Table 19 and
Table 20. The Diode Model parameters (Table 19) apply to traditional thermal sensors
that use the Diode Equation to determine the processor temperature. Transistor Model
parameters (Table 20) have been added to support thermal sensors that use the
transistor equation method. The Transistor Model may provide more accurate
temperature measurements when the diode ideality factor is closer to the maximum or
minimum limits. Please contact your external thermal sensor supplier for their
recommendation. This thermal diode is separate from the Intel Thermal Monitor's
thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.
Table 18.
Table 19.
Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
A24
Thermal diode anode
THERMDC
A25
Thermal diode cathode
Thermal Diode Parameters using Diode Model
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IFW
Forward Bias Current
5
-
200
µA
1
n
Diode Ideality Factor
1.000
1.009
1.050
-
2, 3, 4
RT
Series Resistance
2.79
4.52
6.24
Ω
2, 3, 5
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Intel does not support or recommend operation of the thermal diode when the processor
power supplies are not within their specified tolerance range.
2.
Characterized across a temperature range of 50 – 100°C.
3.
Not 100% tested. Specified by design characterization.
4.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW = IS * (e qVD/nkT –1)
where IS = saturation current, q = electronic charge, VD = voltage across the diode, k =
Boltzmann Constant, and T = absolute temperature (Kelvin).
66
Datasheet
Thermal Specifications and Design Considerations
5.
The series resistance, RT, is provided to allow for a more accurate measurement of the
junction temperature. RT, as defined, includes the lands of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant,
q = electronic charge.
Table 20.
Thermal Diode Parameters using Transistor Mode
Symbol
Parameter
Min
Typ
Max
Unit
Notes
-
200
µA
1, 2
200
µA
1.005
-
3, 4, 5
Ω
3, 6
IFW
Forward Bias
Current
5
IE
Emitter Current
5
nQ
Transistor Ideality
0.997
Series Resistance
2.79
Beta
RT
1.001
0.3
0.760
4.52
6.24
3, 4
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
Same as IFW in Table 19
3.
Characterized across a temperature range of 50 - 100 °C.
4.
Not 100% tested. Specified by design characterization.
5.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qVBE/nQkT –1)
Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
6.
The series resistance, RT, provided in the Diode Model Table (Table 19) can be used for
more accurate readings as needed.
When calculating a temperature based on thermal diode measurements, a number of
parameters must be either measured or assumed. Most devices measure the diode
ideality and assume a series resistance and ideality trim value, although some are
capable of also measuring the series resistance. Calculating the temperature is then
accomplished using the equations listed under Table 19. In most temperature sensing
devices, an expected value for the diode ideality is designed-in to the temperature
calculation equation. If the designer of the temperature sensing device assumes a
perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes
are not perfect, the designers usually select an ntrim value that more closely matches
the behavior of the diodes in the processor. If the processors diode ideality deviates
from that of ntrim, each calculated temperature will be offset by a fixed amount. This
temperature offset can be calculated with the equation:
Terror(nf) = Tmeasured X (1 - nactual/ntrim)
Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured
ideality of the diode, and ntrim is the diode ideality assumed by the temperature
sensing device.
Datasheet
67
Thermal Specifications and Design Considerations
5.1.2
Thermal Diode Offset
In order to improve the accuracy of diode based temperature measurements, a
temperature offset value (specified as Toffset) will be programmed into a Intel Core
Duo and Intel Core Solo processors’ MSR, which will contain thermal diode
characterization data. During manufacturing each processors thermal diode will be
evaluated for its behavior relative to a theoretical diode. Using the equation above, the
temperature error created by the difference between ntrim and the actual ideality of the
particular processor will be calculated.
If the ntrim value used to calculate Toffset differs from the ntrim value used in a
temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset
can be adjusted by calculating nactual and then recalculating the offset using the actual
ntrim as defined in the temperature sensor manufacturers' datasheet.
The ntrim used to calculate the Diode Correction Toffset are listed in Table 21.
Table 21.
Thermal Diode ntrim and Diode Correction Toffset
Symbol
ntrim
Parameter
Diode ideality used to calculate Toffset
Unit
1.01
Contact your Intel representative for more details on the temperature offset MSR
definition and recommended offset implementation.
5.1.3
Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the
TCC (Thermal Control Circuit) when the processor silicon reaches its maximum
operating temperature. The temperature at which the Intel Thermal Monitor activates
the TCC is not user configurable. Bus traffic is snooped in the normal manner, and
interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be minor and hence not detectable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss, and
may affect the long-term reliability of the processor. In addition, a thermal solution that
is significantly under designed may not be capable of cooling the processor even when
the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks when the processor silicon reaches its
maximum operating temperature. The Intel Thermal Monitor uses this mode to activate
the TCC: Automatic mode and on-demand mode. If both modes are activated,
Automatic mode takes precedence.
Note:
The Intel Thermal Monitor automatic mode must be enabled through BIOS for the
processor to be operating within specifications.
This automatic mode is called Intel Thermal Monitor 1 (TM1). This mode is selected by
writing values to the Model Specific Registers (MSRs) of the processor. After Automatic
mode is enabled, the TCC will activate only when the internal die temperature reaches
the maximum allowed value for operation.
68
Datasheet
Thermal Specifications and Design Considerations
When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the
clocks will be modulated by alternately turning the clocks off and on at a 50% duty
cycle. Cycle times are processor speed dependent and will decrease linearly as
processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis
has been included to prevent rapid active/inactive transitions of the TCC when the
processor temperature is near the trip point. The duty cycle is factory configured and
cannot be modified. Also, automatic mode does not require any additional hardware,
software drivers, or interrupt handling routines. Processor performance will be
decreased by the same amount as the duty cycle when the TCC is active.
The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal
Monitor control register is written to a 1, the TCC will be activated immediately,
independent of the processor temperature. When using on-demand mode to activate
the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the
same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is
fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.
On-demand mode may be used at the same time automatic mode is enabled, however,
if the system tries to enable the TCC via on-demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take
precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSRs, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal
Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt
upon the assertion or deassertion of PROCHOT#.
Note:
PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep and
Deep Sleep low power states (internal clocks stopped), hence the thermal diode
reading must be used as a safeguard to maintain the processor junction temperature
within maximum specification. If the platform thermal solution is not able to maintain
the processor junction temperature within the maximum specification, the system must
initiate an orderly shutdown to prevent damage. If the processor enters one of the
above low power states with PROCHOT# already asserted, PROCHOT# will remain
asserted until the processor exits the low power state and the processor junction
temperature drops below the thermal trip point.
Contact your Intel representative for more details on the Intel Thermal Monitor register
and programming details.
If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out
of specification. Regardless of enabling the automatic or on-demand modes, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached a temperature of approximately 125°C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified in Chapter 3.5.
Datasheet
69
Thermal Specifications and Design Considerations
5.1.4
Digital Thermal Sensor
The Celeron M processor also contains an on die digital thermal sensor that can be read
via a MSR (no I/O interface). The digital thermal sensor is the preferred method of
reading the processor die temperature since it can be located much closer to the
hottest portions of the die and can thus more accurately track the die temperature and
potential activation of processor core clock modulation via the Intel Thermal Monitor.
The digital thermal sensor is only valid while the processor is in the normal operating
state (C0 state).
Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature
relative to the maximum supported operating temperature of the processor (TJ,max). It
is the responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the digital thermal sensor will always be at
or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status
bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the
processor is operating out of specification and immediate shutdown of the system
should occur. The processor operation and code execution is not guaranteed once the
activation of the Out of Spec status bit is set.
The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the
Intel Thermal Monitor (TM1) trigger point. When the DTS indicates maximum processor
core temperature has been reached TM1 hardware thermal control mechanism will
activate. The DTS and Intel Thermal Monitor (TM1) temperature may not correspond to
the thermal diode reading since the thermal diode is located in a separate portion of
the die and thermal gradient between the individual core DTS. Additionally, the thermal
gradient from DTS to thermal diode can vary substantially due to changes in processor
power, mechanical and thermal attach and software application. The system designer is
required to use the DTS to guarantee proper operation of the processor within its
temperature operating specifications.
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the IA-32 Intel® Architecture Software Developer's
Manual and your Intel representative for specific register and programming details.
5.1.5
Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and
temperature gradient. This feature is intended for graceful shut down before the
THERMTRIP# is activated. If the processor’s TM1 is triggered and the temperature
remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR
register and generates thermal interrupt. For more details on the interrupt mechanism,
contact your Intel representative.
5.1.6
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its maximum operating temperature. If the Intel Thermal
Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the
processor to be operating within specification), the TCC will be active when PROCHOT#
is asserted. The processor can be configured to generate an interrupt upon the
assertion or deassertion of PROCHOT#. Refer to the IA-32 Intel® Architecture Software
Developer's Manuals and your Intel representative for specific register and
programming details.
The Celeron M processor implements a bi-directional PROCHOT# capability to allow
system designs to protect various components from over-temperature situations. The
PROCHOT# signal is bi-directional in that it can either signal when the processor has
70
Datasheet
Thermal Specifications and Design Considerations
reached its maximum operating temperature or be driven from an external source to
activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means
for thermal protection of system components.
When PROCHOT# is driven by an external agent, TM1 is enabled and the processor
core will have their core clocks modulated.
One application is the thermal protection of voltage regulators (VR). System designers
can create a circuit to monitor the VR temperature and activate the TCC when the
temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and
activating the TCC, the VR can cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in
case of system cooling failure. The system thermal design should allow the power
delivery circuitry to operate within its temperature specification even while the
processor is operating at its TDP. With a properly designed and characterized thermal
solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very
short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT#
in the anticipated ambient environment may cause a noticeable performance loss.
Contact your Intel representative for details on implementing the bi-directional
PROCHOT# feature.
§
Datasheet
71