TI CDCLVD110

CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
D Low-Output Skew <30 ps (Typical) for
TQFP PACKAGE
(TOP VIEW)
Clock-Distribution applications
D
D
D
D
D
24 23 22 21 20 19 18 17
VSS
Q2
Q2
Q1
Q1
Q0
Q0
VDD
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3
4
5 6 7
VDD
Q7
Q7
Q8
Q8
Q9
Q9
VSS
8
CK
SI
CLK0
CLK0
VBB
CLK1
CLK1
EN
D
D
10 LVDS Differential Clock Outputs
VCC range 2.5 V ±5%
Typical Signaling Rate Capability of Up to
1.1 GHz
Configurable Register (SI/CK) Individually
Enables Disables Outputs, Selectable
CLK0, CLK0 or CLK1, CLK1 Inputs
Full Rail-to-Rail Common-Mode Input
Range
Receiver Input Threshold ±100 mV
Available in 32-Pin TQFP Package
Fail-Safe I/O-Pins for VDD = 0 V (Power
Down)
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
D Distributes One Differential Clock Input to
description
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10
pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is
specifically designed for driving 50-Ω transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can
be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the
shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the
outputs are not programmable and all outputs are enabled.
The CDCLVD110 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
functional block diagram
CK
11-Bit Shift Register
SI
EN
11-Bit Control Register
10
9 8 7 6 5 4 3 2 1 0
1
0
12-Bit
Counter
Q9
Mux
Q9
CLK_SEL
Q8
Q8
CLK0
CLK0
0
Q7
Mux
Q7
CLK1
CLK1
1
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VBB
2
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CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CK
1
I
Control register input clock, features a 120-kΩ pullup resistor
SI
2
I
Control register serial input/CLK Select, features a 120-kΩ pulldown resistor
CLK0
3
I
Complementary differential input, LVDS
CLK0
4
I
True differential input, LVDS
VBB
CLK1
5
O
Reference voltage output
6
I
Complementary differential input, LVDS
CLK1
7
I
True differential input, LVDS
8
I
Control enable (for programmability), features a 120-kΩ pulldown resistor, input
EN
VSS
VDD
9, 25
Device ground
16, 32
Supply voltage
Q [9:0]
11, 13, 15, 18, 20,
22, 24, 27, 29, 31
O
Clock outputs, these outputs provide low-skew copies of CLKIN
Q[9:0]
10, 12, 14, 17, 19,
21,23, 26, 28, 30
O
Complementary clock outputs, these outputs provide low-skew copies of CLKIN
absolute maximum ratings†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.8 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.2 V to (VDD + 0.2)
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.2 V to (VDD + 0.2)
Driver short circuit current, Qn, Qn, IOSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VDD
Receiver common-mode input voltage, VIC
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
VDD – 0.5|VID|
85
°C
0.5|VID|
–40
Operating free-air temperature, TA
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V
3
CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
driver electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
|VOD|
∆VOD
VOS
∆VOS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential output voltage
RL = 100 Ω
250
450
600
mV
VOD magnitude change
Offset voltage
50
mV
–40°C to 85°C
0.95
1.2
1.45
V
350
mV
VOS magnitude change
IOS
Output short circuit current
VBB
CO
Reference output voltage
VO = 0 V
|VOD| = 0 V
VDD = 2.5 V, IBB = –100 µA
Output capacitance
VO = VDD or GND
–20
20
1.15
1.25
1.35
3
mA
V
pF
receiver electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
VIDH
VIDL
Input threshold high
|VID|
IIH
Input differential voltage
IIL
CI
TEST CONDITIONS
MIN
TYP
MAX
100
Input threshold low
VI = VDD
VI = 0 V
Input current,
current CLK0/CLK0,
CLK0/CLK0 CLK1/CLK1
Input capacitance
UNIT
mV
–100
mV
200
mV
–5
5
VI = VDD or GND
5
3
µA
A
pF
supply current electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
IDD
Supply
Su
ly current
IDDZ
TEST CONDITIONS
MIN
TYP
MAX
Full loaded
All outputs enabled and loaded, RL = 100 Ω, f = 0 Hz
No load
Outputs enabled, no output load, f = 0 Hz
35
3-State
All outputs 3-state by control logic, f = 0 Hz
35
UNIT
130
mA
LVDS—switching characteristics over recommended operating free-air temperature range,
VDD = 2.5 V ±5%
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
MIN
TYP
MAX
UNIT
tPLH
Propagation delay low-to-high
CLK0, CLK0
CLK1, CLK1
Qn, Qn
2
3
ns
tPHL
Propagation delay high-to-low
CLK0, CLK0
CLK1, CLK1
Qn, Qn
2
3
ns
tduty
Duty cycle
CLK0, CLK0
CLK1, CLK1
Qn, Qn
tsk(o)
tsk(p)
Output skew
Any Qn, Qn
Pulse skew
Any Qn, Qn
50
ps
tsk(pp)
tr
Part-to-part skew
Any Qn, Qn
600
ps
Output rise time, 20% to 80%, RL = 100 Ω, CL = 5 pF
Any Qn, Qn
350
ps
tf
Output fall time, 20% to 80%, RL = 100 Ω, CL = 5 pF
Any Qn, Qn
350
ps
fclk
4
CLK0, CLK0
CLK1, CLK1
Max input frequency
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Any Qn, Qn
45%
55%
30
900
1100
ps
MHz
CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
control register characteristics over recommended operating free-air temperature range,
VDD = 2.5 V ±5%
PARAMETER
TEST CONDITIONS
MIN
100
TYP
MAX
Maximum frequency of shift register
2
ns
th
tremoval
Hold time, clock to SI
1.5
ns
Removal time, enable to clock
1.5
ns
tw
VIH
Clock pulse width, minimum
VIL
Logic input low
Setup time, clock to SI
Logic input high
VDD = 2.5 V
VDD = 2.5 V
Input current, CK pin
IIH
VI = VDD
Input current, SI and EN pins
Input current, CK pin
IIL
VI = GND
Input current, SI and EN pins
150
UNIT
fMAX
tsu
MHz
3
ns
2
V
0.8
–5
5
10
30
–10
–30
–5
5
V
µA
A
µA
A
specification of control register
The CDCLVD110 is provided with an 11-bit, serial-in shift register and an 11-bit control register. The control
Register enables/disables each output clock and selects either CLK0 or CLK1 as the input clock. The
CDCLVD110 has two modes of operation:
Programmable Mode (EN=1)
The shift register utilizes a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11
clock pulses, the twelfth clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9, Q9
output pair, and the tenth bit (bit 9) enables the Q0, Q0 pair. The eleventh bit (bit 10) on SI selects either
CLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To
restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK
(shift register clock input) and EN set to low. The control register can be configured only once after each
reset.
Standard Mode (EN=0)
In this mode, the CDCLVD110 is not programmable and all the clock outputs are enabled. The clock input
(CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register.
state-machine inputs
EN
SI
CK
OUTPUT
L
L
X
All outputs enabled, CLK0 selected, control register disabled, default state
L
H
X
All outputs enabled, CLK1 selected, control register disabled
H
L
↑
First stage stores L, other stage stores data of previous stage
H
H
First stage stores H, other stage stores data of previous stage
L
X
Reset of state machine, shift and control registers
control register
BIT 10
BITS [0–9]
QN[0–9]
CLK0
L
H
H
H
CLK1
X
L
Outputs disabled
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CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
serial input (SI) sequence
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CLK_SEL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
truth table for control logic
CK
EN
SI
CLK0
CLK0
CLK1
CLK1
L
L
L
L
L
L
L
H
X
L
H
L
X
L
L
Open
Open
L
L
H
X
L
L
H
X
L
L
H
X
X
All outputs enabled
Q (0–9)
Q(0–9)
X
L
H
X
H
L
X
X
L
H
X
L
H
L
H
X
H
L
H
L
Open
Open
L
H
X = Don’t care
APPLICATION INFORMATION
Fail-Safe information:
For VDD = 0 V (power-down mode) the CDCLVD110 has fail-safe input and output pins. In power-on mode,
fail-safe biasing at input pins can be accomplished with a 10-kΩ pullup resistor from CLK0/CLK1 to VDD and
a 10-kΩ pulldown resistor from CLK0/CLK1 to GND.
LVDS Receiver Input termination:
The LVDS receiver inputs need to have 100-Ω termination resistors placed as close as possible across the input
pins.
Control Inputs termination:
No external termination is required. The CK control input has an internal 120-kΩ pullup resistor while SI– and
EN– control inputs each have an internal 120-kΩ pulldown resistor. If the control pins are left open per the
default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled.
6
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CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
CLKIN
CLKIN
Q0
Q0
tPLH1
tPHL1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
tPLH9
tPHL9
Q1
Q1
Q2
Q2
Q3
Q3
Q9
Q9
Figure 1. Waveforms for Calculation of tsk(o) and tsk(pp)
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and the slowest tPLHn (n = 1, 2,…10)
– The difference between the fastest and the slowest tPHLn (n = 1, 2,…10)
B. Part–to–part skew, tsk(pp), is calculated as the greater of:
– The difference between the fastest and the slowest tPLHn (n = 1, 2,…10) across multiple devices
– The difference between the fastest and the slowest tPHLn (n = 1, 2,…10) across multiple devices
C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tPHL) and the low-to-high
(tPLH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tPHL – tPLH |. Pulse skew
is sometimes referred to as pulse width distortion or duty cycle skew.
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7
CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Differential Output Signal
VOD = (Qn) – (Qn)
80%
5%
250 mV
0-V
Differential
–250 mV
–5%
20%
t/2
t/2
Figure 2. Test Criteria for fclk, Duty Cycle, tr, tf, VOD
8
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CDCLVD110
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
SCAS684 – SEPTEMBER 2002
MECHANICAL DATA
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,25
0,80
24
0,20 M
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,05 MIN
0,25
0°–ā7°
1,45
1,35
Seating Plane
0,75
0,45
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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Copyright  2002, Texas Instruments Incorporated