TI LMR14206XMK/NOPB

LMR14206
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SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
LMR14206 SIMPLE SWITCHER® 42Vin, 0.6A Step-Down Voltage Regulator in SOT-23
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FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
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The LMR14206 is a PWM DC/DC buck (step-down)
regulator. With a wide input range from 4.5V-42V,
they are suitable for a wide range of applications
such as power conditioning from unregulated
sources. They feature a low RDSON (0.9Ω typical)
internal switch for maximum efficiency (85% typical).
Operating frequency is fixed at 1.25 MHz allowing the
use of small external components while still being
able to have low output voltage ripple. Soft-start can
be implemented using the shutdown pin with an
external RC circuit allowing the user to tailor the softstart time to a specific application.
1
2
Input Voltage Range of 4.5V to 42V
Output Voltage Range of 0.765V to 34V
Output Vurrent up to 0.6A
1.25 MHz Switching Frequency
Low Shutdown Iq, 16 µA Typical
Short Circuit Protected
Internally Compensated
Soft-Start Function
Thin 6-Pin SOT Package (2.97 x 1.65 x 1mm)
Fully Enabled for WEBENCH® Power Designer
PERFORMANCE BENEFITS
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Tight Accuracy for Powering Digital ICs
Extremely Easy to Use
Tiny Overall Solution Reduces System Cost
The LMR14206 is optimized for up to 600 mA load
current with a 0.765V nominal feedback voltage.
Additional features include: thermal shutdown, VIN
under-voltage lockout, and gate drive under-voltage
lockout. The LMR14206 is available in a low profile 6pin SOT package.
APPLICATIONS
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Point-of-Load Conversions from 5V, 12V, and
24V Rails
Space Constrained Applications
Battery Powered Equipment
Industrial Distributed Power Applications
Power Meters
Portable Hand-Held Instruments
System Performance
Efficiency vs Load Current
VIN = 24V, VOUT = 1.2V and 3.3V
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current
VIN = 12V, VOUT = 1.2V and 3.3V
70
60
50
40
30
20
60
50
40
30
20
10
10
1.2Vout
3.3Vout
0
0.0
70
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
1.2Vout
3.3Vout
0
0.6
0.0
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
0.6
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMR14206
SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
www.ti.com
CBOOT
L1
VOUT
LMR14206
VIN
VIN
CB
SHDN
SW
GND
FB
D1
R1
R2
CIN
COUT
Figure 1.
Connection Diagram
LMR14206
CB
1
GND
2
FB
3
PIN 1 ID
6
SW
5
VIN
4
SHDN
Figure 2. 6-Pin SOT (Top View)
See DDC Package
PIN DESCRIPTIONS
2
Pin
Name
1
CB
2
GND
3
FB
4
SHDN
Function
SW FET gate bias voltage. Connect CBOOT cap between CB and SW.
Ground connection.
Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)). Resistors should be
in the 100-10K range to avoid input bias errors.
Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If
this function is not used tie to VIN or leave open.
5
VIN
Power input voltage pin: 4.5V to 42V normal operating range.
6
SW
Power FET output: Connect to inductor, diode, and CBOOT cap.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN
-0.3V to +45V
SHDN
-0.3V to (VIN+0.3V) <45V
SW Voltage
-0.3V to +45V
CB Voltage above SW Voltage
7V
FB Voltage
-0.3V to +5V
Maximum Junction Temperature
Power Dissipation
150°C
(3)
Internally Limited
Lead Temperature
300°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
ESD Susceptibility Human Body Model (4)
1.5 kV
For soldering specifications see SNOA549
(1)
(2)
(3)
(4)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and
the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal
shutdown engages at TJ=175°C (typ.) and disengages at TJ=155°C (typ).
Human Body Model, applicable std. JESD22-A114-C.
Operating Conditions
Operating Junction Temperature Range (1)
−40°C to +125°C
Storage Temperature
−65°C to +150°C
Input Voltage VIN
4.5V to 42V
SW Voltage
(1)
Up to 42V
All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are ensured through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes
only. Unless otherwise stated the following conditions apply: VIN = 12V.
Symbol
IQ
Parameter
Quiescent current
Conditions
SHDN = 0V
Device On, No Load
1.35
1.85
0.9
1.6
Ω
0.0
0.5
µA
(3)
Switch leakage current
VIN = 42V
ICL
Switch current limit
See
(4)
See
(5)
tMIN
Minimum ON time
fSW
Switching frequency
VFB = 0.5V
0.95
0.1
1.0
0.765
0.782
VFB = 0V
Maximum duty cycle
Undervoltage lockout
thresholds
On threshold
Shutdown threshold
Device on
81
87
4.4
3.7
Shutdown pin input bias current VSHDN = 2.3V (5)
VSHDN = 0V
3.5
2.3
µA
V
ns
1.50
0.35
Off threshold
Device off
1.25
mA
A
100
VUVP
ISHDN
1.15
0.747
DMAX
VSHDN
µA
40
1.75
ILSW
FB Pin reference voltage
Units
16
See
Feedback pin bias current
Max (1)
1.30
Switch ON resistance
VFB
Typ (2)
Device On, Not Switching
RDSON
IFB
Min (1)
MHz
%
3.25
1.0
0.9
0.3
0.05
1.5
0.02
1.5
V
V
µA
THERMAL SPECIFICATIONS
RθJA
(1)
(2)
(3)
(4)
(5)
(6)
4
Junction-to-Ambient Thermal
Resistance, SOT Package
See
(6)
121
°C/W
All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
Includes the bond wires, RDSON from VIN pin to SW pin.
Current limit at 0% duty cycle.
Bias currents flow into pin.
All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to
JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution, number
of thermal vias, board size, ambient temperature, and air flow.
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Typical Performance Characteristics
Input UVLO vs. Temperature
SHDN Pin Current vs. SHDN Pin Voltage
Figure 3.
Figure 4.
Switching Node and Output Voltage Waveforms
Load Transient Waveforms
VIN = 12V, VOUT = 3.3V, IOUT = 200 mA
Top trace: VOUT, 10 mV/div, AC Coupled
Bottom trace: SW, 5V/div, DC Coupled
T = 1 µs/div
Figure 5.
VIN = 12V, VOUT = 3.3V, IOUT = 300 mA to 200 mA to 300 mA
Top trace: VOUT, 20 mV/div, AC Coupled
Bottom trace: IOUT, 100 mA/div, DC Coupled
T = 200 µs/div
Figure 6.
Switch Current Limit vs. SHDN Pin Voltage
(Soft-Start Implementation)
Start-Up Waveform
SWITCH CURRENT LIMIT (A)
1.2
VIN = 12V, VOUT = 3.3V, IOUT = 50 mA
Top trace: VOUT, 1V/div, DC Coupled
Bottom trace: SHDN, 2V/div, DC Coupled
T = 40 µs/div
Figure 7.
1.0
0.9
0.7
0.6
0.4
1.1
1.7
2.3
2.8
3.4
4.0
SHDN PIN VOLTAGE (V)
Figure 8.
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Block Diagram
CB
+
+
OSC
SET
FB
+
PWM
Comp
Error
Amp
+
Bandgap
Soft
Start
VIN
Max Duty
Cycle Limit
RESET
Inductor
Current
Measurement
DC
LIMIT
BUCK
DRIVE
FET
Driver
SW
UVLO
TSD
UVLO
Comp
Thermal
Shutdown
BG
Voltage
Regulator
GND
SHDN
6
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APPLICATION INFORMATION
PROTECTION
The LMR14206 has dedicated protection circuitry running during normal operation to protect the IC. The thermal
shutdown circuitry turns off the power device when the die temperature reaches excessive levels. The UVLO
comparator protects the power device during supply power startup and shutdown to prevent operation at
voltages less than the minimum input voltage. A gate drive (CB) under-voltage lockout is included to ensured that
there is enough gate drive voltage to drive the MOSFET before the device tries to start switching. The
LMR14206 also features a shutdown mode decreasing the supply current to approximately 16 µA.
CONTINUOUS CONDUCTION MODE
The LMR14206 contains a current-mode, PWM buck regulator. A buck regulator steps the input voltage down to
a lower output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady
state), the buck regulator operates in two cycles. The power switch is connected between VIN and SW. In the first
cycle of operation the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and
the load current is supplied by COUT and the rising current through the inductor. During the second cycle the
transistor is open and the diode is forward biased due to the fact that the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of
these two cycles determines the output voltage. The output voltage is defined approximately as:
D=VOUT/VIN and D’ = (1-D)
where
•
D is the duty cycle of the switch.
(1)
D and D' will be required for design calculations.
DESIGN PROCEDURE
This section presents guidelines for selecting external components.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the
front page schematic, Figure 1. The feedback pin voltage is 0.765V, so the ratio of the feedback resistors sets
the output voltage according to the following equation:
VOUT=0.765V(1+(R1/R2))
(2)
Typically R2 will be given as 100Ω-10 kΩ for a starting value. To solve for R1 given R2 and VOUT, use:
R1=R2((VOUT/0.765V)-1).
(3)
INPUT CAPACITOR
A low ESR ceramic capacitor (CIN) is needed between the VIN pin and GND pin. This capacitor prevents large
voltage transients from appearing at the input. Use a 2.2 µF-10 µF value with X5R or X7R dielectric. Depending
on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is
applied. Consult with the capacitor manufacturer's data sheet for information on capacitor derating over voltage
and temperature.
INDUCTOR SELECTION
The most critical parameters for the inductor are the inductance, peak current, and the DC resistance. The
inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages.
(VIN - VOUT)VOUT
L=
VIN x IRIPPLE x fSW
(4)
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A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, and current
stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage
ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the
ripple current increases with the input voltage, the maximum input voltage is always used to determine the
inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is
available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the
inductor copper loss equal 2% of the output power. See AN-1197 for more information on selecting inductors. A
good starting point for most applications is a 10 µH to 22 µH with 1.1A or greater current rating. Using such a
rating will enable the LMR14206 to current limit without saturating the inductor. This is preferable to the device
going into thermal shutdown mode and the possibility of damaging the inductor if the output is shorted to ground
or other longterm overload.
OUTPUT CAPACITOR
The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant
frequency, PWM mode is approximated by:
VRIPPLE = IRIPPLE(ESR+(1/(8fSWCOUT)))
(5)
The ESR term usually plays the dominant role in determining the voltage ripple. Low ESR ceramic capacitors are
recommended. Capacitors in the range of 22 µF-100 µF are a good starting point with an ESR of 0.1Ω or less.
BOOTSTRAP CAPACITOR
A 0.15 µF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications
where the input voltage is less than twice the output voltage a larger capacitor is recommended, generally 0.15
µF to 1 µF to ensure plenty of gate drive for the internal switches and a consistently low RDSON.
SOFT-START COMPONENTS
The LMR14206 has circuitry that is used in conjunction with the SHDN pin to limit the inrush current on start-up
of the DC/DC switching regulator. The SHDN pin in conjunction with a RC filter is used to tailor the soft-start for a
specific application. When a voltage applied to the SHDN pin is between 0V and up to 2.3V it will cause the cycle
by cycle current limit in the power stage to be modulated for minimum current limit at 0V up to the rated current
limit at 2.3V. Thus controlling the output rise time and inrush current at startup. The resistor value should be
selected so the current sourced into the SHDN pin will be greater then the leakage current of the SHDN pin (1.5
µA ) when the voltage at SHDN is equal or greater then 2.3V.
SHUTDOWN OPERATION
The SHDN pin of the LMR14206 is designed so that it may be controlled using 2.3V or higher logic signals. If the
shutdown function is not to be used the SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin
should not exceed 42V. If the use of a higher voltage is desired due to system or other constraints it may be
used, however a 100 kΩ or larger resistor is recommended between the applied voltage and the SHDN pin to
protect the device.
SCHOTTKY DIODE
The breakdown voltage rating of the diode (D1) is preferred to be 25% higher than the maximum input voltage.
The current rating for the diode should be equal to the maximum output current for best reliability in most
applications. In cases where the duty cycle is greater than 50%, the average diode current is lower. In this case it
is possible to use a diode with a lower average current rating, approximately (1-D)IOUT, however the peak current
rating should be higher than the maximum load current. A 0.5A to 1A rated diode is a good starting point.
8
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LAYOUT CONSIDERATIONS
To reduce problems with conducted noise pick up, the ground side of the feedback network should be connected
directly to the GND pin with its own connection. The feedback network, resistors R1 and R2, should be kept
close to the FB pin, and away from the inductor to minimize coupling noise into the feedback pin. The input
bypass capacitor CIN must be placed close to the VIN pin. This will reduce copper trace resistance which effects
input voltage ripple of the IC. The inductor L1 should be placed close to the SW pin to reduce EMI and capacitive
coupling. The output capacitor, COUT should be placed close to the junction of L1 and the diode D1. The L1, D1,
and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall
efficiency. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the
system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane. For more detail on switching power supply layout considerations see Application Note AN1149: Layout Guidelines for Switching Power Supplies SNVA021.
Typical Applications
CBOOT
LMR14206
L1
15 PH
3.3V OUT
0.15 PF
4.5V to 42V IN
VIN
CB
SHDN
SW
GND
FB
D1
60V 1A
R1
3.4k
R2
1.02k
CIN
2.2 PF
COUT
47 PF
Figure 9. Application Circuit, 3.3V Output
CBOOT
LMR14206
L1
15 PH
5V OUT
0.15 PF
7V to 42V IN
VIN
CB
SHDN
SW
GND
FB
D1
60V 1A
R1
5.62k
CIN
2.2 PF
R2
1.02k
COUT
47 PF
Figure 10. Application Circuit, 5V Output
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L1
47 PH
CBOOT
LMR14206
12V OUT
0.15 PF
15V to 42V IN
VIN
CB
SHDN
SW
GND
FB
D1
60V 1A
R1
14.7k
CIN
2.2 PF
COUT
22 PF
R2
1k
Figure 11. Application Circuit, 12V Output
CBOOT
LMR14206
L1
47 PH
15V OUT
0.15 PF
18V to 42V IN
VIN
CB
SHDN
SW
GND
FB
D1
60V 1A
R1
28k
CIN
2.2 PF
COUT
22 PF
R2
1.5k
Figure 12. Application Circuit, 15V Output
L1
10 PH
CBOOT
LMR14206
0.8V OUT
0.15 PF
4.5V to 12V IN
VIN
CB
SHDN
SW
GND
FB
D1
60V 1A
R1
30.9
CIN
2.2 PF
COUT
100 PF
R2
787
Figure 13. Application Circuit, 0.8V Output
10
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMR14206XMK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SJ2B
LMR14206XMKE/NOPB
ACTIVE
SOT
DDC
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SJ2B
LMR14206XMKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SJ2B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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PACKAGE MATERIALS INFORMATION
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8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMR14206XMK/NOPB
SOT
DDC
6
LMR14206XMKE/NOPB
SOT
DDC
LMR14206XMKX/NOPB
SOT
DDC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
6
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMR14206XMK/NOPB
SOT
DDC
6
1000
210.0
185.0
35.0
LMR14206XMKE/NOPB
SOT
DDC
6
250
210.0
185.0
35.0
LMR14206XMKX/NOPB
SOT
DDC
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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