SCBS031B − FEBRUARY 1989 − REVISED SEPTEMBER 1994
•
•
•
•
•
•
•
DW OR N PACKAGE
(TOP VIEW)
BiCMOS Design Significantly Reduces
Standby Current
3-State True Outputs Drive Bus Lines or
Buffer Memory-Address Registers
High-Impedance State During Power Up
and Power Down
P-N-P Inputs Reduce DC Loading
Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
ESD Protection Exceeds 2000 V
Per MIL-STD-883C, Method 3015
Package Options Include Plastic
Small-Outline (DW) Packages and
Standard Plastic (N) 300-mil DIPs
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
description
The SN64BCT541A octal buffer and line driver is ideal for driving bus lines or buffering memory-address
registers. The device features inputs and outputs on opposite sides of the package to facilitate
printed-circuit-board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all eight outputs are in the high-impedance state. The outputs are in a high-impedance state during
power up and power down while the supply voltage is less than approximately 3 V.
The SN64BCT541A is characterized for operation from − 40°C to 85°C and from 0°C to 70°C.
FUNCTION TABLE
INPUTS
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Copyright 1994, Texas Instruments Incorporated
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POST OFFICE BOX 655303
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1
SCBS031B − FEBRUARY 1989 − REVISED SEPTEMBER 1994
logic symbol†
1
OE1
OE2
A1
A2
A3
A4
A5
A6
A7
A8
logic diagram (positive logic)
OE1
&
EN
19
2
OE2
18
1
3
17
4
16
5
15
6
14
7
13
8
12
9
11
A1
Y1
1
19
2
18
Y1
Y2
Y3
Y4
To Seven Other Channels
Y5
Y6
Y7
Y8
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input negative voltage rating may be exceeded if the input clamp current rating is observed.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
V
Input clamp current
−18
mA
IOH
IOL
High-level output current
−15
mA
Low-level output current
64
mA
TA
Operating free-air temperature
85
°C
2
High-level input voltage
2
−40
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
V
V
SCBS031B − FEBRUARY 1989 − REVISED SEPTEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 4.5 V,
VOH
VCC = 4.5 V
VOL
IOZH
VCC = 4.5 V,
VCC = 5.5 V,
IOZL
VCC = 5.5 V,
VCC = 0 to 2.3 V (power up)
IOZ
II
IIH
IIL
IOS‡
ICCL
ICCH
ICCZ
Ci
Co
MIN
II = −18 mA
IOH = − 3 mA
IOH = − 15 mA
IOH = 64 mA
TYP†
2.4
3.3
2
3.1
0.42
VO = 2.7 V
VO = 0.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V
V
V
0.55
V
50
µA
−50
µA
" 50
µA
A
VI = 7 V
VI = 2.7 V
0.1
20
µA
VI = 0.5 V
VO = 0
−0.6
mA
−225
mA
47
72
mA
27
40
mA
5
7
mA
−100
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V,
VCC = 5 V,
UNIT
−1.2
" 50
OE at 0.8 V
VO = 2.7 V or 0.5 V,
VCC = 1.8 V to 0 (power down)
VCC = 5.5 V,
MAX
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
mA
5
pF
10
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C
•
TA = 0°C
to 70°C
MIN
TYP
MAX
MIN
MAX
MIN
2.1
3.7
5.3
1.7
6.3
1.7
6
3.7
5.5
7.5
3.2
8.7
3.4
8.2
4.5
7.2
9.3
4.4
11
3.9
10.7
5
8
10.4
5.4
12.4
4.4
11.5
3.5
5.6
7.6
3
9.1
3
8.6
3.9
5.2
7.2
3
9.4
3
8.6
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•
UNIT
TA = − 40°C
to 85°C
MAX
ns
ns
ns
3
SCBS031B − FEBRUARY 1989 − REVISED SEPTEMBER 1994
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
S1
Open
(all others)
From Output
Under Test
Test
Point
CL
(see Note A)
R1
From Output
Under Test
R1
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
RL = R1 = R2
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
Timing Input
(see Note B)
3V
1.5 V
1.5 V
0V
1.5 V
tw
0V
Data Input
(see Note B)
3V
th
tsu
Low-Level
Pulse
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
(see Note D)
VOH
1.5 V
1.5 V
VOL
VOH
1.5 V
1.5 V
0V
tPLZ
1.5 V
Waveform 1
(see Notes C and D)
3.5 V
VOL
tPHZ
tPLH
1.5 V
1.5 V
tPZL
tPHL
tPHL
Out-of-Phase
Output
(see Note D)
Output
Control
(low-level enable)
0.3 V
tPZH
Waveform 2
(see Notes C and D)
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
4
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
SN64BCT541ADW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
Samples Not Available
SN64BCT541ADWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
Samples Not Available
SN64BCT541AN
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
Samples Not Available
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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