TI TPA6011A4PWPG4

TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
3-W STEREO AUDIO POWER AMPLIFIER
WITH ADVANCED DC VOLUME CONTROL
FEATURES
•
•
•
•
DESCRIPTION
Advanced DC Volume Control With 2-dB
Steps
From -40 dB to 20 dB
– Fade Mode
– Maximum Volume Setting for SE Mode
– Adjustable SE Volume Control
Referenced to BTL Volume Control
3 W Into 3-Ω Speakers
Stereo Input MUX
Differential Inputs
The TPA6011A4 is a stereo audio power amplifier
that drives 3 W/channel of continuous RMS power
into a 3-Ω load. Advanced dc volume control
minimizes external components and allows BTL
(speaker) volume control and SE (headphone) volume control. Notebook and pocket PCs benefit from
the integrated feature set that minimizes external
components without sacrificing functionality.
To simplify design, the speaker volume level is
adjusted by applying a dc voltage to the VOLUME
terminal. Likewise, the delta between speaker volume
and headphone volume can be adjusted by applying
a dc voltage to the SEDIFF terminal. To avoid an
unexpected high volume level through the
headphones, a third terminal, SEMAX, limits the
headphone volume level when a dc voltage is applied. Finally, to ensure a smooth transition between
active and shutdown modes, a fade mode ramps the
volume up and down.
APPLICATIONS
•
•
•
Notebook PC
LCD Monitors
Pocket PC
APPLICATION CIRCUIT
Right
Speaker
ROUT+
1
PGND
SE/BTL
CS
2
3
Power Supply
ROUTHP/LINE
24
VDD
23
100 kΩ
22
100 kΩ
DC VOLUME CONTROL
CC
30
20
10
1 kΩ
PVDD
RHPIN
Ci
5
Right Line
Audio Source
RLINEIN
21
SEDIFF
20
Ci
6
CS
RIN
-10
VOLUME
SEMAX
19
In From DAC
or
Potentiometer
(DC Voltage)
VDD
7
Ci
8
VDD
AGND
LIN
BYPASS
C(BYP)
9
CC
LLINEIN
Ci
10
Left HP
Audio Source
11
Power Supply
CS
12
FADE
LHPIN SHUTDOWN
PVDD
LOUT+
LOUT-
PGND
-20
-30
SE Volume,
SEDIFF [Pin 20] = 0 V
-40
-50
17
Ci
Left Line
Audio Source
Headphone
s
18
Volume - dB
4
BTL Volume
0
Ci
Right HP
Audio Source
1 kΩ
SE Volume,
SEDIFF [Pin 20] = 1 V
-60
16
-70
15
System
Control
14
13
BTL Volume (dB) ∝ Volume (V)
SE Volume (dB) ∝ Volume (V) - SEDIFF
(V)
-80
Left
Speaker
-90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Volume [Pin 21] - V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
AVAILABLE OPTIONS
PACKAGE
TA
24-PIN TSSOP (PWP) (1)
40°C to 85°C
(1)
TPA6011A4PWP
The PWP package is available taped and reeled. To order a taped
and reeled part, add the suffix R to the part number
(e.g., TPA6011A4PWPR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VSS
Supply voltage, VDD, PVDD
VI
Input voltage
-0.3 V to 6 V
-0.3 V to VDD+0.3 V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
-40°C to 85°C
TJ
Operating junction temperature range
-40°C to 150°C
Tstg
Storage temperature range
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PWP
2.7 mW
21.8 mW/°C
1.7 W
1.4 W
RECOMMENDED OPERATING CONDITIIONS
VSS
Supply voltage, VDD, PVDD
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
2
SE/BTL, HP/LINE, FADE
SHUTDOWN
MIN
MAX
4.0
5.5
UNIT
V
0.8 × VDD
V
2
V
0.6 × VDD
SE/BTL, HP/LINE, FADE
SHUTDOWN
-40
V
0.8
V
85
°C
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = PVDD = 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5.5 V, Gain = 0 dB, SE/BTL = 0 V
30
mV
VDD = 5.5 V, Gain = 20 dB, SE/BTL = 0 V
50
mV
| VOO |
Output offset voltage (measured differentially)
PSRR
Power supply rejection ratio
VDD = PVDD = 4.0 V to 5.5 V
| IIH |
High-level input current (SE/BTL, FADE, HP/LINE,
SHUTDOWN, SEDIFF, SEMAX, VOLUME)
VDD = PVDD = 5.5 V,
VI = VDD = PVDD
1
µA
| IIL |
Low-level input current (SE/BTL, FADE, HP/LINE,
SHUTDOWN, SEDIFF, SEMAX, VOLUME)
VDD = PVDD = 5.5 V, VI = 0 V
1
µA
IDD
Supply current, no load
-42
-70
dB
VDD = PVDD = 5.5 V, SE/BTL = 0 V,
SHUTDOWN = 2 V
6.0
7.5
9.0
VDD = PVDD = 5.5 V, SE/BTL = 5.5 V,
SHUTDOWN = 2 V
3.0
5
6
IDD
Supply current, max power into a 3-Ω load
VDD = 5 V = PVDD, SE/BTL = 0 V,
SHUTDOWN = 2 V, RL = 3Ω,
PO = 2 W, stereo
IDD(SD)
Supply current, shutdown mode
SHUTDOWN = 0.0 V
mA
1.5
1
ARMS
20
µA
OPERATING CHARACTERISTICS
TA = 25°C, VDD = PVDD = 5 V, RL = 3 Ω, Gain = 6 dB (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
THD = 1%, f = 1 kHz
2
THD = 10%, f = 1 kHz, VDD = 5.5 V
3
MAX
UNIT
PO
Output power
THD+N
Total harmonic distortion + noise
PO = 1 W, RL = 8 Ω , f = 20 Hz to 20 kHz
VOH
High-level output voltage
RL = 8 Ω, Measured between output and VDD
700
mV
VOL
Low-level output voltage
RL = 8 Ω, Measured between output and GND
400
mV
2.85
V
V(Bypass Bypass voltage (Nominally VDD/2)
W
<0.4%
Measured at pin 17, No load, VDD = 5.5 V
2.65
2.75
)
BOM
ZI
Maximum output power bandwidth
THD = 5%
Supply ripple rejection ratio
f = 1 kHz, Gain = 0 dB, C(BYP) = 0.47 µF
Noise output voltage
f = 20 Hz to20 kHz, Gain = 0 dB,
C(BYP) = 0.47 µF
Input impedance (see Figure 26)
VOLUME = 5.0 V
>20
kHz
BTL
-63
dB
SE
-57
dB
BTL
36
µVRMS
14
kΩ
3
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
PWP PACKAGE
(TOP VIEW)
PGND
ROUTPVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
Terminal Functions
TERMINAL
NAME
PGND
NO.
I/O
DESCRIPTION
1, 13
-
Power ground
LOUT-
12
O
Left channel negative audio output
PVDD
3, 11
-
Supply voltage terminal for power stage
LHPIN
10
I
Left channel headphone input, selected when HP/LINE is held high
LLINEIN
9
I
Left channel line input, selected when HP/LINE is held low
LIN
8
I
Common left channel input for fully differential input. AC ground for single-ended inputs.
VDD
7
-
Supply voltage terminal
RIN
6
I
Common right channel input for fully differential input. AC ground for single-ended inputs.
RLINEIN
5
I
Right channel line input, selected when HP/LINE is held low
RHPIN
4
I
Right channel headphone input, selected when HP/LINE is held high
ROUT-
2
O
Right channel negative audio output
ROUT+
24
O
Right channel positive audio output
SHUTDOWN
15
I
Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal
FADE
16
I
Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high is
placed on this terminal
BYPASS
17
I
Tap to voltage divider for internal midsupply bias generator used for analog reference
AGND
18
-
Analog power supply ground
SEMAX
19
I
Sets the maximum volume for single ended operation. DC voltage range is 0 to VDD.
SEDIFF
20
I
Sets the difference between BTL volume and SE volume. DC voltage range is 0 to VDD.
VOLUME
21
I
Terminal for dc volume control. DC voltage range is 0 to VDD.
HP/LINE
22
I
Input MUX control. When logic high, RHPIN and LHPIN inputs are selected. When logic low, RLINEIN and
LLINEIN inputs are selected.
SE/BTL
23
I
Output MUX control. When this terminal is high, SE outputs are selected. When this terminal is low, BTL
outputs are selected.
LOUT+
14
O
Left channel positive audio output.
4
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM
RHPIN
RLINEIN
R
MUX
_
_
+
HP/LINE
ROUT+
+
RIN
BYP
BYP
+
_
_
ROUT-
+
EN
BYP
SE/BTL
HP/LINE
SE/BTL
MUX
Control
PVDD
PGND
VDD
Power
Management
VOLUME
32-Step
Volume
Control
SEDIFF
SEMAX
SHUTDOWN
AGND
FADE
LHPIN
LLINEIN
L
MUX
BYPASS
_
_
HP/LINE
+
LOUT+
+
LIN
BYP
BYP
+
_
_
LOUT-
+
BYP
EN
SE/BTL
NOTE: All resistor wipers are adjusted with 32 step volume control.
5
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 1. DC Volume Control (BTL Mode, VDD = 5 V) (1)
VOLUME (PIN 21)
(1)
(2)
6
FROM (V)
TO (V)
GAIN OF AMPLIFIER
(Typ)
0.00
0.26
-85 (2)
0.33
0.37
-40
0.44
0.48
-38
0.56
0.59
-36
0.67
0.70
-34
0.78
0.82
-32
0.89
0.93
-30
1.01
1.04
-28
1.12
1.16
-26
1.23
1.27
-24
1.35
1.38
-22
1.46
1.49
-20
1.57
1.60
-18
1.68
1.72
-16
1.79
1.83
-14
1.91
1.94
-12
2.02
2.06
-10
2.13
2.17
-8
2.25
2.28
-6 (2)
2.36
2.39
-4
2.47
2.50
-2
2.58
2.61
0
2.70
2.73
2
2.81
2.83
4
2.92
2.95
6
3.04
3.06
8
3.15
3.17
10
3.26
3.29
12
3.38
3.40
14
3.49
3.51
16
3.60
3.63
18
3.71
5.00
20 (2)
For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
Tested in production. Remaining gain steps are specified by design.
TPA6011A4
www.ti.com
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 2. DC Volume Control (SE Mode, VDD = 5 V) (1)
SE_VOLUME = VOLUME - SEDIFF or SEMAX
(1)
(2)
FROM (V)
TO (V)
GAIN OF AMPLIFIER
(Typ)
0.00
0.26
-85 (2)
0.33
0.37
-46
0.44
0.48
-44
0.56
0.59
-42
0.67
0.70
-40
0.78
0.82
-38
0.89
0.93
-36
1.01
1.04
-34
1.12
1.16
-32
1.23
1.27
-30
1.35
1.38
-28
1.46
1.49
-26
1.57
1.60
-24
1.68
1.72
-22
1.79
1.83
-20
1.91
1.94
-18
2.02
2.06
-16
2.13
2.17
-14
2.25
2.28
-12
2.36
2.39
-10
2.47
2.50
-8
2.58
2.61
-6 (2)
2.70
2.73
-4
2.81
2.83
-2
2.92
2.95
0 (2)
3.04
3.06
2
3.15
3.17
4
3.26
3.29
6 (2)
3.38
3.40
8
3.49
3.51
10
3.60
3.63
12
3.71
5.00
14
For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
Tested in production. Remaining gain steps are specified by design.
7
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
THD+N
Total harmonic distortion plus noise (BTL)
THD+N
Total harmonic distortion plus noise (SE)
vs Frequency
1, 2 3
vs Output power
6, 7, 8
vs Frequency
4, 5
vs Output power
9
vs Output voltage
10
Closed loop response
ICC
Supply current
PD
PO
11, 12
vs Temperature
13
vs Supply voltage
14, 15, 16
Power Dissipation
vs Output power
17, 18
Output power
vs Load resistance
19, 20
Crosstalk
vs Frequency
21, 22
HP/LINE attenuation
vs Frequency
23
PSRR
Power supply ripple rejection (BTL)
vs Frequency
24
PSRR
Power supply ripple rejection (SE)
vs Frequency
25
ZI
Input impedance
vs BTL gain
26
Vn
Output noise voltage
vs Frequency
27
10
VDD = 5 V
RL = 3 Ω
Gain = 20 dB
BTL
5
2
1
0.5
PO = 0.5 W
0.2
0.1
PO = 1 W
0.05
0.02
PO = 1.75 W
0.01
20
100
1k
f − Frequency − Hz
Figure 1.
8
10 k 20 k
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise (BTL) − %
THD+N − Total Harmonic Distortion + Noise (BTL) − %
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
10
5
2
VDD = 5 V
RL = 4 Ω
Gain = 20 dB
BTL
1
PO = 1.5 W
0.5
PO = 0.25 W
0.2
0.1
0.05
PO = 1 W
0.02
0.01
20
50
100 200
500 1 k 2 k
f − Frequency − Hz
Figure 2.
5 k 10 k
20 k
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
10
VDD = 5 V
RL = 8 Ω
Gain = 20 dB
BTL
5
2
1
PO = 0.25 W
0.5
PO = 0.5 W
0.2
0.1
0.05
0.02
0.01
PO = 1 W
20
50 100 200
500
1k
2k
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise (SE) − %
THD+N − Total Harmonic Distortion + Noise (BTL) − %
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
5 k 10 k 20 k
10
VDD = 5 V
RL = 32 Ω
Gain = 14 dB
SE
5
2
1
0.5
0.2
0.1
0.05
PO = 75 mW
0.02
0.01
50 100 200
20
1k
2k
5 k 10 k 20 k
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
VDD = 5 V
RL = 10 kΩ
Gain = 14 dB
SE
5
2
1
0.5
0.2
0.1
0.05
VO = 1 VRMS
0.02
0.01
20
50 100 200
500 1 k 2 k
f − Frequency − Hz
Figure 5.
5 k 10 k 20 k
THD+N − Total Harmonic Distortion + Noise (BTL) − %
THD+N − Total Harmonic Distortion + Noise (SE) − %
500
f − Frequency − Hz
f − Frequency − Hz
10
5
2
VDD = 5 V
RL = 3 Ω
Gain = 20 dB
BTL
1
f = 20 kHz
0.5
0.2
f = 1 kHz
0.1
0.05
0.02
0.01
0.01
f = 20 Hz
0.1
1
PO − Output Power − W
10
Figure 6.
9
TPA6011A4
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
VDD = 5 V
RL = 4 Ω
Gain = 20 dB
BTL
5
2
1
20 kHz
0.5
0.2
1 kHz
0.1
20 Hz
0.05
0.02
0.01
0.02
0.05 0.1 0.2
0.5
1
PO − Output Power − W
5
10
VDD = 5 V
RL = 8 Ω
Gain = 20 dB
BTL
5
2
1
0.5
20 kHz
0.2
0.1
1 kHz
0.05
20 Hz
0.02
0.01
0.02
0.05 0.1 0.2
0.5
1
PO − Output Power − W
2
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT VOLTAGE
10
5
2
VDD = 5 V
RL = 32 Ω
Gain = 14 dB
SE
1
0.5
0.2
20 Hz
0.1
0.05
0.02
0.01
10 m
20 kHz
1 kHz
50 m
100 m
PO − Output Power − W
Figure 9.
10
2
THD+N − Total Harmonic Distortion + Noise (BTL) − %
10
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise (SE) − %
THD+N − Total Harmonic Distortion + Noise (SE) − %
THD+N − Total Harmonic Distortion + Noise (BTL) − %
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
200 m
5
10
5
VDD = 5 V
RL = 10 kΩ
Gain = 14 dB
SE
2
1
0.5
0.2
0.1
20 kHz
0.05
0.02
0.01
1 kHz
0.005
20 Hz
0.002
0.001
0
500 m
1
1.5
VO − Output Voltage − rms
Figure 10.
2
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
CLOSED LOOP RESPONSE
20
Closed Loop Gain − dB
10
Gain
150
30
120
20
120
90
10
90
0
60
−10
30
0
60
−10
30
−20
0
Phase
−30
−30
−40
−60
−50
−20
−90
−120
−60
−70
−150
−70
100
1k
10 k
f − Frequency − Hz
100 k
−90
VDD = 5 Vdc
RL = 8 Ω
Mode = BTL
Gain = 20 dB
100
−120
−150
1k
10 k
−180
1M
100 k
f − Frequency − Hz
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
VDD = 5 V
Mode = BTL
SHUTDOWN = VDD
Mode = BTL
SHUTDOWN = VDD
9
TA = 125°C
8
I DD − Supply Current − mA
I DD − Supply Current − mA
8
−60
−80
10
10
9
−30
−40
−60
−180
1M
0
Phase
−30
−50
−80
10
150
Gain
Phase − Degrees
30
180
40
Closed Loop Gain − dB
VDD = 5 Vdc
RL = 8 Ω
Mode = BTL
Gain = 0 dB
CLOSED LOOP RESPONSE
180
Phase − Degrees
40
7
6
5
4
3
2
7
6
TA = 25°C
5
4
3
TA = −40°C
2
1
1
0
0
−40 −25 −10
−1
5
20 35 50 65
80 95
110 125
0
0.5
1
1.5
2
2.5
3
3.5
4
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
Figure 13.
Figure 14.
4.5
5 5.5
11
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
450
7
Mode = SE
SHUTDOWN = VDD
TA = 125°C
I DD − Supply Current − nA
IDD − Supply Current − mA
6
5
4
TA = 25°C
3
2
1
TA = 125°C
300
250
200
150
TA = −40°C
TA = 25°C
50
0
0
0
0.5
1 1.5 2 2.5 3 3.5 4 4.5
VDD − Supply Voltage − V
5 5.5
0
0.5
1
1.5 2 2.5 3 3.5
VDD − Supply Voltage − V
4
Figure 15.
Figure 16.
POWER DISSIPATION (PER CHANNEL)
vs
OUTPUT POWER
POWER DISSIPATION (PER CHANNEL)
vs
OUTPUT POWER
4.5
5
200
2
VDD = 5 V
BTL
1.8
PD− Power Dissipation (PER CHANNEL) − mW
PD− Power Dissipation (PER CHANNEL) − W
350
100
TA =−40°C
3Ω
1.6
1.4
4Ω
1.2
1
0.8
0.6
8Ω
0.4
0.2
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4
PO − Output Power − W
Figure 17.
12
Mode = SD
SHUTDOWN = 0 V
400
1.6 1.8
2
VDD = 5 V
SE
180
8Ω
160
140
120
100
16 Ω
80
60
32 Ω
40
20
0
0
50
100
150
200
PO − Output Power − mW
Figure 18.
250
300
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SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
2.2
3.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
8
16
24
32
40
48
RL − Load Resistance − Ω
56
64
−20
1.2
1
0.8
THD+N = 1%
0
8
16
24
32
40
48
RL − Load Resistance − Ω
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
56
64
0
VDD = 5 V
PO = 1 W
RL = 8 Ω
Gain = 0dB
BTL
−10
−20
−30
−40
−50
−60
−70
−80
VDD = 5 V
PO = 1 W
RL = 8 Ω
Gain = 20 dB
BTL
−40
−50
−60
−70
−80
−90
−90
Left to Right
−100
Left to Right
−100
−110
−120
20
THD+N = 10%
Figure 20.
Crosstalk − dB
Crosstalk − dB
−30
2
1.8
1.6
1.4
Figure 19.
0
−10
2.4
2.2
0.6
0.4
0.2
0
0.2
0
VDD = 5.5 V
Gain = 20 dB
BTL
2.6
PO − Output Power − W
2
PO − Output Power − W
3
2.8
VDD = 5 V
THD+N = 1%
Gain = 20 dB
BTL
Right to Left
100
1k
f − Frequency − Hz
Figure 21.
10 k 20 k
Right to Left
−110
−120
20
100
1k
f − Frequency − Hz
10 k 20 k
Figure 22.
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POWER SUPPLY REJECTION RATIO (BTL)
vs
FREQUENCY
0
−10
HP/Line Attenuation − dB
−20
−30
VDD = 5 V
VI = 1 VRMS
RL = 8 Ω
BTL
−40
−50
−60
−70
HP Active
−80
−90
Line Active
−100
−110
−120
20
100
1k
PSRR − Power Supply Rejection Ratio (BTL) − dB
HP/LINE ATTENUATION
vs
FREQUENCY
0
VDD = 5 V
RL = 8 Ω
C(BYP) =0.47 µF
BTL
−10
−20
−30
−40
−50
Gain = 10
−60
Gain = 1
−70
−80
20
10 k 20 k
100
POWER SUPPLY REJECTION RATIO (SE)
vs
FREQUENCY
INPUT IMPEDANCE
vs
BTL GAIN
90
VDD = 5 V
RL = 32 Ω
C(BYP) =0.47 µF
SE
80
70
−30
−40
Gain = 0 dB
−50
−60
Gain = 14 dB
−70
60
50
40
30
−80
20
−90
10
−100
20
14
Figure 24.
+0
−20
10 k 20 k
Figure 23.
ZI − Input Impedamce − kΩ
PSRR − Power Supply Rejection Ratio (SE) − dB
f − Frequency − Hz
−10
1k
f − Frequency − Hz
100
1k
10 k 20 k
0
−40
−30
−20
−10
f − Frequency − Hz
BTL Gain − dB
Figure 25.
Figure 26.
0
10
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OUTPUT NOISE VOLTAGE
vs
FREQUENCY
V n − Output Noise Voltage − µ V RMS
180
160
140
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 8 Ω
BTL
120
Gain = 20 dB
100
80
60
Gain = 0 dB
40
20
0
10
100
1k
10 k
20 k
f − Frequency − Hz
Figure 27.
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APPLICATION INFORMATION
SELECTION OF COMPONENTS
Figure 28 and Figure 29 are schematic diagrams of typical notebook computer application circuits.
Right
Speaker
ROUT+
1
PGND
SE/BTL
CS
2
3
Power Supply
VDD
24
23
CC
100 kΩ
ROUTHP/LINE
22
100 kΩ
1 kΩ
PVDD
Ci
4
Right HP
Audio Source
RHPIN
Ci
5
Right Line
Audio Source
21
VOLUME
RLINEIN
SEDIFF
RIN
SEMAX
VDD
AGND
20
Ci
6
CS
19
In From DAC
or
Potentiometer
(DC Voltage)
VDD
7
Ci
8
LIN
Headphones
18
C(BYP)
17
BYPASS
Ci
Left Line
Audio Source
9
LLINEIN
Ci
10
Left HP
Audio Source
11
Power Supply
CS
A.
CC
12
LHPIN
FADE
16
15
SHUTDOWN
PVDD
LOUT+
LOUT-
PGND
1 kΩ
14
13
System
Control
Left
Speaker
A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 28. Typical TPA6011A4 Application Circuit Using Single-Ended Inputs and Input MUX
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APPLICATION INFORMATION (continued)
Right
Speaker
ROUT+
1
PGND
SE/BTL
CS
2
NC
4
5
6
CS
100 kΩ
100 kΩ
HP/LINE
1 kΩ
PVDD
RHPIN
21
VOLUME
RLINEIN
SEDIFF
RIN
SEMAX
VDD
AGND
20
Ci
Right Positive
Differential Input Signal
19
In From DAC
or
Potentiometer
(DC Voltage)
VDD
7
Ci
Left Positive Differential
Input Signal
8
LIN
Headphones
18
C(BYP)
17
BYPASS
Ci
9
Left Negative
Differential Input Signal
NC
10
11
Power Supply
CS
A.
CC
ROUT-
Ci
Right Negative
Differential Input Signal
23
22
3
Power Supply
VDD
24
12
CC
LLINEIN
LHPIN
PVDD
LOUT-
FADE
15
SHUTDOWN
LOUT+
PGND
1 kΩ
16
System
Control
14
13
Left
Speaker
A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 29. Typical TPA6011A4 Application Circuit Using Differential Inputs
SE/BTL OPERATION
The ability of the TPA6011A4 to easily switch between BTL and SE modes is one of its most important cost
saving features. This feature eliminates the requirement for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode but external headphone or speakers must be
accommodated. Internal to the TPA6011A4, two separate amplifiers drive OUT+ and OUT-. The SE/BTL input
controls the operation of the follower amplifier that drives LOUT- and ROUT-. When SE/BTL is held low, the
amplifier is on and the TPA6011A4 is in the BTL mode. When SE/BTL is held high, the OUT- amplifiers are in a
high output impedance state, which configures the TPA6011A4 as an SE driver from LOUT+ and ROUT+. IDD is
reduced by approximately one-third in SE mode. Control of the SE/BTL input can be from a logic-level CMOS
source or, more typically, from a resistor divider network as shown in Figure 30. The trip level for the SE/BTL
input can be found in the recommended operating conditions table.
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APPLICATION INFORMATION (continued)
4
RHPIN
5
RLINEIN
R
MUX
_
_
ROUT+
+
22
6
HP/LINE
24
+
Input
MUX
Control
Bypass
RIN
Bypass
VDD
+
_
_
ROUT-
2
+
Bypass
100 kΩ
CO
330 µF
1 kΩ
EN
SE/BTL
23
100 kΩ
LOUT+
Figure 30. TPA6011A4 Resistor Divider Network Circuit
Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When
closed the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ resistor is
disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT- amplifier is shut down
causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output
capacitor (Co) into the headphone jack.
HP/LINE OPERATION
The HP/LINE input controls the internal input multiplexer (MUX). Refer to the block diagram in Figure 30. This
allows the device to switch between two separate stereo inputs to the amplifier. For design flexibility, the
HP/LINE control is independent of the output mode, SE or BTL, which is controlled by the aforementioned
SE/BTL pin. To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches from
BTL mode to SE mode, simply connect the SE/BTL control input to the HP/LINE input.
When this input is logic high, the RHPIN and LHPIN inputs are selected. When this terminal is logic low, the
RLINEIN and LLINEIN inputs are selected. This operation is also detailed in Table 3 and the trip levels for a logic
low (VIL) or logic high (VIH) can be found in the recommended operating conditions table.
SHUTDOWN MODES
The TPA6011A4 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, IDD = 20 µA. SHUTDOWN should never be left unconnected
because amplifier operation would be unpredictable.
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Table 3. HP/LINE, SE/BTL, and Shutdown Functions
INPUTS (1)
(1)
AMPLIFIER STATE
HP/LINE
SE/BTL
SHUTDOWN
INPUT
OUTPUT
X
X
Low
X
Mute
Low
Low
High
Line
BTL
Low
High
High
Line
SE
High
Low
High
HP
BTL
High
High
High
HP
SE
Inputs should never be left unconnected.
FADE OPERATION
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.
When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the
recommended operating conditions table.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel
gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock
frequency of 58 Hz, this equates to 34 ms (1/24 Hz) per step. The gain steps down until the lowest gain step is
reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown.
For example, if the amplifier is in the highest gain mode of 20 dB, the time it takes to ramp down the channel
gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the
highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor
from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a
0.47-µF capacitor that is used in the application diagram in Figure 28, the time is approximately 500 ms. This
time scales linearly with the value of bypass capacitor. For example, if a 1-µF capacitor is used for bypass, the
time period to discharge the capacitor to ground is twice that of the 0.47-µF capacitor, or 1 second. Figure 30
below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode.
The gain is set to the highest level and the output is at VDD when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the
start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of
VDD/2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage applied
to the VOLUME, SEDIFF, and SEMAX pins.
In the fade-off mode, the amplifier stores the gain value prior to starting the shutdown sequence. The output of
the amplifier immediately drops to VDD/2 and the bypass capacitor begins a smooth discharge to ground. When
shutdown is released, the bypass capacitor charges up to VDD/2 and the channel gain returns immediately to the
value stored in memory. Figure 31 below is a waveform captured at the output during the shutdown sequence
when the part is in the fade-off mode. The gain is set to the highest level, and the output is at VDD when the
amplifier is shut down.
The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not
change the power-up sequence. Upon a power-up condition, the TPA6011A4 begins in the lowest gain setting
and steps up 2 dB every 2 clock cycles until the final value is reached as determined by the dc voltage applied to
the VOLUME, SEDIFF, and SEMAX pins.
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Device Shutdown
Device Shutdown
ROUT+
ROUT+
Figure 31. Shutdown Sequence in the
Fade-on Mode
Figure 32. Shutdown Sequence in the
Fade-off Mode
VOLUME, SEDIFF, AND SEMAX OPERATION
Three pins labeled VOLUME, SEDIFF, and SEMAX control the BTL volume when driving speakers and the SE
volume when driving headphones. All of these pins are controlled with a dc voltage, which should not exceed
VDD.
When driving speakers in BTL mode, the VOLUME pin is the only pin that controls the gain. Table 1 shows the
gain for the BTL mode. The voltages listed in the table are for VDD = 5 V. For a different VDD, the values in the
table scale linearly. If VDD = 4 V, multiply all the voltages in the table by 4 V/5 V, or 0.8.
The TPA6011A4 allows the user to specify a difference between BTL gain and SE gain. This is desirable to avoid
any listening discomfort when plugging in headphones. When switching to SE mode, the SEDIFF and SEMAX
pins control the singe-ended gain proportional to the gain set by the voltage on the VOLUME pin. When SEDIFF
= 0 V, the difference between the BTL gain and the SE gain is 6 dB. Refer to the section labeled bridged-tied
load versus single-ended load for an explanation on why the gain in BTL mode is 2x that of single-ended mode,
or 6dB greater. As the voltage on the SEDIFF terminal is increased, the gain in SE mode decreases. The voltage
on the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to
determine the SE gain.
Some audio systems require that the gain be limited in the single-ended mode to a level that is comfortable for
headphone listening. Most volume control devices only have one terminal for setting the gain. For example, if the
speaker gain is 20 dB, the gain in the headphone channel is fixed at 14 dB. This level of gain could cause
discomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging in
headphones. The SEMAX terminal controls the maximum gain for single-ended mode.
The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain. A block diagram of the
combined functionality is shown in Figure 33. The value obtained from the block diagram for SE_VOLUME is a
dc voltage that can be used in conjunction with Table 2 to determine the SE gain. Again, the voltages listed in
the table are for VDD = 5 V. The values must be scaled for other values of VDD.
Table 1 and Table 2 show a range of voltages for each gain step. There is a gap in the voltage between each
gain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresis
ensures that the gain control is monotonic and does not oscillate from one gain step to another. If a
potentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer is
turned in one direction and decreases as it is turned back the other direction. The trip point, where the gain
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actually changes, is different depending on whether the voltage is increased or decreased as a result of the
hysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate states
where the gain could be in the next higher gain step or the lower gain step depending on the direction the
voltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensure
that the desired gain is achieved.
A pictorial representation of the volume control can be found in Figure 34. The graph focuses on three gain steps
with the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about each gain
step.
SEDIFF (V)
SEMAX (V)
VOLUME (V)
VOLUME-SEDIFF
Is SEMAX>
(VOLUME-SEDIFF)
?
YES
SE_VOLUME (V) = VOLUME (V) - SEDIFF (V)
NO
SE_VOLUME (V) = SEMAX (V)
Figure 33. Block Diagram of SE Volume Control
4
BTL Gain - dB
+
2
0
2.61
2.70
2.73
2.81
Voltage on VOLUME Pin - V
Figure 34. DC Volume Control Operation
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INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB
or cutoff frequency also changes by over six times.
Rf
C
Ri
IN
Input Signal
Figure 35. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in Figure 26.
The -3-dB frequency can be calculated using Equation 1.
ƒ3 dB 1
2 CR
i
(1)
INPUT CAPACITOR, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Ri) form a
high-pass filter with the corner frequency determined in Equation 2.
−3 dB
fc(highpass) 1
2 Ri C i
fc
(2)
The value of Ci is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where Ri is 70 kΩ and the specification calls for a flat-bass response down to 40 Hz.
Equation 2 is reconfigured as Equation 3.
1
C i
2 R fc
i
(3)
In this example, Ci is 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
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POWER SUPPLY DECOUPLING, C(S)
The TPA6011A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 µF placed as close as possible to the device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, C(BYP)
The midrail bypass capacitor (C(BYP)) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor (C(BYP)) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended
for the best THD and noise performance. For the best pop performance, choose a value for C(BYP) that is equal to
or greater than the value chosen for Ci. This ensures that the input capacitors are charged up to the midrail
voltage before C(BYP) is fully charged to the midrail voltage.
OUTPUT COUPLING CAPACITOR, C(C)
In the typical single-supply SE configuration, an output coupling capacitor (C(C)) is required to block the dc bias at
the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.
−3 dB
fc(high) 1
2 RL C (C)
fc
(4)
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives
the low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass low
frequencies into the load. Consider the example where a C(C) of 330 µF is chosen and loads vary from 3Ω ,4 Ω,
8 Ω, 32Ω , 10 kΩ, and 47 kΩ. Table 4 summarizes the frequency response characteristics of each configuration.
Table 4. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
C(C)
LOWEST
FREQUENCY
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
RL
32 Ω
330 µF
15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
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As Table 4 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance, the more the real capacitor behaves like an ideal capacitor.
BRIDGED-TIED LOAD vs SINGLE-ENDED LOAD
Figure 36 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6011A4 BTL amplifier
consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this
differential drive configuration, but, initially consider power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation,
where voltage is squared, yields 4× the output power from the same supply rail and load impedance (see
Equation 5).
V(rms) Power V O(PP)
2 2
V(rms)
2
RL
(5)
VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 36. Bridge-Tied Load Configuration
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In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which
is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider
the single-supply SE configuration shown in Figure 37. A coupling capacitor is required to block the dc offset
voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so they
tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting
low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network
created with the speaker impedance and the coupling capacitance and is calculated with Equation 6.
f(c) 1
2 RL C C
(6)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
-3 dB
VO(PP)
C(C)
RL
VO(PP)
fc
Figure 37. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal
considerations section.
SINGLE-ENDED OPERATION
In SE mode (see Figure 37), the load is driven from the primary amplifier output for each channel (OUT+).
The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.
BTL AMPLIFIER EFFICIENCY
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 38).
25
TPA6011A4
www.ti.com
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
IDD
VO
IDD(avg)
V(LRMS)
Figure 38. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
PL
Efficiency of a BTL amplifier P SUP
Where:
2
V rms 2
V
V
PL L
, and VLRMS P , therefore, P L P
2
RL
2RL
and P SUP VDD I DDavg
and
I DDavg 1
0
VP
VP
1
[cos(t)] 0 2V P
sin(t) dt RL
RL
RL
Therefore,
P SUP 2 VDD V P
RL
(7)
substituting PL and PSUP into Equation 7,
2
Efficiency of a BTL amplifier VP
2 RL
2 V DD VP
RL
VP
4 V DD
Where:
VP 2 PL R L
Therefore,
BTL 2 PL R L
4 V DD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(8)
Table 5 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, the maximum draw
on the power supply is almost 3.25 W.
26
TPA6011A4
www.ti.com
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 5. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems
(1)
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK VOLTAGE
(V)
INTERNAL DISSIPATION
(W)
0.25
31.4
2.00
0.55
0.50
44.4
2.83
0.62
1.00
62.8
4.00
0.59
1.25
70.2
4.47 (1)
0.53
High peak voltages cause the THD to increase.
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in equation 8, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
CREST FACTOR AND THERMAL CONSIDERATIONS
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. From the TPA6011A4 data sheet, one can
see that when the TPA6011A4 is operating from a 5-V supply into a 3-Ω speaker, that 4-W peaks are available.
Use equation 9 to convert watts to dB.
P
P dB 10Log W 10Log 4 W 6 dB
1W
P ref
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
• 6 dB - 15 dB = -9 dB (15-dB crest factor)
• 6 dB - 12 dB = -6 dB (12-dB crest factor)
• 6 dB - 9 dB = -3 dB (9-dB crest factor)
• 6 dB - 6 dB = 0 dB (6-dB crest factor)
• 6 dB - 3 dB = 3 dB (3-dB crest factor)
To convert dB back into watts use equation 10.
P W 10PdB10 Pref
= 63 mW (18-db crest factor)
= 125 mW (15-db crest factor)
= 250 mW (12-db crest factor)
= 500 mW (9-db crest factor)
= 1000 mW (6-db crest factor)
= 2000 mW (3-db crest factor)
(10)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the worst case, which is 2 W of continuous power output with a 3-dB crest factor,
against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system.
Using the power dissipation curves for a 5-V, 3-Ω system, the internal dissipation in the TPA6011A4 and
maximum ambient temperatures is shown in Table 6.
27
TPA6011A4
www.ti.com
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 6. TPA6011A4 Power Rating, 5-V, 3-Ω Stereo
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
4
2 W (3 dB)
1.7
-3°C
4
1 W (6 dB)
1.6
6°C
4
500 mW (9 dB)
1.4
24°C
4
250 mW (12 dB)
1.1
51°C
4
125 mW (15 dB)
0.8
78°C
4
63 mW (18 dB)
0.6
96°C
Table 7. TPA6011A4 Power Rating, 5-V, 8-Ω Stereo
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
2.5
1250 mW (3-dB crest factor)
0.55
100°C
2.5
1000 mW (4-dB crest factor)
0.62
94°C
2.5
500 mW (7-dB crest factor)
0.59
97°C
2.5
250 mW (10-dB crest factor)
0.53
102°C
The maximum dissipated power (PD(max)) is reached at a much lower output power level for an 8-Ω load than for
a 3-Ω load. As a result, this simple formula for calculating PD(max) may be used for an 8-Ω application.
2V2
DD
P D(max) 2
RL
(11)
However, in the case of a 3-Ω load, the PD(max) occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula for
a 3-Ω load.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the PWP package is shown in the dissipation rating table. Use equation 12 to convert this to θJA. .
1
1
Θ JA 45°CW
0.022
Derating Factor
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per
channel, so the dissipated power needs to be doubled for two channel operation. Givenθ JA, the maximum
allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be
calculated using Equation 13. The maximum recommended junction temperature for the TPA6011A4 is 150°C.
The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.
T A Max T J Max ΘJA P D
150 45(0.6 2) 96°C (15-dB crest factor)
(13)
NOTE:
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per
channel.
Table 6 and Table 7 show that some applications require no airflow to keep junction temperatures in the
specified range. The TPA6011A4 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Table 6 and Table 7 were calculated for maximum
listening volume without distortion. When the output level is reduced the numbers in the table change
significantly. Also, using 8-Ω speakers increases the thermal performance by increasing amplifier efficiency.
28
THERMAL PAD MECHANICAL DATA
www.ti.com
PWP (R-PDSO-G24)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
13
24
Exposed Thermal Pad
2,40
1,65
1
12
5,16
4,10
Top View
NOTE: All linear dimensions are in millimeters
PPTD030
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPA6011A4PWP
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA6011
TPA6011A4PWPG4
ACTIVE
HTSSOP
PWP
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA6011
TPA6011A4PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA6011
TPA6011A4PWPRG4
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA6011
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPA6011A4PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA6011A4PWPR
HTSSOP
PWP
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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