TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 D D D D D D Low rDS(on) . . . 0.38 Ω Typ Voltage Output . . . 60 V Input Protection Circuitry . . . 18 V Pulsed Current . . . 3 A Per Channel Extended ESD Capability . . . 4000 V Direct Logic-Level Interface D PACKAGE (TOP VIEW) GND SOURCE1 GATE2 DRAIN2 1 8 2 7 3 6 4 5 DRAIN1 GATE1 SOURCE2 NC NC – No internal connection description The TPIC5223L is a monolithic gate-protected logic-level power DMOS array that consists of two electrically isolated independent N-channel enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC5223L is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature of – 40°C to 125°C. schematic DRAIN1 8 DRAIN2 4 GATE2 3 Q1 Q2 D1 D2 Z1 7 GATE1 ZC1b Z2 ZC2b ZC1a ZC2a 2 1 SOURCE1 GND 6 SOURCE2 NOTE A: For correct operation, no terminal may be taken below GND. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 9 V to 18 V Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A Continuous gate-to-source zener diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . 108 mJ Continuous total power dissipation, TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.95 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage V(BR)GS V(BR)SG Gate-to-source breakdown voltage TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 5 VGS = 0 VDS = VGS, IGS = 250 µA ISG = 250 µA Source-to-gate breakdown voltage MIN TYP MAX 60 1.5 V 2.05 2.2 V 9 V 100 V Reverse drain-to-GND breakdown voltage (across D1, D2) Drain-to-GND current = 250 µA VDS(on) Drain-to-source on-state voltage ID = 1 A, See Notes 2 and 3 VF(SD) Forward on-state voltage, source-to-drain IS = 1 A, VGS = 0 (Z1, Z2), See Notes 2 and 3 and Figure 12 VF Forward on-state voltage, GND-to-drain ID = 1 A (D1, D2), See Notes 2 and 3 IDSS Zero gate voltage drain current Zero-gate-voltage VDS = 48 V,, VGS = 0 TC = 25°C TC = 125°C IGSSF IGSSR Forward-gate current, drain short circuited to source Reverse-gate current, drain short circuited to source VGS = 15 V, VSG = 5 V, VDS = 0 VDS = 0 Ilk lkg current drain-to-GND drain to GND Leakage current, VDGND = 48 V TC = 25°C TC = 125°C 0.05 1 0.5 10 0.38 0.43 Static drain-to-source drain to source on-state on state resistance VGS = 5 V, ID = 1 A,, See Notes 2 and 3 and Figures 6 and 7 TC = 25°C rDS(on) DS( ) TC = 125°C 0.61 0.65 VGS = 5 V, Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source Crss Short-circuit reverse transfer capacitance, common source VDS = 25 V, f = 1 MHz, 0.375 0.425 V 0.85 1.2 V 3 VDS = 15 V, ID = 500 mA, See Notes 2 and 3 and Figure 9 Forward transconductance V 18 V(BR) gfs UNIT V 0.05 1 0.5 10 20 200 nA 10 100 nA µA µA Ω 1.2 VGS = 0, See Figure 11 1.49 S 150 190 100 125 40 50 pF F NOTES: 2. Technique should limit TJ – TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25°C PARAMETER trr Reverse recovery time Reverse-recovery QRR Total diode charge TEST CONDITIONS IS = 500 mA, VGS = 0 0, See Figures 1 and 14 POST OFFICE BOX 655303 VDS = 48 V, di/dt = 100 A/µs A/µs, • DALLAS, TEXAS 75265 MIN TYP Z1 and Z2 50 D1 and D2 210 Z1 and Z2 50 D1 and D2 800 MAX UNIT ns nC 3 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX 34 70 20 40 28 55 td(on) td(off) Turn-on delay time tr1 tf2 Rise time Fall time 15 30 Qg Total gate charge 3.1 3.8 Qgs(th) Threshold gate-to-source charge 0.5 0.6 Qgd Gate-to-drain charge 1.9 2.3 LD LS Internal drain inductance 5 Internal source inductance 5 Rg Internal gate resistance Turn-off delay time RL = 50 Ω,, See Figure 2 VDD = 25 V,, tf1 = 10 ns, VDS = 48 V, V See Figure 3 ID = 500 mA, A tr1 = 10 ns,, VGS = 5 V, V UNIT ns nC nH Ω 0.25 thermal resistance PARAMETER TEST CONDITIONS MIN TYP RθJA Junction-to-ambient thermal resistance See Notes 4 and 7 130 RθJB Junction-to-board thermal resistance See Notes 5 and 7 78.6 See Notes 6 and 7 34 RθJP Junction-to-pin thermal resistance NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power PARAMETER MEASUREMENT INFORMATION 1.5 VDS = 48 V VGS = 0 TJ = 25°C Z1, and Z2‡ I S – Source-to-Drain Diode Current – A 1 Reverse di/dt = 100 A/µs 0.5 0 25% of IRM† – 0.5 Shaded Area = QRR –1 – 1.5 IRM† –2 trr(SD) – 2.5 0 50 100 150 200 250 300 350 400 450 Time – ns † IRM = maximum recovery current ‡ The above waveform is representative of D1 and D2 in shape only. 500 Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT °C/W TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V RL Pulse Generator tr1 VDS 5V VGS VGS 0V DUT Rgen tf1 50 Ω td(off) td(on) CL = 30 pF (see Note A) 50 Ω tr2 tf2 VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms Current Regulator 12-V Battery 0.2 µF Same Type as DUT 50 kΩ 0.3 µF Qg 5V Qgs(th) VDD VDS 0V Qgd VGS DUT IG = 100 µA Gate Voltage Time IG CurrentSampling Resistor ID CurrentSampling Resistor VOLTAGE WAVEFORM TEST CIRCUIT Figure 3. Gate-Charge Test Circuit and Voltage Waveform POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tav tw 14 mH Pulse Generator (see Note A) ID 5V VGS VDS 0V IAS (see Note B) VGS 50 Ω ID DUT 0V Rgen 50 Ω V(BR)DSX = 60 V Min VDS 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration (tw) is increased until peak current IAS = 3 A. I V t av AS (BR)DSX 108 mJ, where t av Energy test level is defined as E AS 2 + + + avalanche time. Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 1 2.5 VDS = VGS 2 ID = 1 mA ID = 100 µA 1.5 1 0.5 0 – 40 – 20 0 20 40 60 80 100 120 140 160 TJ – Junction Temperature – °C ID = 1 A r DS(on) – Static Drain-to-Source On-State Resistance – Ω VGS(th) – Gate-to-Source Threshold Voltage – V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0.8 0.6 VGS = 4.5 V 0.4 VGS = 5 V 0.2 0 – 40 – 20 Figure 5 6 0 20 40 60 80 100 120 140 160 TJ – Junction Temperature – °C Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 3 1 0.9 0.8 0.7 TJ = 25°C VGS = 4 V 0.6 0.5 I D – Drain Current – A On-State Resistance – Ω r DS(on) – Static Drain-to-Source STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT VGS = 4.5 V 0.4 VGS = 5 V 0.3 nVGS = 0.2 V TJ = 25°C 2 1 0.2 VGS = 3 V 0 0.1 1 ID – Drain Current – A 10 1 2 3 4 5 6 7 8 9 VDS – Drain-to-Source Voltage – V Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 50 40 TJ = 75°C I D – Drain Current – A 35 30 25 20 15 2 1 TJ = 125°C 10 TJ = 25°C TJ = 150°C 5 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 1.475 TJ = – 40°C 1.470 Percentage of Units – % 3 Total Number of Units = 1554 VDS = 15 V ID = 500 mA TJ = 25°C 45 0 10 0 0 1 2 3 4 5 VGS – Gate-to-Source Voltage – V gfs – Forward Transconductance – S Figure 9 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 10 350 280 245 I SD – Source-to-Drain Diode Current – A 315 C – Capacitance – pF VGS = 0 VGS = 0 f = 1 MHz TJ = 25°C Ciss(0) = 245 pF Coss(0) = 3700 pF Crss(0) = 132 pF 210 175 Ciss 140 Coss 105 70 Crss 35 4 8 12 16 20 24 28 32 36 TJ = 125°C TJ = 25°C TJ = 150°C TJ = 75°C 0.1 0.1 0 0 TJ = – 40°C 1 40 VDS – Drain-to-Source Voltage – V 1 VSD – Source-to-Drain Voltage – V Figure 11 Figure 12 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 200 10 8 6 30 4 20 VDD = 48 V 10 2 0 0 0.5 1 1.5 2 2.5 3 3.5 180 D1 and D2 160 140 120 100 80 60 Z1 and Z2 40 4 4.5 5 0 0 100 200 300 400 Reverse di/dt – A/µs Qg – Gate Charge – nC Figure 13 8 VDS = 48 V VGS = 0 IS = 500 mA TJ = 25°C See Figure 1 20 VDD = 20 V 0 trr – Reverse-Recovery Time – ns VDD = 20 V VDD = 30 V 40 220 12 ID = 500 mA TJ = 25°C See Figure 3 50 REVERSE-RECOVERY TIME vs REVERSE di/dt VGS – Gate-to-Source Voltage – V VDS – Drain-to-Source Voltage – V 60 10 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 500 600 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 5 10 I AS – Maximum Peak Avalanche Current – A I D – Maximum Drain Current – A TC = 25°C 1 µs† 1 ms† 10 ms† 1 ÁÁ ÁÁ ÁÁ 0.1 0.1 500 µs† θJA§ θJP‡ DC Conditions 1 10 VDS – Drain-to-Source Voltage – V 100 See Figure 4 4 3 TC = 25°C TC = 125°C 2 1 0.01 0.1 1 10 100 tav – Time Duration of Avalanche – ms † Less than 2% duty cycle ‡ Device mounted in intimate contact with infinite heatsink. § Device mounted on FR4 printed-circuit board with no heatsink. Figure 16 Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC5223L 2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 THERMAL INFORMATION D PACKAGE† JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions RθJB – Junction-to-Board Thermal Resistance – °C/W d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 d = 0.01 1 tc Single Pulse tw ID 0 0.1 0.0001 0.001 0.01 0.1 tw – Pulse Duration – s † Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE A: ZθB(t) = r(t) RθJB tw pulse duration tc cycle time d duty cycle tw tc + + + 10 + ń Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 10 100 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPIC5223LD OBSOLETE SOIC D Pins Package Eco Plan (2) Qty 8 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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