CXA3355ER GPS Down Converter IC Description The CXA3355ER is an IC developed as a GPS RF down converter. This IC realizes a reduction in the number of external parts by integrating an LNA, image rejection mixer, IF filter, PLL and VCO (L, C) into a small package with low current consumption. Features • Includes all functions required for the GPS down converter • Low voltage operation: VCC = 1.6 to 2.0V • Low current consumption (active mode): 11mA (Typ. at VCC = 1.8V, IF ≈ 1MHz) • Low current consumption (power save mode) < 1µA • Total gain ≈ 100dB • Total NF ≈ 4dB • On-chip VCO and PLL • Supports typical TCXO frequencies (13MHz, 16.368MHz, 18.414MHz, etc.) • On-chip LNA (LNA NF: 2.0dB) • Image rejection mixer • On-chip IF filter, and an external filter can be connected as an option for further band narrowing. • 1-bit IF output • Antenna sense function 44 pin VQFN (Plastic) Absolute Maximum Ratings (Ta • Supply voltage VCC1 VCC2 VCC3 • Operating temperature Topr • Storage temperature Tstg = 25°C) –0.2 to +2.5 V –0.2 to +3.6 V –0.2 to +3.6 V –40 to +85 °C –65 to +150 °C Recommended Operating Conditions 1.6 to 2.0 Supply voltage VCC1 VCC2 1.6 to 3.3 VCC3 2.7 to 3.3 V V V Applications GPS down converter IC Structure SiGe BiCMOS monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04156-PS CXA3355ER GND (RF) GND (RF) RF_INP RF_INN GND VCC1 (LNA) LNA_OUT GND GND LNA_IN GND (LNA) Block Diagram and Pin Configuration 33 32 31 30 29 28 27 26 25 24 23 1540fo = 1575.42MHz VCC1 (RF) 34 22 GND (LNA) LNA RF_AMP 21 GND (LNA) VCC1 (RF) 35 Mixer Mixer TESTINP 36 20 VCO_I 1536fo [1539fo] TESTINN 37 19 C_VCO 90˚ 4fo [fo] TESTOUTP 38 IF_AMP1 18 GND PLL IF_AMP1 MC DMPS TESTOUTN 39 PFD SC CP 17 LPF IF Phase Shifter VCC1 (IF) 40 RC 16 VCC1 (PLL) GND (IF) 41 ×2 15 GND (PLL) R_EXT1 42 14 TCXO IF_AMP2 LPF HPF BIAS 13 CLK_OUT CTL 12 LT 2 3 4 5 6 7 8 DIAG AILIM GND (ANT) VCC3 (ANT) C_EXT DATA_OUT VCC2 (IF) 9 10 11 CLK 1 ASENS ANT SENSE DATA R_EXT2 44 A/D Converter GND (IF) ENABLE 43 fo mode: IF = 1.023MHz 4fo mode: IF = 4.092MHz –2– CXA3355ER Pin Description Pin No. Symbol Standard pin voltage [V] DC Equivalent circuit AC Description VCC3 (ANT) 1 ASENS — 1 — Antenna sense input. GND (ANT) VCC3 (ANT) 2 DIAG — — Antenna sense output. 2 GND (ANT) VCC3 (ANT) 3 AILIM — 3 — Antenna sense current limitation. Connect to the external PNP transistor base pin. GND (ANT) 4 GND (ANT) 0 — Antenna sense GND. 5 VCC3 (ANT) 3.0 — Antenna sense VCC. Leave open when not using the antenna sense function. VCC1 (IF) 6 6 C_EXT 1.2 Capacitor connection for canceling the offset. — GND (IF) –3– CXA3355ER Pin No. Symbol Standard pin voltage [V] DC Equivalent circuit Description AC VCC2 (IF) 7 DATA_OUT — 1.8Vp-p 7 Data (IF) output. GND (IF) 8 VCC2 (IF) 1.8 — IF block VCC. 9 GND (IF) 0 — IF block GND. 10 DATA — — 11 CLK — — VCC2 (IF) VCC1 (PLL) Serial data input. 10 Serial data clock input. 11 12 12 LT — — GND (PLL) Latch signal input. VCC2 (IF) 13 CLK_OUT — 1.8Vp-p 13 TCXO clock output. Leave open when not using the TCXO clock. GND (IF) VCC1 (PLL) 14 TCXO — — Reference frequency input. 14 GND (PLL) 15 GND (PLL) 0 — PLL block GND. 16 VCC1 (PLL) 1.8 — PLL block VCC. –4– CXA3355ER Pin No. Symbol Standard pin voltage [V] DC Equivalent circuit AC Description VCC1 (PLL) 17 LPF 1.2 — PLL loop filter connection. 17 GND (PLL) 18 GND 0 — GND. VCC1 (RF) 19 C_VCO 1.1 19 — Capacitor connection for decoupling the VCO bias circuit. GND (RF) VCC1 (RF) 20 VCO_I 0.1 Capacitor connection for decoupling the VCO bias circuit. — 20 GND (RF) 21 GND (LNA) 0 — LNA block GND. 22 GND (LNA) 0 — LNA block GND. 23 GND (LNA) 0 — LNA block GND. 24 LNA_IN 0.8 — VCC1 (LNA) LNA input. 27 24 27 LNA_OUT 1.8 — LNA output. GND (LNA) –5– CXA3355ER Pin No. Symbol Standard pin voltage [V] DC AC Equivalent circuit Description 25 GND 0 — GND. 26 GND 0 — GND. 28 VCC1 (LNA) 1.8 — LNA block VCC. 29 GND 0 — GND. 30 RF_INN 1.7 — VCC1 (RF) RF amplifier input. 31 30 31 RF_INP 1.7 — GND (RF) 32 GND (RF) 0 — RF block GND. 33 GND (RF) 0 — RF block GND. 34 VCC1 (RF) 1.8 — RF block VCC. 35 VCC1 (RF) 1.8 — RF block VCC. VCC1 (IF) 36 TESTINP 1.3 IF signal input when using an external filter. — 36 37 37 TESTINN 1.3 IF signal input when using an external filter. — GND (IF) VCC1 (IF) 38 TESTOUTP 0.5 IF signal output when using an external filter. — 38 39 39 TESTOUTN 0.5 IF signal output when using an external filter. — GND (IF) 40 VCC1 (IF) 1.8 — IF block VCC. 41 GND (IF) 0 — IF block GND. –6– CXA3355ER Pin No. Symbol Standard pin voltage [V] DC Equivalent circuit AC Description VCC1 (IF) 42 R_EXT1 0.5 External resistor connection. (bias) — 42 GND (IF) VCC2 (IF) 43 ENABLE — VCC1 (IF) ENABLE signal input. High (V_IH: 1.2V min.): Active mode Low (V_IL: 0.2V max.): Power save mode — 43 GND (IF) VCC1 (IF) 44 R_EXT2 1.2 External resistor connection. (bias) — 44 GND (IF) –7– CXA3355ER Electrical Characteristics DC Characteristics Item (VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25°C) Symbol Conditions Min. Typ. Max. Unit Supply current 1 ICC1 fo mode, excluding the antenna sense circuit 7 11 15 mA Supply current 2 ICC2 4fo mode, excluding the antenna sense circuit 9 13 17 mA Supply current 3 ICC3 Power save mode — 0.1 1 µA Input impedance Zin Pin 36 (TESTINP), Pin 37 (TESTINN) 50 100 200 Ω Output impedance Zout Pin 38 (TESTOUTP), Pin 39 (TESTOUTN) 50 100 200 Ω Note: fo mode and 4fo mode use the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz 4fo mode: TCXO = 16.368MHz, fLO = 1571.328MHz, IF = 4.092MHz AC Characteristics Item (VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25°C) Symbol Conditions Min. Typ. Max. Unit Total voltage gain G Excluding the A/D converter 85 100 — dB LNA NF1 NF1 50Ω matching, fo mode — 3.0 6 dB LNA NF2 NF2 50Ω matching, 4fo mode — 2.0 5 dB Total NF1 TNF1 50Ω matching, fo mode — 5.0 8.5 dB Total NF2 TNF2 50Ω matching, 4fo mode — 4.0 7.5 dB P-1dB input P1dB Up to before the A/D converter — –100 — dBm Image rejection ratio IMRR Detuning frequency = 1.023MHz, 4.092MHz — –40 –20 dBc LPF1 (fo mode) LPF1 @150kHz Normalized at the 1.023MHz level –5 — 4 dB LPF2 (fo mode) LPF2 @2.046MHz Normalized at the 1.023MHz level –13 — 2 dB LPF3 (fo mode) LPF3 @6MHz Normalized at the 1.023MHz level — — –13 dB BPF1 (4fo mode) BPF1 @1MHz Normalized at the 4.092MHz level — — –6 dB BPF2 (4fo mode) BPF2 @3.069MHz Normalized at the 4.092MHz level –9 — 6.5 dB BPF3 (4fo mode) BPF3 @5.115MHz Normalized at the 4.092MHz level –9 — 6.5 dB BPF4 (4fo mode) BPF4 @12MHz — — –6 dB C/N 100K C/N 4fo mode, TCXO = 16.368MHz — –70 –55 dBc/Hz Spurious component Sp 4fo mode, ratio of the carrier level and the reference leak level — –40 — dBc Normalized at the 4.092MHz level Note: fo mode and 4fo mode use the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz 4fo mode: TCXO = 16.368MHz, fLO = 1571.328MHz, IF = 4.092MHz –8– CXA3355ER IF Output Signal (DATA_OUT) Item Symbol (VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25°C) Conditions Min. Typ. Max. Unit DATA_OUT rise time DTr Pin 7 (DATA_OUT) 10 to 90% Load = 1MΩ//13pF — 6 — ns DATA_OUT fall time DTf Pin 7 (DATA_OUT) 10 to 90% Load = 1MΩ//13pF — 4 — ns (VCC1 = 1.8 ± 0.2V, VCC1 ≤ VCC2 ≤ 3.3V, 2.7V ≤ VCC3 ≤ 3.3V, Ta = 25°C) ENABLE Signal Item Symbol Conditions Min. Typ. Max. Unit Input voltage high level EVIH Pin 43 (ENABLE) input voltage high level threshold voltage 1.2 — VCC2 + 0.2 V Input voltage low level EVIL Pin 43 (ENABLE) input voltage low level threshold voltage –0.1 — 0.2 V Power-on Reset Function Item Allowable rise time Symbol MTr (VCC1 = 1.8 ± 0.2V, VCC1 ≤ VCC2 ≤ 3.3V, 2.7V ≤ VCC3 ≤ 3.3V, Ta = 25°C) Conditions Min. Typ. Max. Unit ENABLE and power supply (VCC1, VCC2) rise time for the power-on reset function to operate. Note: Use an ENABLE and power supply (VCC1, VCC2) rise time of 100ms or less. — — 100 ms TCXO (VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25°C) Item Symbol Conditions Min. Typ. Max. Unit Input level Vtcxo Input level to Pin 14 (TCXO) 0.2 0.6 1.2 Vp-p CLK_OUT rise time CTr Pin 13 (CLK_OUT) 10 to 90% Load = 1MΩ//13pF — 6 — ns CLK_OUT fall time CTf Pin 13 (CLK_OUT) 10 to 90% Load = 1MΩ//13pF — 4 — ns Threshold Voltage Value Item Symbol (VCC1 = 1.8 ± 0.2V, VCC1 ≤ VCC2 ≤ 3.3V, 2.7V ≤ VCC3 ≤ 3.3V, Ta = 25°C) Conditions Min. Typ. Max. Unit Logic input voltage high level VIH Logic input pins = Pin 10 (DATA), Pin 11 (CLK), Pin 12 (LT) VCC2 – 0.2 — VCC2 + 0.2 V Logic input voltage low level VIL Logic input pins = Pin 10 (DATA), Pin 11 (CLK), Pin 12 (LT) –0.1 — 0.2 V Logic output pin = Pin 2 (DIAG) VCC3 – 0.2 — VCC3 V Logic output pins = Pin 7 (DATA_OUT), Pin 13 (CLK_OUT) VCC2 – 0.2 — VCC2 V Logic output pins = Pin 7 (DATA_OUT), Pin 13 (CLK_OUT) 0 — 0.2 V Logic output voltage high level VOH Logic output voltage low level VOL –9– CXA3355ER Threshold Voltage Value (Antenna Sense) Item Symbol (VCC1 = VCC2 = 1.8V, VCC3 = 3V, Ta = 25°C) Conditions Min. Typ. Max. Unit Threshold voltage 1 Vs1 Threshold voltage at which connection of the prescribed load is detected from the open status 10 30 60 mV Threshold voltage 2 Vs2 Threshold voltage for switching to the short status from the prescribed load connected status 140 170 200 mV – 10 – CXA3355ER Electrical Characteristics Measurement Circuit RF_IN LNA_OUT LNA_IN VCC1 (LNA) 50Ω matching condition 100p 12n 2.7p 1p 18n 4.7n 3.9n 3p 3.3p 12p 33 32 31 30 29 28 27 26 25 24 23 GND (RF) GND (RF) RF_INP RF_INN GND VCC1 (LNA) LNA_OUT GND GND LNA_IN GND (LNA) 12p 10p VCC1 (RF) 34 VCC1 (RF) GND (LNA) 22 35 VCC1 (RF) GND (LNA) 21 0.1µ 36 TESTINP VCO_I 20 37 TESTINN C_VCO 19 TESTIN 0.1µ Buffer 38 TESTOUTP GND 18 24k 100p TESTOUT 39 TESTOUTN Buffer 8p VCC1 (IF) 40 VCC1 (IF) 0.1µ VCC1 (PLL) LPF 17 VCC1 (PLL) 16 VCC1 (PLL) 10p 1n 41 GND (IF) GND (PLL) 15 42 R_EXT1 TCXO 14 43 ENABLE CLK_OUT 13 10n VCC3 (ANT) 4 5 CLK GND (ANT) 3 DATA AILIM 2 GND (IF) DIAG 1 44 R_EXT2 VCC2 (IF) ASENS 39k DATA_OUT VCC2 (IF) C_EXT 33k 6 7 8 9 10 11 TCXO input level: 0.2 to 1.2Vp-p CLK_OUT LT 12 18n ENABLE pin VCC2 (IF): Active mode GND: Power save mode Bus Control DATA_OUT DIAG 1n VCC2 (IF) ANT ∗ The RF block bypass capacitors should have excellent high frequency characteristics. ∗ Use parts with a tolerance of ±1% for the following resistor elements. Other parts should have a tolerance of ±5%. • Pin 17 (LPF) • Pin 42 (R_EXT1) • Pin 44 (R_EXT2) – 11 – CXA3355ER Measurement Methods Note: The measurement methods in 4fo mode (TCXO = 16.368MHz, IF = 4.092MHz) are described below. 1) Total Gain Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ Total Gain: Output level [dBm] – SG input level to LNA_IN [dBm] Microwave coaxial cable Evaluation Board OPEN Signal Generator freq. = 1575.42MHz 50Ω AMP. = –120dBm LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) TCXO VCC2 (IF) IC VCC3 (ANT) TESTOUTP TESTOUTN External ENABLE Microwave coaxial cable Signal Generator 50Ω freq. = 16.368MHz AMP. = 0dBm buffer GND TESTOUT VCC = 1.8V Microwave coaxial cable ∗ All GND pins Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz 2) LNA NF Input: LNA_IN Output: LNA_OUT ∗ Compensate for the evaluation board and coaxial cable loss, and measure the NF value at the IC end. [Sony recommended measuring instruments] Noise source: Agilent 346A NF meter: Agilent N8973A Microwave coaxial cable NF meter freq. = 1575.42MHz BW = 2MHz Microwave coaxial cable LNA_OUT Noise Source Evaluation Board OPEN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) VCC2 (IF) VCC3 (ANT) LNA_IN IC TCXO Microwave coaxial cable Signal Generator 50Ω ENABLE GND VCC = 1.8V ∗ All GND pins – 12 – freq. = 16.368MHz AMP. = 0dBm CXA3355ER 3) Total NF Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "3" (IF filter output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ Total NF: Calculate NF from the noise power ratio when the DC 28V applied to the noise source is switched on and off. Use the 346A made by Agilent as the noise source for measurement. Noise Source Evaluation Board OPEN NF calculation formula DC 28V ON/OFF LNA_IN Y= VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50Ω AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE buffer GND TESTOUT VCC = 1.8V Microwave coaxial cable ∗ All GND pins Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz NON NOFF NF = 10 log ENR Y–1 ( ) NON: Noise power when the DC 28V is on. NOFF: Noise power when the DC 28V is off. ENR: Excess Noise Ratio 4) P-1dB Input Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ P-1dB Input: Input level [dBm] at the point when the response drops by 1dB from the desired signal straight line extension. Signal Generator freq. = 1575.42MHz 50Ω AMP. = –120 to –90dBm Microwave coaxial cable Evaluation Board OPEN LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50Ω AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE buffer GND TESTOUT VCC = 1.8V ∗ All GND pins Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz Microwave coaxial cable – 13 – CXA3355ER 5) Image Rejection Ratio Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "2" (Adder output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ IMRR (detuning frequency ≈ 4MHz): Image wave output level (at 1575.42MHz input) [dBm] – Desired wave output level (at 1567.236MHz input) [dBm] Signal Generator freq. = 1575.42MHz (Desired wave) 1567.236MHz (Image wave) 50Ω AMP. = –75dBm Microwave coaxial cable Evaluation Board OPEN LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50Ω AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE buffer GND TESTOUT VCC = 1.8V Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz Microwave coaxial cable ∗ All GND pins 6) Filter Response Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "3" (IF filter output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ Filter Response: Vary the input frequency to LNA_IN and measure the output level. Normalize fo (4fo) to the reference (0dB). Microwave coaxial cable Evaluation Board OPEN Signal Generator freq. = 1571.388MHz to 1675.42MHz 50Ω AMP. = –75dBm LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50Ω AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE buffer GND TESTOUT VCC = 1.8V ∗ All GND pins Spectrum Analyzer Center freq. = 150kHz to 100MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz Microwave coaxial cable – 14 – CXA3355ER 7) C/N Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "1I" (Ich mixer output block) ... See page 19. Monitor method: (1) Perform differential – single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. ∗ C/N: Carrier + 100kHz noise level – Carrier level [dBc/Hz] Microwave coaxial cable Evaluation Board OPEN Signal Generator freq. = 1575.42MHz 50Ω AMP. = –60dBm LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50Ω AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE buffer GND TESTOUT VCC = 1.8V Spectrum Analyzer Center freq. Microwave coaxial cable (Carrier) = 4.092MHz (Noise) = 4.192MHz 50Ω SPAN = 10kHz RBW = 100Hz VBW = 100Hz ∗ All GND pins 8) Spurious Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 19. Measure the spurious components separated by a certain frequency from the carrier. ∗ Spurious: Each spurious output level – Carrier level [dBc] Microwave coaxial cable Evaluation Board OPEN Signal Generator freq. = 1575.52MHz 50Ω AMP. = –120dBm LNA_IN VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) TCXO VCC2 (IF) IC VCC3 (ANT) TESTOUTP TESTOUTN External ENABLE Microwave coaxial cable Signal Generator 50Ω freq. = 16.368MHz AMP. = 0dBm buffer GND TESTOUT VCC = 1.8V ∗ All GND pins Microwave coaxial cable – 15 – Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50Ω RBW = 100Hz VBW = 100Hz CXA3355ER 9) Antenna Sense • Vary VS and measure the DIAG pin voltage. • Vary VS and measure the inflow current Ib to AILIM. Evaluation Board VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) VCC2 (IF) VCC3 (ANT) AILIM IC A DIAG V ASENS Vs ENABLE GND ∗ All GND pins VCC = 1.8V VCC3 = 3.0V – 16 – CXA3355ER Initial Settings The CXA3355ER is initialized by setting the ENABLE signal (Pin 43) from low level to high level. The timing, etc. should satisfy the conditions below. In addition, the TCXO frequency and IF frequency combinations in the table below can be obtained by setting Pin 10 (DATA), Pin 11 (CLK) and Pin 12 (LT) as shown in the table and then performing initialization. This eliminates the need for serial data setting. Pin 10 (DATA) Pin 11 (CLK) Pin 12 (LT) TCXO frequency [MHz] IF frequency [MHz] GND GND GND 16.368 4.092 Vcc2 GND GND 18.414 1.023 Vcc2 Vcc2 GND 13 0.976 1. During Power-on Power supply, ENABLE VCC 0.9 × VCC 0.1 × VCC GND 100ms or less The CXA3355ER is initialized by simultaneously raising the power supplies and the ENABLE signal (Pin 43) during power-on. The power supply and ENABLE signal (Pin 43) rise time should be 100ms or less. In addition, the power supplies (VCC1, VCC2) should rise simultaneously. The antenna sense circuit power supply (VCC3) should be left open except when using the antenna sense function. 2. Initialization After Power-on Power supply VCC GND ENABLE VCC 0.5 × VCC 10ms or more GND After power-on, the CXA3355ER is initialized by setting the ENABLE signal (Pin 43) to low level for 10ms or more and then setting it to high level. – 17 – CXA3355ER Serial Data Settings The CXA3355ER can make the PLL counter settings, perform TCXO_CLK output, select the internal IF filter, and use the test I/O circuit according to the serial data settings (3-wire bus control). The transfer bit length is 18 bits, and there are four addresses. The address is set by the A1 and A0 bits. The timing, etc. should satisfy the conditions below. Serial Data Format MSB LSB A1 A0 D15 D14 D13 D12 D11 D10 0 0 MC10 MC9 MC8 MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 0 1 SC4 SC3 SC2 SC1 SC0 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 1 0 TI2 TI1 TI0 1 1 0 0 0 TO2 TO1 TO0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 CLK 0 0 TCL 0 0 0 0 0 0 0 0 FIL 0 0 0 0 0 0 0 0 0 0 0 MC (0 to 10): Main counter frequency division value setting 0: Logic input voltage low level SC (0 to 4): Swallow counter frequency division value setting 1: Logic input voltage high level RC (0 to 8): Reference counter CLK: TCXO CLK output (0: Not output, 1: Output) FIL: Internal filter selection (0: fo mode LPF, 1: 4fo mode BPF) TCL: IF block test I/O control (0: When not using the test I/O circuit, 1: When using the test I/O circuit) TI (0 to 2): IF block test input location setting TO (0 to 2): IF block test output location setting 18-bit Data Format Invalid data Address data Invalid data Each data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 DATA CLK LT Time Latch ∗ Input data to all four addresses. Serial Data Interface Bus Timing (3-wire Bus Control) tSD tHD DATA CLK tLOW tSD = Data setup time tHD = Data hold time tLOW = Low period of CLK tHIGH = High period of CLK tSL = LT setup time tWHLT = High pulse width (LT) tHIGH tHL LT tWHLT ≥ 100ns tSD, tHD, tLOW, tHIGH, tHL, tWHLT ≥ 50ns – 18 – tWHLT CXA3355ER Description of Functions 1. Test Circuit The CXA3355ER has a test circuit for test signal I/O. The test circuit is connected between each IF block, and test I/O control can be performed by the serial data settings. The test circuit location, configuration and the serial data settings are as follows. 33 To each IF block 32 31 34 30 1540fo = 1575.42MHz RF_AMP 35 Test input control Mixer Mixer "1Q" "1I" 36 36 37 37 90˚ IF_AMP1 IF_AMP1 38 Local 38 39 Test output control 39 "1I": Ich mixer output block (Ich IF AMP1 input block) "1Q": Qch mixer output block (Qch IF AMP1 input block) "2": Adder output block (IF filter input block) "3": IF filter output block (IF AMP2 input block) "4": IF AMP2 output block (A/D converter input block) IF Phase Shifter 40 41 From each IF block "2" 42 ∗ Actual operation is differential, but only one side is shown. ∗ The inter-circuit connections are cut off during test input selection and test output selection. 43 IF_AMP2 LPF 44 HPF BIAS 1 "3" "4" A/D Converter ANT SENSE 2 3 4 5 6 7 Test Circuit Location and Configuration Serial Data Settings for Test Input Selection Test input block Serial Data Settings for Test Output Selection TI2 TI1 TI0 TO2 TO1 TO0 Test output block 0 0 0 Normal operation 0 0 0 Normal operation 0 0 1 Ich IF AMP1 input block 0 0 1 Ich mixer output block 0 1 0 Qch IF AMP1 input block 0 1 0 Qch mixer output block 0 1 1 Not used. 0 1 1 Not used. 1 0 0 Not used. 1 0 0 Not used. 1 0 1 IF filter input block 1 0 1 Adder output block 1 1 0 IF AMP2 input block 1 1 0 IF filter output block 1 1 1 A/D converter input block 1 1 1 IF AMP2 output block 0: Logic input voltage low level 1: Logic input voltage high level ∗ Set the TCL register to "1" when using or to "0" when not using the test input circuit or the test output circuit. (See page 18.) – 19 – CXA3355ER 2. Using an External Filter When using the CXA3355ER in 4fo mode with the initial settings (see page 17) which do not require serial data setting, input and output are performed via the test circuit located between the internal IF filter and the IF AMP2 in the following stage, so an external filter is necessary. The external filter uses Pins 36 to 39. Differential I/O is performed with Pin 38 (TESTOUTP) and Pin 39 (TESTOUTN) as the internal IF filter output pins and Pin 36 (TESTINP) and Pin 37 (TESTINN) as the input pins to IF AMP2. Also, the impedance is 200Ω (differential) for both input and output. Note that the bias voltage is determined inside the IC, so Pins 36 and 37 should not be connected directly with Pins 38 and 39. When not using an external filter, eliminate the DC components using an approximately 10nF capacitor. The overall external filter block and the external filter configuration are shown below. Secondary LPF Secondary HPF External filter I/O circuit IF AMP2 To the comparator LPF HPF CXA3355ER 39 Pin 36: TESTINP Pin 37: TESTINN Pin 38: TESTOUTP Pin 39: TESTOUTN 38 37 36 Zout ≈ 200Ω Zin ≈ 200Ω External filter Overall External Filter Block L1 L3 C2 C5 Pin 38 C8 C12 C10 C4 C7 C11 Pin 39 10 Pin 36 0 C6 C3 C9 C13 –10 L4 L2 Chip C L5, L6 (2 series) [pF] Chip L Response [dB] C1 CXA3355ER IF Filter Response (Example of representative characteristics) Normalized at 4MHz Pin 37 [µH] –20 –30 C1 91 L1, L2 2.2 C2, C3 300 L3, L4 3.9 C4 240 L5, L6 4.7 C5, C6 91 –60 C7 130 –70 C8, C9, C12, C13 680 C10, C11 1500 –40 –50 Internal filter Internal filter + External filter 0 1 2 3 4 5 6 7 Detuning frequency [MHz] External Filter Configuration – 20 – 8 9 10 CXA3355ER Description of Operation Overview of Operation This IC down-converts the GPS (Global Positioning System) frequency of 1.57542GHz to fo (fo: 1.023MHz) or 4fo (4fo: 4.092MHz). The internal configuration is divided into the analog block, consisting of the amplifier, mixer and filters, and the digital block (including the comparator block and the control block), which forms the PLL. The analog block converts the frequency and amplifies the signal with the amplifier and the mixer, and eliminates undesired components with the filters. The digital block can switch the PLL frequency division ratio in order to down convert the output signal to fo or 4fo. 1. LNA The GPS signal that passes through the antenna is input to Pin 24 via a matching circuit as shown in the figure below. The input signal is amplified by the LNA, and then output from Pin 27. Always use matching circuits for the LNA input pin (Pin 24) and the LNA output pin (Pin 27), and match at 1.57542GHz. 2. RF Amplifier, RF Mixer, IF Phase Shifter and Adder The signal amplified by the LNA passes through the SAW filter, and is then input to Pin 30 via a matching circuit. The input signal is amplified by the RF amplifier, and then down-converted by the RF mixer to the fo (1.023MHz) or 4fo (4.092MHz) I and Q components. The IF signal down-converted to the I and Q components has the image component eliminated by the phase shifter and the adder, and is then input to the IF filter. Always use a matching circuit for the RF amplifier input pin (Pin 30), and match at 1.57542GHz. Matching Circuit 24 Matching Circuit 27 LNA fo or 4fo SAW Matching Circuit 30 1540fo Phase Shifter 31 0˚ 90˚ 90˚ – 21 – To the IF filter Adder fo: 1.023MHz CXA3355ER 3. IF Filter The IF signal that passed through the adder has the undesired components outside the band eliminated by the IF filter. In fo mode the signal passes through only the LPF and is input to IF AMP2. In 4fo mode the signal passes through the LPF and then the HPF and is input to IF AMP2. Note that fo mode and 4fo mode can be switched by the serial data setting. Set the serial data setting register FIL to "0" for fo mode (LPF) or to "1" for 4fo mode (BPF). In addition, an external filter can also be connected to this IC using Pins 36 to 39. (See page 20.) From the adder To IF AMP2 LPF HPF 4. IF AMP2 and A/D Converter The signal that passed through the IF filter is amplified by IF AMP2, converted to a binary signal by the A/D converter, and then output from the DATA output pin (Pin 7). The A/D converter performs sampling at the TCXO CLK. In addition, the A/D converter output voltage high level is VCC2 (1.6 to 3.3V), so a wide range of interfaces can be supported. 5. TCXO (Pin 14) Input the signal from the external oscillator to Pin 14 via a capacitor as the reference signal. Input frequencies from 10MHz to 26MHz are supported. The input signal level from the external oscillator should be 1.2Vp-p or less (0.6Vp-p typ., 0.2Vp-p min.). This is also the same in power save mode. However, using the typical level of 0.6Vp-p is recommended from the viewpoint of reducing harmful waves to the receive block, etc. 6. TCXO CLK Output (Pin 13) This IC can output TCXO CLK from Pin 13 according to the serial data setting. The output voltage high level is VCC2 (1.6 to 3.3V), so a wide range of interfaces can be supported. Set the serial data setting register CLK to "0" when not using TCXO CLK, or to "1" when using TCXO CLK. (See page 18.) – 22 – CXA3355ER 7. PLL/VCO The PLL is comprised by a VCO, frequency divider and phase/frequency comparator as shown in the figure below, and incorporates an inductor, varactor and all other necessary components. The loop filter is externally connected. Use components that satisfy the required characteristics. Serial data setting is unnecessary when this IC is used with the typical TCXO and IF combinations set by the initial settings shown in page 17. When making serial data settings, set counter frequency division values that satisfy the following equations. • fVCO = (M × N + A) × (fTCXO × 2) ÷ R • (fTCXO × 2) ÷ R > 800kHz • N ≥ 3, R ≥ 3 fVCO: VCO oscillation frequency, fTCXO: TCXO frequency MC data = N, SC data = A, RC data = R, DMPS data = M = 24 (fixed) To the RF phase shifter DMPS MC 1/M, 1/(M + 1) 1/N Frequency division ratio (M × N) + A VCO Loop filter ∗ M = 24 SC PFD CP 1/A ×2 RC 1/R 14 TCXO (10MHz to 26MHz) 8. ENABLE (Pin 43) Active mode and power save mode can be switched according to the level. • High (V_IH: 1.2V min.): Active mode • Low (V_IL: 0.2V max.): Power save mode – 23 – 17 VCC1 CXA3355ER 9. Antenna Sense The power supply lines are separated internally, so antenna sense operation at the supply voltage (VCC3) of 3.0 ± 0.3V is recommended. Note that the antenna sense function does not operate independently, so voltage should also be applied to the other power supply pins (VCC1, VCC2) for use in active mode. In addition, leave the power supply pin (VCC3) open when not using the antenna sense function. The antenna sense function checks whether an antenna is connected. Pin 2 (DIAG) outputs high voltage when an antenna is not connected, or low voltage when an antenna is connected. A current limiting circuit is provided as a countermeasure against short circuits. The DIAG pin voltage switching point is as shown in the table below. MODE Connection status DIAG voltage Vs < V1 Open High V1 < Vs < V2 Normal connection Low V2 < Vs Short High DIAG [V] V1, V2, V3 and Ib in the table below are as follows. V1: 10 to 60mV → Threshold voltage at which connection of the prescribed load is detected from the open status V2: 140 to 200mV → Threshold voltage for switching to the short status from the prescribed load connected status. V3: 250mV → Current limiting threshold voltage. Ib: 1.7 to 2.1mA → Base current in the normal connection status. V1 R3 VCC3 (ANT) Vs CXA3355ER V1 ASENS 1 A1 2 3 DIAG AILIM V2 VA A2 V3 Ib A3 VD Antenna Sense Block Circuit – 24 – Vs I1 = 1.9mA I1 (Typ.) Ib [mA] VCC3 (ANT) V2 V3 Vs CXA3355ER Application Circuit VCC1 VCC1 VCC1 VCC1 VCC2 (LNA) (RF) (IF) (PLL) (IF) SAW Filter VCC1 (LNA) 0.1µ 100p 2.7p 1p 18n 12n 4.7n 3.9n 3p 1µ 3.3p VCC = 1.8V 12p 33 32 31 30 29 28 27 26 25 24 23 GND (RF) GND (RF) RF_INP RF_INN GND VCC1 (LNA) LNA_OUT GND GND LNA_IN GND (LNA) 12p 10p VCC1 (RF) 34 VCC1 (RF) GND (LNA) 22 35 VCC1 (RF) GND (LNA) 21 0.1µ 36 TESTINP VCO_I 20 37 TESTINN C_VCO 19 0.1µ 10n 10n 38 TESTOUTP GND 18 24k 100p 39 TESTOUTN VCC1 (PLL) LPF 17 8p VCC1 (IF) 40 VCC1 (IF) VCC1 (PLL) 16 VCC1 (PLL) 10p 1n 41 GND (IF) GND (PLL) 15 42 R_EXT1 TCXO 14 43 ENABLE CLK_OUT 13 10n VCC3 (ANT) 4 5 CLK GND (ANT) 3 DATA AILIM 2 GND (IF) DIAG 1 44 R_EXT2 VCC2 (IF) ASENS 39k DATA_OUT VCC2 (IF) C_EXT 33k 6 7 8 9 10 11 TCXO input level: 0.2 to 1.2Vp-p LT 12 18n ENABLE pin Vcc2 (IF): Active mode GND: Power save mode DATA_OUT 1n VCC2 (IF) Number of parts • Resistors: 3pcs • Capacitors: 20pcs • Inductors: 5pcs • SAW filter: 1pcs (Excluding the antenna sense circuit) ∗ This diagram shows the application circuit when the initial settings are made for 4fo mode. (See page 17.) ∗ The RF block bypass capacitors should have excellent high frequency characteristics. ∗ Use parts with a tolerance of ±1% for the following resistor elements. Other parts should have a tolerance of ±5%. • Pin 17 (LPF) • Pin 42 (R_EXT1) • Pin 44 (R_EXT2) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 25 – CXA3355ER Supplement Materials (Example of representative characteristics) Graph 1. ICC Graph 2. Total Gain 10 20 IF AMP2 output level [dBm] 5 Icc [mA] 15 10 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C 0 –5 –10 –15 –20 –25 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C –30 fo 4fo –35 –40 –135 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85 5 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 Vcc [V] LNA_IN input level [dBm] Graph 3. Total NF Graph 4. Image Rejection Ratio 10 –20 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C –25 8 –30 IMRR [dBc] Total NF [dB] –35 6 fo mode 4fo mode 4 –40 –45 –50 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C 2 –55 –60 0 0 1 2 3 4 –65 0.1 5 1 10 IF frequency [MHz] Detuning frequency [MHz] Graph 5. Filter Response (Normalized at 1.023MHz) Graph 6. Filter Response (Normalized at 4.092MHz) 10 10 fo Upper spec (fo) Lower spec (fo) Filter response [dB] 0 –5 –10 –15 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C –20 0 –5 –10 –15 –25 –30 –30 1 10 –35 0.1 100 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C –20 –25 –35 0.1 4fo Upper spec (4fo) Lower spec (4fo) 5 Filter response [dB] 5 1 10 Detuning frequency [MHz] Detuning frequency [MHz] – 26 – 100 CXA3355ER Graph 7. Local Leak Graph 8. C/N –40 –60 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25˚C –50 C/N [dBc/Hz] Local leak [dBm] –65 –70 –75 –60 –70 –80 –80 –90 –100 0.01 –85 Evaluation board LNA_IN pin 0.1 1 Frequency difference from the carrier [MHz] Graph 9a. Antenna Sense (VS vs. DIAG) Graph 9b. Antenna Sense (VS vs. Ib) 2.5 4.0 VCC1 = VCC2 = 1.8V VCC3 = 3V Temp = 25˚C 3.5 2.0 3.0 1.5 VCC1 = VCC2 = 1.8V VCC3 = 3V Temp = 25˚C 2.0 1.5 1.0 Ib [mA] DIAG [V] 2.5 DIAG Upper Spec Lower Spec 0.5 Ib 1.0 0.5 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0 Vs [V] 0.1 0.2 0.3 Vs [V] – 27 – 0.4 0.5 0.6 CXA3355ER Package Outline Unit: mm 44PIN VQFN (PLASTIC) 0.8 ± 0.1 5.1 2.0 33 0. 22 4-φ0.8 23 34 C 22 0.4 ± 0.1 2.0 44 0.55 ± 0.1 B A 12 1 11 PIN 1 INDEX 0.4 0.05 M S A-B C X4 0.1 S A-B C MAX0.02 S 0.4 Solder Plating + 0.09 0.14 – 0.03 0.135 0.175 + 0.09 0.31 – 0.03 S 0.05 S TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.06g SONY CODE VQFN-44P-02 LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm – 28 – Sony Corporation