SONY CXD2951GA-2

CXD2951GA-2
Single Chip GPS LSI
Description
The CXD2951GA-2 is a dedicated single chip LSI
for the GPS (Global Positioning System), satellitebased location measurement system. This LSI
enables the configuration of a single chip system
providing a cost-effective, low-power solution.
Compared with conventional methods, position
detection time and sensitivity are substantially
improved with the use of an advanced signal
processing scheme. With the integration of both the
Radio and baseband blocks into a single CMOS IC,
the CXD2951GA-2 is ideal for use in automotive,
cellular handset, handheld navigation, mobile
computing and other location-based applications.
Features
• 12-channel GPS receiver capable of simultaneously
receiving 12 satellites
• Reception frequency: 1575.42MHz
(L1 band, CA code)
• Reference clock (TCXO) frequency:
18.414MHz (GPS, Sony standard),
The unique frequency of major applications is available,
such as GSM and W-CDMA. (optional)
13.000MHz (GSM),
14.400MHz (CDMA),
16.368MHz (GPS),
19.800MHz (PDC/CDMA),
26.000MHz (GSM)
• 32 bits RISC CPU (ARM7TDMI)
• 288K-bytes Program ROM
• 72K-bytes Data RAM
Power is supplied only to 8K-byte Data RAM while
in backup mode.
• System power management
• 1-channel UART
• Internal RTC (Real Time Clock)
• 10-bit successive approximation system A/D
converter, A/D data available on NMEA messages
• All-in-view positioning
• Communication format: Supports NMEA-0183
• 1 PPS output
• Supports assisted-GPS for cellular (optional)
176 pin LFLGA (Plastic)
Radio
• Image Rejection Mixer
• VCO Tank
• IF Filters
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage I/O
IOVDD
• Supply voltage core
CVDD
• Supply voltage radio VDD
• Input voltage
VI
• Output voltage
VO
• Operating temperature Topr
• Storage temperature Tstg
–0.5 to +4.6
–0.5 to +2.5
–0.5 to +2.5
–0.5 to +6
–0.5 to +6
–40 to +85
–50 to +150
V
V
V
V
V
°C
°C
Recommended Operating Conditions
• Supply voltage I/O
IOVDD
3.0 to 3.6
V
∗ Under operation with internal ROM, using no
external expansion bus:
IOVDD
2.6 to 3.6
V
∗ Under operation in backup mode:
BKUPIOVDD 2.5 (Min.) V
• Supply voltage core
CVDD
1.62 to 1.98
V
• Supply voltage radio VDD
1.62 to 1.98
V
• Operating temperature Topr
–40 to +85
°C
Input/Output Pin Capacitance (Baseband)
• Input capacitance
CIN
9 (Max.)
• Output capacitance
COUT
11 (Max.)
• I/O capacitance
CI/O
11 (Max.)
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04445A49
CXD2951GA-2
Performance
Baseband
• Tracking sensitivity:
–152dBm (average) or less
• Acquisition sensitivity: –139dBm (average) or less in Normal mode
–150dBm (average) or less in High sensitivity mode
∗ Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier
with NF ≤ 2dB, 25dB gain.
• TTFF (Time to First Fix):
Time until initial position measurement after power-on with the following conditions:
Cold Start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility)
Warm Start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility)
Hot Start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility)
∗ Reference data with elevation angle of 5° or more and no interception environment with satellite powers
≥ –130dBm. (Not in High sensitivity mode)
Note) "95% possibility" means "position time with 95% possibility".
• Positioning accuracy:
2DRMS: approx. 5m
∗ Reference data with elevation angle of 5° or more and no interception environment with satellite powers
≥ –130dBm.
• Measurement data update time: 1s
• Power consumption:
50mW (average) while position calculating with tracking satellites in low power mode
120mW (average) while position calculating with acquiring and tracking satellites
∗ Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its
amplitude is 3.3V swing.
• 1PPS output
1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97).
Note) These values are not guaranteed, depending on the conditions.
Radio
• Total Gain (typ.):
100dB
• Noise figure (typ.):
8dB
• Synthesizer phase noise (typ.):
–70dBc/Hz (10kHz)
–80dBc/Hz (100kHz)
• PLL spurious (typ.):
–45dBc (inside fosc ±1.023MHz)
–55dBc (outside fosc ±1.023MHz)
Note) These values are not guaranteed.
–2–
CXD2951GA-2
System Block Diagram
1575.42MHz
TCXO
LNA
Freq.
Synthesizer
CPU
Down
Converter
BPF
SAW
RF/IF
1575.42MHz → 1.023MHz
LPF
LNA
1 bit
1.023MHz
TCXO
Reference clock
18.414MHz
(GPS, Sony standard)
Acquisition Block
• Acquire GPS signals
Tracking Block
• Locking to GPS signals
• 12ch correlations
Costas Loop & DLL
I/O
UART
A/D
ARM7TDMI
Computation
& Control
• Control Acquisition
& Tracking block
• Position calculating
RTC
X'tal
32.768kHz
–3–
Timer
3ch
RAM
72KB
ROM
288KB
CXD2951GA-2
Pin Configuration (Top View)
18
V
U
T
R
P
N
17
16
15
14
13
12
11
10
9
8
87
85
81
79
76
75
71
67
64
62
EA3
EA5
CVSS3
EA9
IOVDD2
IOVSS2
EA15
EA19
ETEST0
CVSS2
7
6
59
57
IF2GND IF1GND
90
88
86
83
80
77
73
70
68
63
60
56
EA0
EA2
EA4
EA7
EA8
EA11
EA13
EA16
EA18
CVDD2
VCOM
IF1VCC
66
65
92
89
84
82
78
74
72
69
CVDD4
EA1
EA6
CVDD3
EA10
EA12
EA14
EA17
93
91
96
ECLKI
CVSS4
IOVDD3
ETEST2 ETEST1
61
RREF
58
54
5
53
TEST
OUTP
48
4
3
50
49
MIXGND LNASRC
46
45
52
55
51
H
40
37
C
38
98
33
35
36
VDDCP
LPFRF
VSSCP
102
97
100
31
32
104
99
106
101
110
108
VDDPLL VSSPLL
103
27
105
109
111
IOVSS8
ETEST4
115
114
113
116
117
118
121
120
123
29
25
23
ETESTTDO
20
TRST
13
11
125
124
127
EXWE3
128
131
130
132
EXWE0 IOVDD4
A
18
34
P
N
LPFIF
30
M
24
21
26
L
TCK
22
K
19
18
CVDD1
CVSS1
15
17
J
H
IOVDD1 EXTCXO
12
16
G
9
14
F
EPORT10 EPORT8 IOVSS1
7
EXCS1
EXCS0
R
EPORT12 EPORT11 ETCXO
122
126
T
ETESTTDI ETESTTINT TDO
119
EXOE
28
ETESTTMS TDI
107
112
U
ETESTTCK TMS RADIOSUB
EVIN2
IOVDD7
EXWE2 IOVSS5
B
39
EXROMI
ECLKS0 IOVSS4
D
41
95
BKUPIOVDD ECLKS1 ECLKS2
E
43
IOVSS3
ECCKO BKUPIOVSS EOSCEN
F
42
94
ECCKI BKUPCVDD BKUPCVSS
G
44
VDDVCO VCODE VSSVCO
CAP
ETEST3 EAVDAD EADVRT
J
V
ECLKO
EVIN3 EAVSAD
K
47
RFIN
IF2VCC TESTINN TEST TESTINP RFSUB RFRREF LNAMAT
OUTD
EVIN1 EAVSPLL EVIN0
L
1
TEST MIXGND MIXGND LNASRC MIXGND NRING
OUTN
EADVRB ECLKOUT EAVDPLL
M
2
EPORT6
5
EPORT4
129
137
139
143
145
147
155
158
161
165
167
169
EXWE1
ED27
ED25
ED21
ED19
ED17
ED15
ED12
ED9
ED5
ED3
ED1
173
1
133
135
138
141
146
149
150
154
157
159
163
164
171
175
ED29
ED26
ED23
ED18
CVSS5
CVDD5
IOVDD5
ED13
ED11
ED7
ED6
CVSS6
IOVSS7
151
152
153
156
134
136
140
142
144
148
ED28
ED24
ED22
ED20
ED16
17
16
15
14
13
12
EXRS ETESTXRS IOVSS6 ED14
11
10
9
8
10
3
8
D
EPORT2 EPORT7
176
4
C
174
2
B
ETXD0 EPORT1
160
162
166
168
170
172
ED10
ED8
ED4
ED2
ED0
CVDD6
7
6
5
4
3
2
A
1
: Pin 1 index.
–4–
E
ERXD0 EPORT0 IOVDD6 EPORT3
ED31
ED30
6
EPORT5 EPORT9
CXD2951GA-2
Pin Description
Pin
No.
Symbol
I/O
Description
1
EPORT0
I/O/Z
I/O port 0
(with a software controllable pull-down resistor, Connected to GND with a resistor.)
2
EPORT1
I/O/Z
I/O port 1
(with a software controllable pull-down resistor, See software application note.)
3
EPORT2
I/O/Z
I/O port 2
(with a software controllable pull-down resistor, See software application note.)
4
EPORT3
I/O/Z
I/O port 3
(with a software controllable pull-down resistor, See software application note.)
5
EPORT4
I/O/Z
I/O port 4
(with a software controllable pull-down resistor, See software application note.)
6
EPORT5
I/O/Z
I/O port 5
(with a software controllable pull-down resistor, See software application note.)
7
EPORT6
I/O/Z
I/O port 6
(with a software controllable pull-down resistor, See software application note.)
8
EPORT7
I/O/Z
I/O port 7
(with a software controllable pull-down resistor, See software application note.)
9
EPORT8
I/O/Z
I/O port 8
(with a software controllable pull-down resistor, See software application note.)
10
EPORT9
I/O/Z
I/O port 9
(with a software controllable pull-down resistor, See software application note.)
11
EPORT10
I/O/Z
I/O port 10
(with a software controllable pull-down resistor, See software application note.)
12
EPORT11
I/O/Z
I/O port 11
(with a software controllable pull-down resistor, See software application note.)
13
EPORT12
I/O/Z
I/O port 12
(with a software controllable pull-down resistor, See software application note.)
14
IOVSS1
GND
15
IOVDD1
3.3V
16
ETCXO
I
17
EXTCXO
O
18
CVSS1
GND
19
CVDD1
1.8V
20
TRST
I
Test (Open, with a pull-down resistor)
21
ETESTTINT
O
Test
22
TDO
O
Test
23
ETESTTDO
O
Test
24
TDI
I
Test (Open, with a pull-up resistor)
25
ETESTTDI
I
Test (Open, with a pull-up resistor)
26
TCK
I
Test (Open, with a pull-down resistor)
27
ETESTTCK
I
Test (Open, with a pull-down resistor)
28
TMS
I
Test (Open, with a pull-up resistor)
TCXO oscillator (Frequency selectable, See software application note.)
–5–
CXD2951GA-2
Pin
No.
Symbol
I/O
29
ETESTTMS
30
RADIOSUB
I
∗
31
VDDPLL
∗
PLL 1.8V
32
VSSPLL
∗
PLL GND
33
VDDCP
∗
Charge pump 1.8V
LPFIF
∗
Loop filter for IF PLL
35
LPFRF
∗
Loop filter for RF PLL
36
VSSCP
∗
Charge pump GND
VDDVCO
∗
VCO 1.8V
VSSVCO
∗
VCO GND
39
VCODECAP
∗
VCO decap pin
40
RFSUB
∗
RF GND
LNAMAT
∗
LNA 1.8V
42
NRING
∗
LNA 1.8V
43
RFRREF
∗
External resistor pin
44
MIXGND
∗
Mixer GND
LNASRC
∗
LNA GND
46
MIXGND
∗
Mixer GND
47
RFIN
∗
RF input
MIXGND
∗
Mixer GND
49
LNASRC
∗
LNA GND
50
MIXGND
∗
Mixer GND
51
TESTINP
∗
Radio test (Open)
TESTINN
∗
Radio test (Open)
53
TESTOUTP
∗
Radio test
54
TESTOUTN
∗
Radio test
55
TESTOUTD
∗
Radio test (Open)
IF1VCC
∗
1st IF 1.8V
57
IF1GND
∗
1st IF GND
58
IF2VCC
∗
2nd IF 1.8V
IF2GND
∗
2nd IF GND
60
VCOM
∗
IF common voltage
61
RREF
∗
External resistor pin
62
CVSS2
GND
63
CVDD2
1.8V
34
37
38
41
45
48
52
56
59
Description
Test (Open, with a pull-up resistor)
Radio GND
∗ Radio analog pins: See page 10 to 12 for details.
–6–
CXD2951GA-2
Pin
No.
Symbol
I/O
Description
64
ETEST0
I
65
ETSET1
I
66
ETEST2
I
67
EA19
O/Z
External expansion address 19
68
EA18
O/Z
External expansion address 18
69
EA17
O/Z
External expansion address 17
70
EA16
O/Z
External expansion address 16
71
EA15
O/Z
External expansion address 15
72
EA14
O/Z
External expansion address 14
73
EA13
O/Z
External expansion address 13
74
EA12
O/Z
External expansion address 12
75
IOVSS2
GND
76
IOVDD2
3.3V
77
EA11
O/Z
External expansion address 11
78
EA10
O/Z
External expansion address 10
79
EA9
O/Z
External expansion address 9
80
EA8
O/Z
External expansion address 8
81
CVSS3
GND
82
CVDD3
1.8V
83
EA7
O/Z
External expansion address 7
84
EA6
O/Z
External expansion address 6
85
EA5
O/Z
External expansion address 5
86
EA4
O/Z
External expansion address 4
87
EA3
O/Z
External expansion address 3
88
EA2
O/Z
External expansion address 2
89
EA1
O/Z
External expansion address 1
90
EA0
O/Z
External expansion address 0
91
CVSS4
GND
92
CVDD4
1.8V
93
ECLKI
I
94
ECLKO
O
95
IOVSS3
GND
96
IOVDD3
3.3V
97
ECLKOUT
98
EXROMI
99
EAVSPLL
PLL GND
100
EAVDPLL
PLL 3.3V
O/Z
I
Test (Connect to GND.)
CPU clock oscillator
1PPS output (Effective 1s late after reset release)
Boot selection (Low: Internal ROM, High: External Memory/EXCS0)
–7–
CXD2951GA-2
Pin
No.
Symbol
101
EAVSAD
102
EADVRB
I
A/D converter Reference input Bottom
103
EVIN0
I
A/D converter Analog input 0
104
EVIN1
I
A/D converter Analog input 1
105
EVIN2
I
A/D converter Analog input 2
106
EVIN3
I
A/D converter Analog input 3
107
EADVRT
I
A/D converter Reference input Top
108
EAVDAD
A/D converter 3.3V
109
IOVSS8
GND
110
ETEST3
I/O/Z
(Connect to GND with a resistor.)
111
ETEST4
I/O/Z
(Connect to GND with a resistor.)
112
IOVDD7
3.3V
113
BKUPCVSS
Backup core power supply GND
114
BKUPCVDD
Backup core power supply 1.8V
115
ECCKI
I
116
ECCKO
O
117
BKUPIOVSS
Backup I/O power supply GND
118
BKUPIOVDD
Backup I/O power supply 3.3V
119
EOSCEN
I
Oscillator enable (H-Active), See backup mode section.
120
ECLKS0
I
Test (Connect to GND.)
121
ECLKS1
I
Test (Connect to GND.)
122
ECLKS2
I
Test (Connect to GND.)
123
IOVSS4
124
EXCS0
O/Z
External expansion chip selection 0 (Program boot is enable if EXROMI is high.)
125
EXCS1
O/Z
External expansion chip selection 1
126
EXOE
O/Z
External expansion read signal
127
EXWE3
O/Z
External expansion write signal
128
EXWE2
O/Z
External expansion write signal
129
EXWE1
O/Z
External expansion write signal
130
EXWE0
O/Z
External expansion write signal
131
IOVSS5
GND
132
IOVDD4
3.3V
133
ED31
I/O
External expansion data 31 (with a pull-down resistor)
134
ED30
I/O
External expansion data 30 (with a pull-down resistor)
135
ED29
I/O
External expansion data 29 (with a pull-down resistor)
136
ED28
I/O
External expansion data 28 (with a pull-down resistor)
137
ED27
I/O
External expansion data 27 (with a pull-down resistor)
138
ED26
I/O
External expansion data 26 (with a pull-down resistor)
I/O
Description
A/D converter GND
RTC oscillator (32.768kHz)
GND
–8–
CXD2951GA-2
Pin
No.
Symbol
I/O
Description
139
ED25
I/O
External expansion data 25 (with a pull-down resistor)
140
ED24
I/O
External expansion data 24 (with a pull-down resistor)
141
ED23
I/O
External expansion data 23 (with a pull-down resistor)
142
ED22
I/O
External expansion data 22 (with a pull-down resistor)
143
ED21
I/O
External expansion data 21 (with a pull-down resistor)
144
ED20
I/O
External expansion data 20 (with a pull-down resistor)
145
ED19
I/O
External expansion data 19 (with a pull-down resistor)
146
ED18
I/O
External expansion data 18 (with a pull-down resistor)
147
ED17
I/O
External expansion data 17 (with a pull-down resistor)
148
ED16
I/O
External expansion data 16 (with a pull-down resistor)
149
CVSS5
GND
150
CVDD5
1.8V
151
EXRS
I
Reset (L-Active)
152
ETESTXRS
I
Test (Open, with a pull-up resistor)
153
IOVSS6
GND
154
IOVDD5
3.3V
155
ED15
I/O
External expansion data 15 (with a pull-down resistor)
156
ED14
I/O
External expansion data 14 (with a pull-down resistor)
157
ED13
I/O
External expansion data 13 (with a pull-down resistor)
158
ED12
I/O
External expansion data 12 (with a pull-down resistor)
159
ED11
I/O
External expansion data 11 (with a pull-down resistor)
160
ED10
I/O
External expansion data 10 (with a pull-down resistor)
161
ED9
I/O
External expansion data 9 (with a pull-down resistor)
162
ED8
I/O
External expansion data 8 (with a pull-down resistor)
163
ED7
I/O
External expansion data 7 (with a pull-down resistor)
164
ED6
I/O
External expansion data 6 (with a pull-down resistor)
165
ED5
I/O
External expansion data 5 (with a pull-down resistor)
166
ED4
I/O
External expansion data 4 (with a pull-down resistor)
167
ED3
I/O
External expansion data 3 (with a pull-down resistor)
168
ED2
I/O
External expansion data 2 (with a pull-down resistor)
169
ED1
I/O
External expansion data 1 (with a pull-down resistor)
170
ED0
I/O
External expansion data 0 (with a pull-down resistor)
171
CVSS6
GND
172
CVDD6
1.8V
173
ERXD0
I
174
ETXD0
O/Z
175
IOVSS7
GND
176
IOVDD6
3.3V
UART (CH0) reception data (with a pull-down resistor during reset interval)
UART (CH0) transmission data (with Hi-Z during reset interval)
–9–
CXD2951GA-2
Radio Pin Description
Pin
No.
Symbol
Standard
pin voltage
[V]
30
RADIOSUB
0
31
VDDPLL
1.8
PLL 1.8V
32
VSSPLL
0
PLL GND
33
VDDCP
1.8
Radio GND
Charge pump 1.8V
VDDCP
34
LPFIF
0.8
IF2VCC
IF PLL loop filter
connection
34
1k
VSSCP
LPFRF
5k
IF2GND
VDDCP
35
Description
Equivalent circuit
VDDVCO
IF1VCC
RF PLL loop filter
connection
0.9
1k
35
1k
39
VCODECAP
39
0.65
1k
Capacitor connection
for decoupling the
VCO bias circuit
VSSVCO
VSSCP
36
VSSCP
0
Charge pump GND
37
VDDVCO
1.8
VCO 1.8V
38
VSSVCO
0
VCO GND
40
RFSUB
0
RF GND
42
NRING
1.8
LNA 1.8V
IF1VCC
43
RFRREF
External resistor
connection
(LNA, RF mixer bias)
0.1
43
250
IF1GND
– 10 –
CXD2951GA-2
Standard
pin voltage
[V]
Pin
No.
Symbol
44
MIXGND
0
Mixer GND
45
LNASRC
0
LNA GND
46
VDDCP
Equivalent circuit
Description
1.8
Charge pump 1.8V
41
IF1VCC
41
LNAMAT
1.8
LNA 1.8V
7k
47
47
RFIN
—
RF input
10k
LNASRC
48
MIXGND
0
Mixer GND
49
LNASRC
0
LNA GND
50
MIXGND
0
Mixer GND
IF1VCC
51
TESTINP
Radio test input pin
Normally leave open.
—
51
200
200
52
52
TESTINN
Radio test input pin
Normally leave open.
—
IF1GND
IF1VCC
53
TESTOUTP
—
53
54
54
TESTOUTN
—
IF1GND
– 11 –
Radio test output pin
Capacitor and
resistor connection
Radio test output pin
Capacitor and
resistor connection
CXD2951GA-2
Pin
No.
Symbol
Standard
pin voltage
[V]
Equivalent circuit
Description
IF2VCC
55
TESTOUTD
—
Radio digital test
output pin
Normally leave open.
55
IF2GND
56
IF1VCC
1.8
1st IF 1.8V
57
IF1GND
0
1st IF GND
58
IF2VCC
1.8
2nd IF 1.8V
59
IF2GND
0
2nd IF GND
IF1VCC
40k
60
VCOM
1.0
60
IF common voltage
1k
50k
IF1GND
IF1VCC
61
RREF
External resistor
connection
(VCO, PLL, IF block
bias)
1.1
6k
61
IF1GND
– 12 –
CXD2951GA-2
A/D Converter Operating Conditions
Item
Symbol
Supply voltage
VAD
Pin name
EAVDAD∗1
Operating temperature
Ta
—
A/D Converter Characteristics
Item
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
–40.0
+85.0
°C
(VAD = 3.0 to 3.6V, Ta = –40 to +85°C)
Symbol
Max.
Unit
Resolution
10
Bit
Channel
4
Ch
–1.0
+1.0
LSB
–2.0
+2.0
LSB
Differential linearity error (DLE)
VAD = 3.0V,
VRT = 3.0V, VRB = 0.3V
Integral linearity error (ILE)
Sampling time
TCXO = 18.414MHz
Conversion time
Reference input voltage (Bottom)
VRT∗2
VRB∗3
Analog input voltage
VIN∗4
Reference input voltage (Top)
Current consumption
Conditions
VAD = 3.0V
Applicable pins
∗1 EAVDAD (Pin 108)
∗2 EADVRT (Pin 107)
∗3 EADVRB (Pin 102)
∗4 EVIN[0:3] (Pins 103 to 106)
– 13 –
Min.
Typ.
µs
3
11
µs
2.0
VAD
V
0
0.7
V
VRB
VRT
V
1.6
mA
CXD2951GA-2
DC Characteristics
(IOVDD = 3.0 to 3.6V, CVDD = 1.62 to 1.98V, Ta = –40 to +85°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input voltage∗1
High level
VIH
2.0
5.5
V
Low level
VIL
–0.3
0.8
V
Output voltage∗2
High level
VOH1
IOH = 4mA
Low level
VOL1
IOL = 4mA
Output voltage∗3
High level
VOH2
IOH = 8mA
Low level
VOL2
IOL = 8mA
V
2.4
0.4
V
V
2.4
0.4
V
Pull-up resistor∗4
RU
48
110
kΩ
Pull-down resistor∗5
RD
40
100
kΩ
Current consumption during normal
IOPE
operation (via IOVDD, CVDD and VDD)∗6
Current consumption during backup
operation (via BKUPIOVDD)∗7
Current consumption during backup
operation (via BKUPCVDD)∗8
ISTB1
ISTB2
TCXO = 18.414MHz,
Ta = 25°C
60
BKUPIOVDD = 3.6V,
Ta = 25°C
0.2
1.0
µA
BKUPIOVDD = 3.6V,
Ta = 85°C
0.2
1.0
µA
BKUPCVDD = 1.98V,
Ta = 25°C
7.5
15
µA
BKUPCVDD = 1.98V,
Ta = 85°C
50
120
µA
mA
Applicable pins
∗1 Pins 1 to 13, 20, 24 to 29, 64 to 66, 98, 119, 120 to 122, 133 to 148, 151, 152, 155 to 170, 173
∗2 Pins 1 to 13, 21 to 23, 97, 174
∗3 Pins 67 to 74, 77 to 80, 83 to 90, 124 to 130, 133 to 148, 155 to 170
∗4 Pins 24, 25, 28, 29, 152
∗5 Pins 1 to 13, 20, 26, 27, 133 to 148, 155 to 170, 173
∗6 Pins 15, 76, 96, 100, 108, 112, 118, 132, 154, 176 (3.3V)
Pins 19, 31, 33, 37, 41, 42, 56, 58, 63, 82, 92, 114, 150, 172 (1.8V)
∗7 Pin 118
∗8 Pin 114
– 14 –
CXD2951GA-2
AC Characteristics
• External Expansion Bus (Read/32-bit mode)
(CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C)
Item
Symbol
Min.
Max.
Unit
EXOE ↓ to address valid
Toea
3
ns
EXOE ↓ to EXCS ↓
Toecs
1
ns
Data setup
Tas
15
ns
Data hold
Tah
0
ns
EXOE
Toea
EA[19:0]
Toecs
EXCS[1:0]
Tas
ED[31:0]
– 15 –
Tah
CXD2951GA-2
• Extarnal Expansion Bus (Write/32-bit mode (1-wait))
(CVDD = 1.62 to 1.98V, IOVDD = 3.0 to 3.6V, CL = 25pF, Topr = –40 to +85°C)
Item
Symbol
Min.
Max.
Unit
EXCS ↓ to address valid
Tcsfav
2
ns
EXCS ↓ to EXWE ↓
Tcswef
Tsys – 1
ns
EXCS ↓ to EXWE ↑
Tcswer
Tsys × 3 – 2
ns
EXCS ↓ to data valid
Tcsd
15
ns
∗ Tsys: ARM clock cycle
T1
T2
T3
EXCS[1:0]
Tcsfav
EA[19:0]
Tcswer
Tcswef
EXWE[3:0]
Tcsd
ED[31:0]
– 16 –
CXD2951GA-2
Backup Mode
The backup mode is established by setting both EOSCEN and EXRS low. In this mode, the low power
consumption can be achieved by stopping all oscillators except for RTC oscillator during the reset interval.
Although all registers are initialized, the SRAM contents in backup area are held.
In order to cancel this mode (reset cancellation), set EOSCEN high at first and then set EXRS high after the
oscillation stabilization time and PLL lock time have passed. It needs 100ms or more.
See Initialization section.
Normal operation
Backup
Reset
Normal operation
IOVDD
CVDD
BKUPIOVDD
BKUPCVDD
OSC, PLL output
EOSCEN
EXRS
Oscillation stabilization time
Power Off
Pull-down output
Power Off
Hi-Z output
EXCS[1:0], EXWE[3:0], EXOE
Power Off
High output
EA[19:0], ECLKOUT
Power Off
Low output
ED[31:0], EPORT[12:0], ERXD0
ETXD0
– 17 –
PLL lock time
(0.5ms max.)
CXD2951GA-2
Initialization
The CXD2951GA-2 is initialized by setting the reset signal EXRS (Pin 151) to the low level. Note that internal
RAM is not initialized by the operation. Satisfy the conditions shown below for the timing and others.
1. When turning the power on (Power-on reset)
VDD
Power supply,
EOSCEN
(Pin 119)
VDD [V]
EXRS (Pin 151)
100ms or more
VDD/2
GND
The power supply both 3.3V and 1.8V should turn on simultaneously, and EOSCEN (Pin 119) should also rise
simultaneously with the power supply turning on. EXRS (Pin 151) should rise 100ms or more after the power
supply and EOSCEN rise.
2. Initialization during operation
Power supply,
EOSCEN
(Pin 119)
VDD
EXRS (Pin 151)
VDD [V]
100µs or more
VDD/2
GND
For initialization during operation, the interior circuit except internal RAM is initialized by setting the EXRS
(Pin 151) signal to the low level for 100µs or more. Note that internal RAM is not also initialized by the
operation. At this time, the EOSCEN (Pin 119) signal should keep the high level.
– 18 –
CXD2951GA-2
RTC crystal and TCXO
In order to operate CXD2951GA-2 appropriately, the recommended characteristics of RTC crystal and TCXO
is shown below.
Recommended characteristics of RTC crystal
Operating temperature
Nominal frequency
Frequency tolerance
Frequency temperature coefficient
Frequency peak temperature
Frequency aging
–40 to +85°C
32.768kHz
±20ppm
–0.04ppm/°C2 (Max.)
+25 ± 5°C
±3ppm/year
Recommended characteristics of TCXO
Operating temperature
Frequency tolerance
Frequency vs. temperature
Frequency vs. supply voltage
–40 to +85°C
±2.0ppm
±2.5ppm
±0.2ppm
Frequency vs. load
Frequency aging
±0.2ppm
±1ppm/year
Recommended parts
RTC crystal
TCXO
EPSON FC-255
NDK SNA3088B (NT5032 series)
– 19 –
CXD2951GA-2
Radio Block Operation
Radio block diagram shows RF section of the chip. The signal flow starts from the RFIN port (Pin 47). The
signal is amplified and mixed down to the first Intermediate Frequency (IF) of 2MHz with cosine and sine wave
quadrature mixers. Out of band images are filtered out and the signal is again mixed down to the 2nd IF of
1MHz with another set of quadrature mixers. The complex signal becomes real with the addition of real and
imaginary components. The image of the 2nd IF mixing is removed with the last Band Pass Filter (BPF). The
real signal is then amplified one last time and transferred to digital baseband processing unit.
RF Digital
Reset
CLK
RF Analog
2nd IF (1MHz)
RFIN
A/D Converter
BPF
1st IF (2MHz)
Data
Baseband
BPF
BPF
RF Local
(1573MHz)
IF Local (3MHz)
VCO
VCO
PLL
PLL
BIAS
BUF
PLLCLK
Enable
TEST
LPFRF
LPFIF
Radio Block Diagram
To have constant internal frequencies for mixing and other purposes, the supplied TCXO frequency is counted
by a Real Time Clock (RTC), and the internal PLL divider is automatically set to provide correct frequency for
RF mixing and baseband operation.
The loop filters (RF and IF) are externally connected. Use parts that satisfy the required tolerance.
– 20 –
CXD2951GA-2
Radio Characteristics
DC Characteristics
Item
Supply current 1
Supply current 2
(VDD = 1.8V, Ta = 25°C)
Symbol
IDD
Conditions
Active mode∗1
IPS
Power save mode∗1
Min.
Typ.
Max.
Unit
13.5
17
20.5
mA
—
0.1
1.5
µA
∗1 Applicable pins 31, 33, 37, 41, 42, 56, 58
AC Characteristics
Item
(VDD = 1.8V, Ta = 25°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Total gain
G
Before the A/D converter
90
100
—
dB
Image rejection ratio
IMRR
Image frequency = 1571.328MHz
—
–35
–15
dB
2nd IF filter 2.5MHz
Fc
@2.5MHz Normalized at 1.023MHz
–6
0
4
dB
2nd IF filter 4MHz
Fa
@4MHz Normalized at 1.023MHz
—
–25
–15
dB
∗ Including the 50Ω matching circuit
Design Measurement Results
Item
(VDD = 1.8V, Ta = 25°C)
Conditions
Symbol
Min.
Typ.
Max.
Unit
Total NF
NF
Before the 2nd IF mixer
—
8
—
dB
IIP3
IIP3
Before the A/D converter
—
–90
—
dBm
P-1dB input
P1dB
Before the A/D converter
—
–100
—
dBm
S11
S11
—
–15
—
dB
Lock up time
LUT
Measure the interval between reset
input and IF output.
—
2.5
—
ms
C/N 100K
C/N
TCXO = 18.414MHz
—
–70
—
dBc/Hz
Local leak
Leak
Measure at RF input.
—
–65
—
dBm
∗ Including the 50Ω matching circuit
– 21 –
CXD2951GA-2
Radio Supplement Materials (Example of Representative Characteristics)
IDD
Input/output characteristic
24
10
VDD = 1.8V
Ta = 25˚C
22
5
0
Output level [dBm]
IDD [mA]
20
18
16
14
VDD = 1.8V
Ta = 25˚C
–5
–10
–15
–20
–25
–30
12
–35
10
1.6
–40
–135 –130 –125 –120 –115 –110 –105 –100 –95 –90 –85
2.0
1.8
VDD [V]
Input level [dBm]
IIP3
C/N
10
–50
5
VDD = 1.8V
Ta = 25˚C
–55
0
C/N [dBc/Hz]
Output level [dBm]
–60
–5
–10
–15
–20
–65
–70
–75
–25
–80
–30
VDD = 1.8V
Ta = 25˚C
–35
–85
–40
–130 –125 –120 –115 –110 –105 –100 –95 –90 –85 –80 –75 –70
–90
10
1000
Offset frequency [kHz]
Input level [dBm]
Image rejection ratio
IF filter response (simulation)
5
–20
0
VDD = 1.8V
Ta = 25˚C
–25
–5
Response [dB]
–30
IMRR [dB]
100
–35
–40
–10
–15
–20
–25
–30
–45
–35
–40
1.570 1.571 1.572 1.573 1.574 1.575 1.576 1.577 1.578 1.579 1.580 1.581
–50
0
0.5
1.0
1.5
2.0
2.5
3.0
Frequency [GHz]
IF frequency [MHz]
Filter characteristic represented by RF frequency as x-axis
(Normalized at 1.023MHz)
– 22 –
CXD2951GA-2
RFIN input impedance
+j50
+j25
+j100
+j10
0
25
–j10
50
∞
100
2GHz
1.8GHz
1.2GHz
1.6GHz
1.4GHz 1GHz
–j25
–j100
–j50
– 23 –
Application Circuit
L046
56nH
10P
CN012
TXD0
1
RXD0
2
RXD1
3
NMEA/Orig
4
UPDATE
5
RESET/POWER DOWN
DGND
VDD (3.3V/5V)
6
7
9
10
R005
10k
L040
1µH
L003
10µH
JS040
0
R063 22
1 XRESET
R202 XX
BATT 6
IC003
MAX6364
2 GND
IC002
XX
R062 22
BKUPIOVDD_3.3V
OUT 5
3 Reset In
L002 22µH
C004
22µ
JS041
0
1 VOUT 5
NC
C161
2 GND
10µ
4
3 VDD
CE
C046
0.1µ
IC004
2 GND R3112Q291A
BKUPCVDD_1.8V
IC005 R1124N181D
2 GND
ECO 4
3
CE
C121
0.1µ
1 VDD
R1124N331D
VDD
VOUT 5
1
R013
470k
C013
10µ
Application circuits shown are typical examples
illustrating the operation of the devices. Sony
cannot assume responsibility for any problems
arising out of the use of these circuits or for
any infringement of third party patent and other
right due to same.
IC006 R1160N181B
Vcc 4
R205 47k
8
BATT
AGND
R004
10k
R001 22
R002 22
CD 3
1 VOUT 5
NC
2 GND
C059
0.1µ
OUT 4
C150
10µ
L045
1µH
C045
0.1µ
C066
10µ
4
3 VDD
C048
2.2µ
CE
C162
10µ
JS025
0
SYSTEM_RESET
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
C079
0.1µ
ED15
ED14
ED13
ED9
ED12
ED8
ED11
ED7
ED10
ED6
ED5
ED4
ED3
ED2
C077
0.1µ
ED1
C072
0.1µ
ED0
C069
0.1µ
133 ED31
D18
EXCS1
E16
124
EXCS0
D17
123
IOVSS4
E17
F3 11 EPORT10
122
ECLKS2
F16
F17
EADVRB
102
L18
N18
101
EAVSAD
P3 33 VDDCP
100
EAVDPLL
N16
N1 34 LPFIF
99
EAVSPLL
M17
P2 35 LPFRF
98
EXROMI
P16
R198
33k
P1 36 VSSCP
97
ECLKOUT
N17
R3 37 VDDVCO
96
IOVDD3
R16
C144
0.01µ
R1 38 VSSVCO
95
IOVSS3
P17
R18
CVDD4
T18
91
CVSS4
R17
T2 43 RFRREF
90
EA0
U18
U2 44 MIXGND
89
EA1
T17
C092
0.1µ
ED24
ED22
L024
1µH
R028
XX
EA11
R201 XX
C126
0.1µ
EA16
EA19
ED4
NC E6
ED9
EA9
C094
0.1µ
EA12
EA18
ED12
ED28
NC E5
ED2
DQ2 E4
J3 A6
DQ18 E3
J4 A9
DQ19 E2
J5 NC
DQ3 E1
IC021
MBM29PL320
J6 A14
J7 A17
ED18
ED19
ED3
ED13
DQ13 D9
ED29
DQ29 D8
ED14
DQ14 D7
J9 DQ9
CVDD_1.8V
ED20
ED31
DQ31/A-1 D6
K2 Vss
NC D5
K3 A7
A0 D4
K4 A10
DQ16 D3
K5 NC
Vss D2
K6 A13
Vcc D1
K7 A16
Vcc C9
K8 A19
DQ15 C8
NC
A1
A4
EA2
ED16
C127
0.1µ
ED15
C128
0.1µ
C148
XX
C076
0.1µ
C082
0.1µ
EA5
ED0
DE1
ED17
ED30
EA4
EA7
EA3
EA6
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
EA15
EA16
EA17
R200
56k
EA18
A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7
EA19
C146
0.001µ
ED5
Vss E7
H9 Vcc
C147
0.01µ
CL005
CL004
CL002
CL003
CL001
C166
100p
R207
1M
DQ4
DQ28 E8
H8 DQ24
U3 U4 V2 U5 V3 V4 T4 T6 V5 U6 T5 U7 V6 T7 V7 U8 T8 V8 U9 V9 T9 T10 V10 U10 T11 U11 V11 T12 U12 T13 V12 V13 U13 T14 V14 U14 V15 T15 U15 T16 V16 U16 V17 U17
R206
1M
DQ5
DQ12 E9
H7 A18
J8 Vcc
88 EA2
87 EA3
86 EA4
85 EA5
84 EA6
83 EA7
82 CVDD3
81 CVSS3
80 EA8
79 EA9
78 EA10
77 EA11
76 IOVDD2
75 IOVSS2
74 EA12
73 EA13
72 EA14
71 EA15
70 EA16
69 EA17
68 EA18
DQ20 F1
H6 A15
J2 DQ23
EA8
C093
0.1µ
H5 NC
J1 DQ22
ED23
R025
100k
EA15
67 EA19
66 ETEST2
65 ETSET1
64 ETEST0
63 CVDD2
62 CVSS2
61 RREF
60 VCOM
59 IF2GND
58 IF2VCC
57 IF1GND
56 IF1VCC
55 TESTOUTD
54 TESTOUTN
JS038
0
P18
ECLKI
92
94
T3 40 RFSUB
53 TESTOUTP
JS037 XX
R199 2k
ECLKO
93
T1 41 LNAMAT
U1 42 NRING
R2 39 VCODECAP
52 TESTINN
L004
2.7nH
51 TESTINP
C145
10p
L17
EA17
C125
0.1µ
XOE
M1 30 RADIOSUB
M16
NC
M18
EVIN0
ED10
L16
EVIN1
103
NC
EVIN2
104
XWP
EVIN3
105
L3 29 ETESTTMS
ED11
106
M2 28 TMS
NC
M3 27 ETESTTCK
H4 H3 H2 H1 G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2
NC
K16
DQ10
K17
EADVRT
A3
EAVDAD
107
DQ0
108
L1 26 TCK
DQ1
K3 25 ETESTTDI
R057
100k
R056
100k
ED6
J17
ED27
K18
IOVSS8
Vss
ETEST3
109
DQ6
110
C090
0.1µ
DQ11
J16
BKUPCVSS H16
DQ27
J18
ETEST4
DQ17
IOVDD7
K1 22 TDO
111
DQ30
112
EA14
113
EA10
114
K2 21 ETESTTINT
N2 32 VSSPLL
C086
12p
BKUPCVDD H17
J2 19 CVDD1
H3 20 TRST
IC020
CXD2951GA-2
C124
0.1µ
C085
12p
Vss
H18
DW/XW
ECCKI
ED8
115
X002
ED21
J1 18 CVSS1
C089 0.1µ
R203
22
DQ21
G18
NC
ECCKO
ED25
BKUPIOVSS G17
116
NC
BKUPIOVDD F18
117
A12
118
H1 17 EXTCXO
DQ8
H2 15 IOVDD1
G1 16 ETCXO
DQ25
G16
ACC
F1 14 IOVSS1
EOSCEN
A2
E18
119
A5
ECLKS0
Vcc
ECLKS1
120
ED7
121
ED26
G2 12 EPORT11
G3 13 EPORT12
Vss
EXOE
125
EPORT8
DQ26
126
EPORT7
E1 10 EPORT9
XCE
EPORT6
F2 9
NC
EPORT5
E3 7
D1 8
Vcc
134 ED30
135 ED29
136 ED28
137 ED27
138 ED26
139 ED25
140 ED24
141 ED23
142 ED22
143 ED21
144 ED20
148 ED16
145 ED19
149 CVSS5
146 ED18
E2 6
D16
50 MIXGND
L039
12nH
150 CVDD5
C18
EXWE3
127
49 LNASRC
C143
68p
147 ED17
C16
EXWE2
48 MIXGND
C149
0.01µ
151 EXRS
B18
EXWE1
128
N3 31 VDDPLL
R197
470
C141
3300p
C142
680p
152 ETESTXRS
EXWE0
129
EPORT4
47 RFIN
C140
0.068µ
153 IOVSS6
156 ED14
157 ED13
IOVSS5
130
EPORT3
46 MIXGND
JS039
0
154 IOVDD5
131
EPORT2
XWE
C153
XX
C139
0.001µ
155 ED15
158 ED12
159 ED11
161 ED9
160 ED10
162 ED8
163 ED7
164 ED6
165 ED5
166 ED4
167 ED3
169 ED1
168 ED2
172 CVDD6
173 ERXD0
170 ED0
174 ETXD0
171 CVSS6
EPORT1
C1 4
L2 24 TDI
C122
0.1µ
C17
B1 2
D2 3
D3 5
J3 23 ETESTTDO
L051
56nH
B17
EA13
C068
0.1µ
X001
Note) The following should be guaranteed
within operating temperature.
• R tolerance: ±5% or less
• C tolerance: ±20% or less
• L tolerance: ±20% or less
C088
0.1µ
IOVDD4
A8
R020 1M
132
45 LNASRC
– 24 –
C060
0.01µ
EPORT0
A11
C067
0.1µ
C3 1
DQ7
R204
22
175 IOVSS7
176 IOVDD6
C2 B3 B2 C4 A2 B4 A3 C5 A4 C6 A5 C7 B5 B6 A6 C8 A7 B7 C9 B8 A8 C10 B9 A9 A10 A11 B10 B11 A12 C11 B12 C12 A13 C13 A14 B13 A15 C14 B14 C15 A16 B16 A17 B16
C083
0.1µ
C167
100p
C129
0.1µ
C154
0.1µ
L035
56nH
C134
0.001µ
L044
4.7nH
C132
39p
L050
3.9nH
L034
15nH
IC022
L048
12nH
6
2
5
3
C131
100p
NJG1107KB2
1
4
L018
27nH C163
XX
C158
0.1µ
L036
56nH
C159
0.001µ
L043
3.3nH
C155
1p
SWF001
C157
XX
L042
15nH
C156
100p
IC024
NJG1107KB2
L041
12nH
1
6
2
5
3
4
TP001
L023
82nH
CXD2951GA-2
Note) If a Flash ROM is used,
the programs which are GPS
software, Flash updater etc.
required for desired operation
should be written into a Flash
ROM in advance.
CXD2951GA-2
Radio Block Application Circuit
Application circuits shown are typical examples
illustrating the operation of the devices. Sony
cannot assume responsibility for any problems
arising out of the use of these circuits or for
any infringement of third party patent and other
right due to same.
M3 27 ETESTTCK
M2 28 TMS
C153
XX
C139
0.001µ
C140
0.068µ
N3 31 VDDPLL
R197
470
N2 32 VSSPLL
C141
3300p
C142
680p
P2 35 LPFRF
R198
33k
P1 36 VSSCP
R3 37 VDDVCO
C144
0.01µ
R1 38 VSSVCO
R2 39 VCODECAP
L004
2.7nH
T3 40 RFSUB
T1 41 LNAMAT
JS037 XX
R199 2k
U1 42 NRING
T2 43 RFRREF
80 EA8
79 EA9
77 EA11
78 EA10
76 IOVDD2
75 IOVSS2
74 EA12
72 EA14
73 EA13
71 EA15
70 EA16
68 EA18
69 EA17
67 EA19
66 ETEST2
65 ETSET1
64 ETEST0
63 CVDD2
62 CVSS2
61 RREF
60 VCOM
58 IF2VCC
59 IF2GND
57 IF1GND
56 IF1VCC
55 TESTOUTD
54 TESTOUTN
53 TESTOUTP
52 TESTINN
51 TESTINP
50 MIXGND
45 LNASRC
JS038
0
49 LNASRC
U2 44 MIXGND
48 MIXGND
L039
12nH
C145
10p
47 RFIN
C149
0.01µ
C143
68p
P3 33 VDDCP
N1 34 LPFIF
46 MIXGND
JS039
0
L3 29 ETESTTMS
M1 30 RADIOSUB
R206
1M
C166
100p
R207
1M
C148
XX
C076
0.1µ
L050
3.9nH
C154
0.1µ
L035
56nH
C134
0.001µ
L044
4.7nH
L034
15nH
IC022
6
2
5
3
4
C131
100p
Parts name
Remarks
C139 to C147,
C149,
C166, C167
MURATA GRM36CH series
Tolerance: ±5%
C145: Self-resonant frequency 2.0GHz or more
L004,
L039,
L050
TAIYO YUDEN HK1005 series
Tolerance: ±5%
L050: Self-resonant frequency 2.0GHz or more
R197 to R200
KOA RK73H series
Tolerance: ±1%
R206, R207
KOA RK73B series
Tolerance: ±5%
∗ Always use matching circuit for the RF amplifier input pin (Pin 47), and match at 1.57542GHz.
∗ The external elements should be placed as close to the chip as possible.
EA8
EA9
NJG1107KB2
1
Enlarged view of the previous page
– 25 –
EA10
C082
0.1µ
C167
100p
C132
39p
Parts ID
EA11
EA12
EA13
EA14
EA15
EA16
EA17
R200
56k
EA18
C146
0.001µ
EA19
C147
0.01µ
CL005
CL004
CL002
CL003
CL001
U3 U4 V2 U5 V3 V4 T4 T6 V5 U6 T5 U7 V6 T7 V7 U8 T8 V8 U9 V9 T9 T10 V10 U10 T11 U11 V11 T12 U12 T13 V12 V13 U13 T14 V14 U14
CXD2951GA-2
Package Outline
Unit: mm
176PIN LFLGA
S A
0.1
X
1.3MAX
PIN 1 INDEX
0.08 S
12.0
S B
0.2 S
12.0
0.10MAX
x4
0.1
0.08
S
Y
1.2
(0.55)
1.0 (0.55)
DETAIL X
φ0.35
φ0.05 M S A B
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.5
B
DETAIL Y
1.75
1.2
176 – φ0.27 ± 0.04
1.2
1.0
C0.3
0.5
A
(0.55)
3–
1 2 3 4 5 6 7 8 9 101112131415161718
(0.55)
1.0
1.2
0.25
1.75
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
LFLGA-176P-052
EIAJ CODE
P-LFLGA176-12x12-0.5
JEDEC CODE
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
– 26 –
ORGANIC SUBSTRATE
NICKEL&GOLD PLATING
COPPER
0.4g
Sony Corporation