W83194BR-648 Data Sheet WIBOND CLOCK GENERATOR FOR SIS P4 SERIES CHIPSET -I- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 Table of Contents1. GENERAL DESCRIPTION ..........................................................................................................1 2. FEATURES ..................................................................................................................................1 3. PIN CONFIGURATION ................................................................................................................2 4. BLOCK DIAGRAM .......................................................................................................................2 5. PIN DESCRIPTION......................................................................................................................3 5.1 Crystal I/O................................................................................................................................. 3 5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs............................................................................... 3 5.3 I2C Control Interface ................................................................................................................ 4 5.4 Fixed Frequency Outputs ........................................................................................................4 5.5 Power Management Pins......................................................................................................... 4 5.6 Power Pins................................................................................................................................ 5 5.7 Hardware MULTSEL0 Selects Function ................................................................................. 5 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................6 7. I2C CONTROL AND STATUS REGISTERS ................................................................................7 8. 7.1 Register 4: Frequency Select (Default = 00H)........................................................................ 7 7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH) ....................... 7 7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH) ......................................... 8 7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH) ............. 8 7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH) ................................... 8 7.6 Register 9: Watchdog Control (Default = 00H) ....................................................................... 9 7.7 Register 10: Watchdog Timer (Default = 08H) ....................................................................... 9 7.8 Register 11: M/N Program (Default = ABH)............................................................................ 9 7.9 Register 12: M/N Program (Default = 2FH) ..........................................................................10 7.10 Register 13: Spread Spectrum Programming (Default = 1FH) ............................................10 7.11 Register 14: Divisor and Step-less Enable Control (Default = 4CH) ...................................10 7.12 Register 15: CPU_ZCLK Skew Control (Default = A7H)......................................................11 7.13 Register 16: CPU_AGP_SKEW (Default = 1CH) .................................................................11 7.14 Register 17: Skew Control (Default = 24H)...........................................................................11 7.15 Register 18: Winbond Chip ID (Read Only) (Default = 77H)................................................12 7.16 Register 19: Winbond Chip ID (Read Only) (Default = 11H)................................................12 7.17 Ratio Selection Table .............................................................................................................13 ACCESS INTERFACE ...............................................................................................................14 8.1 Block Write Protocol...............................................................................................................14 8.2 Block Read Protocol...............................................................................................................14 - II - W83194BR-648 9. 10. 8.3 Byte Write Protocol.................................................................................................................14 8.4 Byte Read Protocol ................................................................................................................14 SPECIFICATIONS .....................................................................................................................15 9.1 Absolute Maximum Ratings...................................................................................................15 9.2 General Operating Characteristics ........................................................................................15 9.3 Skew Group Timing Clock .....................................................................................................16 9.4 CPU 0.7V Electrical Characteristics ......................................................................................16 9.5 CPU 1.0V Electrical Characteristics ......................................................................................16 9.6 AGP Electrical Characteristics...............................................................................................17 9.7 PCI Electrical Characteristics.................................................................................................17 9.8 ZCLK Electrical Characteristics .............................................................................................17 9.9 SDRAM Electrical Characteristics .........................................................................................18 9.10 24M, 48M Electrical Characteristics ......................................................................................18 9.11 REF Electrical Characteristics ...............................................................................................18 POWER MANAGEMENT TIMING .............................................................................................19 10.1 CPU_STOP# Timing Diagram...............................................................................................19 10.2 PCI_STOP# Timing Diagram ................................................................................................19 11. ORDERING INFORMATION......................................................................................................20 12. HOW TO READ THE TOP MARKING .......................................................................................20 13. PACKAGE DRAWING AND DIMENSIONS ...............................................................................21 14. REVISION HISTORY .................................................................................................................22 - III - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 1. GENERAL DESCRIPTION The W83194BR-648 is a Clock Synthesizer for SIS P4 series chipset. W83194BR-648 provides all clocks required for high-speed Intel Pentium 4, and also provides 32 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR648 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194BR-648 provides step-less frequency programming by controlling the VCO freq. and the programmable AGP, PCI clock output divisor ratio. AGP and PCI frequency can be fixed to be four kinds of different frequency outputs. A watchdog timer is quipped and when time out, register9 bit5 will be set to 1 for warning. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The W83194BR-648 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF loads. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V /nS slew rate. 2. FEATURES • Supports Intel Pentium 4 CPU with I2C. • 2 pairs of differential CPU clocks • 2 ZCLK for SIS chipsets • 2 AGP clocks • 1 SDRAM output clock for chipset • 8 PCI synchronous clocks • 1 24/48 MHz, 1 48 MHz • 3 REF clocks • Skew --- CPU to SDRAM < 1 ns, PCI to PCI < 500ps, AGP to AGP < 175ps • Smooth frequency switch with selections from 66 to 200 MHz • I2C 2-Wire serial interface and I2C read back • Flexible spread spectrum to reduce EMI • Programmable registers to enable/stop each output • Packaged in 48-pin SSOP -1- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 3. PIN CONFIGURATION V D D R F S 0 & /R E F 0 F S 1 & /R E F 1 F S 2 & /R E F 2 G N D X IN XO U T G N D ZC LK 0 ZC LK 1 V D D Z P C I_ S T O P # * V D D P C I F S 3 & /P C IC L K _ F 0 F S 4 & /P C IC L K _ F 1 P C IC L K 0 P C IC L K 1 G N D V D D P C I P C IC L K 2 P C IC L K 3 P C IC L K 4 P C IC L K 5 G N D 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 V D D S D S D R A M G N D C P U _S TO P #* C P U C LK T_1 C P U C LK C _1 V D D C G N D C P U C LK T_0 C P U C LK C _0 IR E F G N D V D D A S D C LK * S D A TA * P D # * /V T T _ P W G D G N D A G P C LK 0 A G P C LK 1 V D D A G P V D D 48 48M H z 2 4 _ 4 8 M H z /M U L T IS E L 0 * G N D #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND 4. BLOCK DIAGRAM Driver 48MHz PLL2 XIN XOUT 24_48MHz Mux 1/2 XTAL OSC 3 REF0:2 VCOCLK PLL1 Spread Spectrum 3 Stop CPUCLK_T 0:1 CPUCLK_C 0:1 3 M/N/Ratio S.S.P ROM SDRAM Divider 2 ZCLK 0:1 2 VTT_PWGD FS<0:4> AGPCLK 0:1 Latch & POR 8 Stop PD#* PCI_STOP#* CPU_STOP#* MULTISEL0* PCICLK_F0:1 PCICLK_0:5 Control Logic & Config Register Rref SDATA* SDCLK* I2C interface -2- W83194BR-648 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN INtp120k INtd120k OUT OD I/O I/OD # * DESCRIPTION Input Latched input at power up, internal 120KΩ pull up. Latched input at power up, internal 120KΩ pull down. Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain. Active Low Internal 120kΩ pull-up & Internal 120 kΩ pull-down 5.1 Crystal I/O PIN PIN NAME TYPE 6 XIN IN 7 XOUT OUT DESCRIPTION Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF). 5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs PIN PIN NAME TYPE 40, 39, 44, 43 CPUCLKT_0 CPUCLKC_0, CPUCLKT_1 CPUCLKC_1, OUT 47 14 15 SDRAM OUT PCICLK_F0 OUT FS3& INtd120k PCICLK_F1 OUT FS4& INtd120k 16, 17, 20, PCICLK [0:5] 21, 22, 23 31, 30 AGPCLK [0:1] 9, 10 ZCLK [0:1] DESCRIPTION True CPU clock output and Complementary CPU clock output. These pins will be stopped by CPU_STOP# SDRAM clock output, which have syn. or asyn. Frequencies as CPU clocks. The clock phase is the same as CPUCLKT_0 and CPUCLKT_1. PCI free running clock during normal operation. Latched input for FS3 at initial power up for H/W selecting the output frequency. Internal 120KΩ pull-down PCI free running clock during normal operation. Latched input for FS4 at initial power up for H/W selecting the output frequency. Internal 120KΩ pull-down OUT Low skew (< 500 pS) PCI clock outputs. OUT OUT AGP clock outputs for AGP. Z clock outputs for chipset. -3- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 5.3 I2C Control Interface PIN PIN NAME TYPE DESCRIPTION 2 34 SDATA* I/O Serial data of I C 2-wire control interface, Internal 120KΩ pull-up. 35 SDCLK* IN Serial clock of I2C 2-wire control interface, Internal 120KΩ pull-up. 5.4 Fixed Frequency Outputs PIN 38 2 3 4 26 27 PIN NAME TYPE DESCRIPTION IREF IN Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are two modes to select different current via power on trapping the Pin 26 (MULTISEL0). The table is show as follows. REF0 OUT FS0& INtd120k REF1 OUT FS1& INtd120k REF2 OUT FS2& INtd120k 24_48 MHz OUT MULTISEL0* INtp120k 48 MHz OUT 3.3V, 14.318 MHz reference clock output. Latched input for FS0 at initial power up for H/W selecting the output frequency. Internal 120 KΩ pull- down. 3.3V, 14.318 MHz reference clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency, Internal 120 KΩ pull- down. 3.3V, 14.318 MHz reference clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency. Internal 120 KΩ pull- down. 24 MHz or 48 MHz clock output selected by Register. MULTISEL0* at initial power up for H/W selecting the current multiplier for CPU outputs. Internal 120 KΩ pull-up. 48 MHz output for USB. 5.5 Power Management Pins PIN PIN NAME TYPE DESCRIPTION IN Power Down pin, low active all clocks are stopped, internal 120KΩ pull up. VTT_PWGD IN Power good input signal comes from ACPI with high active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL0 input are valid and is ready to sample. This pin is high active. 45 CPU_STOP#* IN CPU clock stop control pin, This pin is low active. Internal 120KΩ pull-up. 12 PCI_STOP#* IN PCI clock stop control pin, This pin is low active. Internal 120KΩ pull-up. PD#* 33 -4- W83194BR-648 5.6 Power Pins PIN PIN NAME DESCRIPTION 1 VDDR Power supply for REF0: 2 3.3V. 11 VDDZ Power supply for ZCLK 3.3V. 36 VDDA Power supply for core logic. 3.3V 42 VDDC Power supply for CPUCLK 3.3V. 29 VDDAGP Power supply for AGP outputs. 13,19 VDDPCI Power supply for PCI outputs. 48 VDDSD Power supply for SDRAM 3.3V. 28 VDD48 Power supply for 48/24 MHz outputs. 5, 8, 18, 24, 25, 32, 37, 41, 46 GND Circuit Ground. 5.7 Hardware MULTSEL0 Selects Function MULTSEL0 PIN 26 BOARD TARGET TRACE/TERM Z 0 50 Ω 0 60 Ω 1 50 Ω 1 60 Ω 0 50 Ω 0 60 Ω 1 50 Ω 1 60 Ω REFERENCE R, IREF = VDD/(3*RR) Rr = 221 1% IREF = 5.00 mA Rr =221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA -5- OUTPUT CURRENT VOH @ Z Ioh = 4*IREF 1.0V @ 50 Ioh = 4*IREF 1.2V @ 60 Ioh = 6*IREF 1.5V @ 50 Ioh = 6*IREF 1.8V @ 60 Ioh = 4*IREF 0.47V @ 50 Ioh = 4*IREF 0.56V @ 60 Ioh = 6*IREF 0.7V @ 50 Ioh = 6*IREF 0.84V @ 60 Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 4 bit 4 ~ 7, 2) FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) ZCLK (MHz) AGP (MHz) PCI (MHz) 0 0 0 0 0 100.2 100.2 80.2 66.8 33.4 0 0 0 0 1 100.2 133.6 80.2 66.8 33.4 0 0 0 1 0 100.2 200.5 80.2 66.8 33.4 0 0 0 1 1 100.2 167.0 83.5 62.6 31.3 0 0 1 0 0 133.6 100.2 80.2 66.8 33.4 0 0 1 0 1 133.6 133.6 80.2 66.8 33.4 0 0 1 1 0 133.6 200.5 80.2 66.8 33.4 0 0 1 1 1 133.7 167.2 83.6 66.9 33.4 0 1 0 0 0 166.6 99.9 83.3 62.5 31.2 0 1 0 0 1 166.8 133.4 83.4 66.7 33.4 0 1 0 1 0 166.8 222.4 83.4 66.7 33.4 0 1 0 1 1 166.8 166.8 83.4 66.7 33.4 0 1 1 0 0 199.7 99.9 79.9 66.6 33.3 0 1 1 0 1 199.7 133.2 79.9 66.6 33.3 0 1 1 1 0 199.7 199.7 79.9 66.6 33.3 0 1 1 1 1 200.0 150.0 75.0 66.7 33.3 1 0 0 0 0 100.2 100.2 133.6 66.8 33.4 1 0 0 0 1 100.2 133.6 133.6 66.8 33.4 1 0 0 1 0 100.2 200.5 133.6 66.8 33.4 1 0 0 1 1 100.2 167.0 125.3 62.6 31.3 1 0 1 0 0 133.6 100.2 133.6 66.8 33.4 1 0 1 0 1 133.6 133.6 133.6 66.8 33.4 1 0 1 1 0 133.6 200.5 133.6 66.8 33.4 1 0 1 1 1 133.7 167.2 133.7 66.9 33.4 1 1 0 0 0 166.6 99.9 124.9 62.5 31.2 1 1 0 0 1 166.8 133.4 133.4 66.7 33.4 1 1 0 1 0 166.8 222.4 133.4 66.7 33.4 1 1 0 1 1 166.8 166.8 133.4 66.7 33.4 1 1 1 0 0 199.7 99.9 133.2 66.6 33.3 1 1 1 0 1 199.7 133.2 133.2 66.6 33.3 1 1 1 1 0 199.7 199.7 133.2 66.6 33.3 1 1 1 1 1 200.0 150.0 120.0 66.7 33.3 -6- W83194BR-648 7. I2C CONTROL AND STATUS REGISTERS The Register 0~3 are reserved for external clock buffer (The register No. Is increased by 1 if use byte data read/write protocol) 7.1 Register 4: Frequency Select (Default = 00H) BIT NAME PWD 7 SSEL [3] 0 6 SSEL [2] 0 5 SSEL [1] 0 4 SSEL [0] 0 DESCRIPTION Frequency selection by software via I2C Enable software program FS [4:0]. 3 EN_SSEL 0 0 = Select frequency by hardware. 1 = Select frequency by software I2C - Bit 4:7, 2. 2 SSEL [4] 0 Frequency selection bit 4 Enable Spread Spectrum in the frequency table. 1 EN_SPSP 0 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. 0 EN_SAFE_FREQ 0 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 9 bit 4~0. 7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH) BIT PIN NO PWD DESCRIPTION 7 47 1 SDRAM output control 6 44, 43 1 CPUCLKT/C1 output control 5 40, 39 1 CPUCLKT/C0 output control 4 15 X Invert Power on latched value of FS4 pin, Default 1 (Read only) 3 14 X Invert Power on latched value of FS3 pin. Default 1 (Read only) 2 4 X Invert Power on latched value of FS2 pin. Default 1 (Read only) 1 3 X Invert Power on latched value of FS1 pin. Default 1 (Read only) 0 2 X Invert Power on latched value of FS0 pin. Default 1 (Read only) -7- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH) BIT PIN NO PWD 7 6 5 4 3 2 1 0 15 14 23 22 21 20 17 16 1 1 1 1 1 1 1 1 DESCRIPTION PCICLK_F1 output control PCICLK_F0 output control PCICLK 5 output control PCICLK 4 output control PCICLK 3 output control PCICLK 2 output control PCICLK 1 output control PCICLK 0 output control 7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH) BIT PIN NO PWD 7 6 27 26 1 1 5 SEL_24 1 4 3 2 1 0 10 9 4 3 2 1 1 1 1 1 DESCRIPTION 48 MHZ output control 24_48 MHz output control 24/48 MHz frequency control 1: 24 MHz. 0: 48 MHz. ZCLK1 output control ZCLK0 output control REF2 output control REF1 output control REF0 output control 7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH) BIT Pin NO PWD 7 1 6 1 5 0 4 0 3 2 1 0 30 31 MULTISEL0 Reserved 1 1 X 0 DESCRIPTION CPUCLKT/C0 Stop control: 0: CPUCLK0 free run 1: CPUCLK0 can stopped by CPU_STOP# CPUCLKT/C1 Stop control: 0: CPUCLK1 free run 1: CPUCLK1 can stopped by CPU_STOP# PCI_F0 Stop control: 0: PCI_F0 free run 1: PCI_F0 can stopped by PCI_STOP# PCI_F1 Stop control: 0: PCI_F1 free run 1: PCI_F1 can stopped by PCI_STOP# AGP_1 output control AGP_0 output control MULTISEL0 trapping pin data read back, Default 1. Reserved -8- W83194BR-648 7.6 Register 9: Watchdog Control (Default = 00H) BIT NAME PWD DESCRIPTION 7 Reserved 0 6 EN_WD 0 Reserved Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. 5 WD_TIMEOUT 0 4 3 2 SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] 0 0 0 1 0 SAF_FREQ [1] SAF_FREQ [0] 0 0 Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only. Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits. 7.7 Register 10: Watchdog Timer (Default = 08H) BIT NAME PWD 7 6 5 4 3 2 WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] 0 0 0 0 1 0 1 0 WD_TIME [1] WD_TIME [0] 0 0 DESCRIPTION Watchdog timeout time. The bit resolution is 250 mS. The default time is 8*250 mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value. 7.8 Register 11: M/N Program (Default = ABH) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 N_DIV [8] TEST2 TEST1 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] 1 0 1 0 1 0 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 12. Test bit 2. WINBOND test bit, do not change them. Test bit 1. WINBOND test bit, do not change them. 0 M_DIV [0] 1 Programmable M divisor value. -9- Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 7.9 Register 12: M/N Program (Default = 2FH) BIT NAME PWD 7 N_DIV [7] 0 6 5 4 3 2 1 N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] 0 1 0 1 1 1 0 N_DIV [0] 1 DESCRIPTION Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 11. 7.10 Register 13: Spread Spectrum Programming (Default = 1FH) BIT NAME PWD DESCRIPTION 7 6 SP_UP [3] SP_UP [2] 0 0 Spread Spectrum Up Counter bit 3. Spread Spectrum Up Counter bit 2. 5 4 3 2 1 0 SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0] 0 1 1 1 1 1 Spread Spectrum Up Counter bit 1. Spread Spectrum Up Counter bit 0 Spread Spectrum Down Counter bit 3 Spread Spectrum Down Counter bit 2 Spread Spectrum Down Counter bit 1 Spread Spectrum Down Counter bit 0 7.11 Register 14: Divisor and Step-less Enable Control (Default = 4CH) BIT NAME PWD DESCRIPTION 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318 MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 4 bit 0). 7 EN_MN_PROG 0 6 5 4 RATIO_SEL [4] RATIO_SEL [3] RATIO_SEL [2] 1 0 0 3 2 1 0 RATIO_SEL [1] RATIO_SEL [0] TEST0 Reserved 1 1 0 0 CPU, PCI, AGP, SDRAM, and ZCLK ratio selection. The ratio is shown as following table. Test bit 0. WINBOND test bit, do not change them. - 10 - W83194BR-648 7.12 Register 15: CPU_ZCLK Skew Control (Default = A7H) BIT NAME PWD DESCRIPTION 7 CPU_ZCLK_SKEW [2] 1 CPU to ZCLK SKEW control 6 Reserved 0 Reserved 5 Reserved 1 4 Reserved 0 3 Reserved 0 2 Reserved 1 1 Reserved 1 0 Reserved 1 Reserved 7.13 Register 16: CPU_AGP_SKEW (Default = 1CH) BIT NAME PWD DESCRIPTION 7 SEL [1] 0 6 SEL [0] 0 5 FIX_AGP_PCI 0 0:normal mode, 1: fix mode 4 CPU_STOP 1 CPU_STOP pin read back 3 PCI_STOP 1 CPU_STOP pin read back 2 CPU_AGP_SKEW [2] 1 1 CPU_AGP_SKEW [1] 0 0 CPU_AGP_SKEW [0] 0 AGP & PCI FIX frequency (PCI = AGP/2) SEL [1:0] for AGP 00: 72 MHZ 01: 64 MHZ 10: 77NHZ 11: 67MHZ CPU to AGP skew. 7.14 Register 17: Skew Control (Default = 24H) BIT NAME PWD 7 CPU_ZCLK_SKEW [1] 0 6 CPU_ZCLK_SKEW [0] 0 5 CPU_SDRAM_SKEW [2] 1 4 CPU_SDRAM_SKEW [1] 0 3 CPU_SDRAM_SKEW [0] 0 2 CPU_PCI_SKEW [2] 1 1 CPU_PCI_SKEW [1] 0 0 CPU_PCI_SKEW [0] 0 DESCRIPTION CPU to AGP skew CPU to SDRAM skew CPU to PCI skew - 11 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 7.15 Register 18: Winbond Chip ID (Read Only) (Default = 77H) BIT NAME PWD DESCRIPTION 7 CHPI_ID [7] 0 WINBOND Chip ID. W83194BR-648 is 0x77. 6 CHPI_ID [6] 1 WINBOND Chip ID. 5 CHPI_ID [5] 1 WINBOND Chip ID. 4 CHPI_ID [4] 1 WINBOND Chip ID. 3 CHPI_ID [3] 0 WINBOND Chip ID. 2 CHPI_ID [2] 1 WINBOND Chip ID. 1 CHPI_ID [1] 1 WINBOND Chip ID. 0 CHPI_ID [0] 1 WINBOND Chip ID. 7.16 Register 19: Winbond Chip ID (Read Only) (Default = 11H) BIT NAME PWD DESCRIPTION 7 SUB_ID [3] 0 WINBOND Sub-Chip ID. The sub-chip ID of W83194BR-648 is defined as 0001b. 6 SUB_ID [2] 0 WINBOND Sub-Chip ID. 5 SUB_ID [1] 0 WINBOND Sub-Chip ID. 4 SUB_ID [0] 1 WINBOND Sub-Chip ID. 3 VER_ID [3] 0 WINBOND Version ID. The Version ID of W83194BR-648 is 0001b. 2 VER_ID [2] 0 WINBOND Version ID. 1 VER_ID [1] 0 WINBOND Version ID. 0 VER_ID [0] 1 WINBOND Version ID. - 12 - W83194BR-648 7.17 Ratio Selection Table Table of CPU, PCI, AGP, SDRAM, and ZCLK clock selection. Reg14 Reg14 Reg14 Reg14 Reg14 Bit6 Bit5 Bit4 Bit3 Bit2 CPU SDRAM ZCLK AGP PCI SSEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 4 4 4 5 3 3 3 5 3 4 4 4 2 2 2 3 4 4 4 5 3 3 3 5 3 4 4 4 2 2 2 3 Ratio 4 3 2 3 4 3 2 4 5 5 3 4 4 3 2 4 4 3 2 3 4 3 2 4 5 5 3 4 4 3 2 4 Ratio 5 5 5 6 5 5 5 8 6 8 8 8 5 5 5 8 3 3 3 4 3 3 3 5 4 5 5 5 3 3 3 5 Ratio 6 6 6 8 6 6 6 10 8 10 10 10 6 6 6 9 6 6 6 8 6 6 6 10 8 10 10 10 6 6 6 9 Ratio 12 12 12 16 12 12 12 20 16 20 20 20 12 12 12 18 12 12 12 16 12 12 12 20 16 20 20 20 12 12 12 18 - 13 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 8. ACCESS INTERFACE The W83194BR-648 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-648 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write Protocol 8.4 Byte Read Protocol - 14 - W83194BR-648 9. SPECIFICATIONS 9.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER RATING Absolute 3.3V Core Supply Voltage -0.5V to +4.6V Absolute 3.3V I/O Supple Voltage -0.5 V to +4.6 V Operating 3.3V Core Supply Voltage 3.135V to 3.465V Operating 3.3V I/O Supple Voltage 3.135V to 3.465V Storage Temperature -65°C to +150°C Ambient Temperature -55°C to +125°C Operating Temperature 0°C to +70°C Input ESD Protection (Human body model) 2000V 9.2 General Operating Characteristics VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V ± 5 %, TA = 0°C to +70°C, Cl = 10pF PARAMETER SYM. Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH MIN. MAX. UNITS 0.8 Vdc 2.0 Vdc 0.4 2.4 Vdc All outputs using 3.3V power Vdc All outputs using 3.3V power Dynamic Supply Current Idd 350 mA Input Pin Capacitance Cin 5 pF Output Pin Capacitance Cout 6 pF Lin 7 nH Input Pin Inductance TEST CONDITIONS - 15 - CPU = 100 to 200 MHz PCI = 33.3 MHz with load Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 9.3 Skew Group Timing Clock VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V ±5 %, TA = 0°C to +70°C, Cl = 10pF PARAMETER MIN. TYP. MAX. UNITS TEST CONDITIONS CPU to SDRAM Skew -2 0 2 nS CPU Crossing point to SDRAM at 1.5V CPU (early) to AGP Skew 1 2 4 nS CPU Crossing point to AGP at 1.5V CPU (early) to ZCLK Skew 1 2 4 nS CPU Crossing point to ZCLK at 1.5V CPU (early) to PCI Skew 1 2 4 nS CPU Crossing point to PCI at 1.5V CPU to CPU Skew 150 pS Crossing point AGP to AGP Skew 175 pS Measured at 1.5V ZCLK to ZCLK Skew 175 pS Measured at 1.5V PCI to PCI Skew 500 pS Measured at 1.5V 48 MHz to 48 MHz Skew 1000 pS Measured at 1.5V REF to REF Skew 500 pS Measured at 1.5V 9.4 CPU 0.7V Electrical Characteristics VDDA = VDDC= 3.3V ±5 %, TA = 0°C to +70°C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475, IRE = 2.32mA, Ioh = 6*IREF PARAMETER MIN. MAX. UNITS Rise Time 175 700 pS 100 to 200 MHz Fall Time 175 700 pS 100 to 200 MHz Absolute Crossing Point Voltages 250 550 mV 100 to 200 MHz 125 pS 100 to 200 MHz 55 % 100 to 200 MHz Cycle to Cycle jitter Duty Cycle 45 TEST CONDITIONS 9.5 CPU 1.0V Electrical Characteristics VDDA = VDDC= 3.3V ±5 %, TA = 0°C to +70°C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.2V, Voh = 0.8V, Vr = 221, IREF = 5.0 mA, Ioh = 4*IREF PARAMETER MIN. MAX. UNITS Rise Time 300 600 pS 100 to 200 MHz Fall Time 300 600 pS 100 to 200 MHz Absolute Crossing Point Voltages 510 760 mV 100 to 200 MHz 200 pS 100 to 200 MHz 55 % 100 to 200 MHz Cycle to Cycle Jitter Duty Cycle 45 - 16 - TEST CONDITIONS W83194BR-648 9.6 AGP Electrical Characteristics VDDAGP= 3.3V ±5 %, TA = 0°C to +70°C, Test load, C = 10pF, PARAMETER MIN. MAX. UNITS Rise Time 500 1600 pS Measure from 0.4V to 2.4V Fall Time 500 1600 pS Measure from 2.4V to 0.4V 250 pS Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. -33 30 Pull-Down Current Max. 38 TEST CONDITIONS mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V 9.7 PCI Electrical Characteristics VDDPCI = 3.3V ±5 %, TA = 0°C to +70°C, Test load, Cl = 10pF PARAMETER MIN. MAX. UNITS Rise Time 500 2000 pS Measure from 0.4V to 2.4V Fall Time 500 2000 pS Measure from 2.4V to 0.4V 500 pS Measure 1.5V point Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. 55 -33 30 Pull-Down Current Max. 38 TEST CONDITIONS % mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V 9.8 ZCLK Electrical Characteristics VDDZ = 3.3V ±5 %, TA = 0°C to +70°C, Test load, Cl = 10pF MIN. MAX. UNITS Rise Time PARAMETER 500 1600 pS Measure from 0.4V to 2.4V Fall Time 500 1600 pS Measure from 2.4V to 0.4V 250 pS Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. mA -33 30 38 TEST CONDITIONS Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V - 17 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 9.9 SDRAM Electrical Characteristics VDDSD= 3.3V ±5 %, TA = 0°C to +70°C, Test load, Cl = 10pF PARAMETER MIN. MAX. UNITS Rise Time 500 1600 pS Measure from 0.4V to 2.4V Fall Time 500 1600 pS Measure from 2.4V to 0.4V 250 pS Measure 1.5V point 55 % mA Vout = 1.0V -33 mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. 30 Pull-Down Current Max. 38 TEST CONDITIONS 9.10 24M, 48M Electrical Characteristics VDD48 = 3.3V ±5 %, TA = 0°C to +70°C, Test load, Cl = 10pF MIN. MAX. UNITS Rise Time PARAMETER 1000 4000 pS Measure from 0.4V to 2.4V Fall Time 1000 4000 pS Measure from 2.4V to 0.4V 500 pS Measure 1.5V point Long Term Jitter Duty Cycle 45 Pull-Up Current Min. -29 Pull-Up Current Max. Pull-Down Current Min. 55 % -23 29 Pull-Down Current Max. TEST CONDITIONS 27 mA Vout = 1.0V mA Vout = 3.135V mA Vout = 1.95V mA Vout = 0.4V 9.11 REF Electrical Characteristics VDD48 = 3.3V ±5 %, TA = 0°C to +70°C, Test load, Cl = 10pF PARAMETER MIN. MAX. UNITS Rise Time 1000 4000 ps Measure from 0.4V to 2.4V Fall Time 1000 4000 ps Measure from 2.4V to 0.4V 1000 ps Measure 1.5V point 55 % Cycle to Cycle Jitter Duty Cycle 45 Pull-Up Current Min. -33 Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. TEST CONDITIONS mA Vout=1.0V -33 mA Vout=3.135V mA Vout=1.95V 38 mA Vout=0.4V 30 - 18 - W83194BR-648 10. POWER MANAGEMENT TIMING 10.1 CPU_STOP# Timing Diagram CPUCLK (Internal) 1 2 3 4 1 2 3 4 PCICLK (Internal) PCICLK_F CPU_STOP# CPUCLK[0:3] SDRAM For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU locks on latency“ is less than 4 CPU clocks and locks off latency” is less then 4 CPU clocks. 10.2 PCI_STOP# Timing Diagram CPUCLK (Internal) PCICLK (Internal) 1 2 1 2 PCICLK_F PCI_STOP# PCICLK[0:5] For synchronous Chipset, PCI_STOP# pin is an asynchronous Active low” input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI locks on latency“ is less than 2 PCI clocks and locks off latency” is less then 2 PCI clocks. - 19 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 11. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83194BR-648 48-pin SSOP Commercial, 0°C to +70°C 12. HOW TO READ THE TOP MARKING Version A W83194BR-648 28051234 342GCA Version B W83194BR-648 28051234 342GCB 1st line: Winbond logo and the type number: W83194BR-648 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G C A 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR C: Internal use code A: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 20 - W83194BR-648 13. PACKAGE DRAWING AND DIMENSIONS - 21 - Publication Release Date: April 13, 2005 Revision 1.1 W83194BR-648 14. REVISION HISTORY VERSION DATE PAGE DESCRIPTION n.a. All of the versions before 0.50 are for internal use. Add AC/DC Specifications and Power management 0.5 02/7/03 17~22 0.6 2/21/03 All 0.7 12/18/03 7~11, 19 1.0 05/06/04 1.1 04/13/2005 Update new form Correction IC version, add register default value and correction some description and default value Update on web 22 Add disclaimer Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 22 -