AKM AKD4373

[AK4373]
AK4373
Low Power Stereo DAC with HP/SPK-Amp
GENERAL DESCRIPTION
The AK4373 is a low power stereo 24bit DAC with an integrated stereo headphone amplifier and a
monaural speaker driver. It can be used for a variety of portable audio and media player applications,
including game consoles, dedicated headphone drivers, personal navigation devices, and portable media
players. The output drivers can be configured for three unique use cases: mono speaker driver or
single-ended ac-coupled headphones which can be used as stereo line-out, DC-coupled BTL
headphones and Pseudo Cap-less. The AK4373 operates off of a low-voltage power supply, ranging from
2.2V to 3.6V. The output amplifiers operate at up to 4.0V of the headphone power supply. The device is
packaged in a space-saving 32-pin QFN package.
FEATURES
† Sampling Rate: 8 kHz ∼ 48 kHz
† 8-times Over sampling Digital Filter
† SCF with high tolerance to clock jitter
† Stereo Headphone Amplifier
65mW output (Single-ended mode) into 16Ω 3.3V
SNR: 96dB
130mW output (Differential mode) into 32Ω 3.3V
SNR: 96dB
60mW output (Pseudo cap-less mode) into 16Ω 3.3V
SNR: 86dB
Pop-noise free at power-up and reset
† Stereo Lineout
SNR: 96dB
† Mono Speaker Driver
Available for both Dynamic and Piezo Speaker
0.8W @ 8Ω HVDD = 4.0V
1.0W @ 4Ω HVDD = 4.0V
SNR: 97dB
† Digital Processing
HPF, LPF, 3D Enhance, Frequency Compensation, 5-BiQuads,
Digital ALC/Limiter: +36dB to -54dB, 0.375dB/step
† Digital Volume Control: +12dB to -115dB, 0.5dB/step, Mute
† Analog Mixing: Mono input
† PLL: Input Frequency: 27MHz, 25MHz, 24MHz, 13.5MHz, 12.288MHz,
12MHz, and 11.2896MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
Input Level: CMOS or AC coupling Input
† Master Clock (MCKI pin): 256/512/1024fs
† Master Clock Output (MCKO pin): 32fs, 64fs, 128fs, 256fs
2
† µP Interface: 3-Wire serial, I C bus (version1.0, 400 KHz Fast-mode)
† Audio Interface Format: MSB First, 2’s complement
16/20/24bit MSB justified, 16/20/24bit LSB justified,
16/20/24bit I2S, 16/20/24bit DSP Mode
† CMOS Input Level
MS0991-E-00
2008/09
-1-
[AK4373]
† Power Supply:
Analog (AVDD): 2.2 to 3.6V
Digital (DVDD): 1.6 to 3.6V
Driver (HVDD): 2.2 to 4.0V
† Power Consumption:
11.9mW headphone playback
† Ta = -30 ~ +85°C
† Package: 32-pin QFN (5mm x 5mm, 0.5mm pitch)
† Pin/Register compatible with AK4343
■ Block Diagram
AVDD VSS1
DVDD
VCOM
VSS3
I2C
LOUT
CAD0/CSN
Control
Register
Stereo Line Out
ROUT
HPL
Headphone
HPR
SCL/CCLK
SDA/CDTI
PMHPL
HPG
VOL
PMHPR
HPG
VOL
PMDAC
PDN
DACH
Digital
Processing
BICK
- HPF
D/A
DACH
MUTET
DATT - LPF
SMUTE - 3D Enhance
Audio
I/F
- Frequency
Compensation
- 5-BiQuads
- ALC/Limiter
LRCK
SDTI
MCKO
PLL
MCKI
VCOC
SPP
Speaker
SPN
SPKG[1:0]
VOL
DACS
PMPLL
PMSPK
MINS
MINH
MIN+
Mono In
MINPMMIN
HVDD VSS2
Figure 1. Block Diagram (Single-ended mode, HPBTL bit =PSEUDO bit = “0”)
MS0991-E-00
2008/09
-2-
[AK4373]
AVDD VSS1
DVDD
VCOM
VSS3
I2C
CAD0/CSN
Control
Register
SCL/CCLK
SDA/CDTI
Headphone(Lch)
PMDAC
PMHPL
HPL+
HPG
VOL
HPL-
DACH
- HPF
D/A
HPR+
HPG
VOL
HPR-
PDN
Digital
Processing
DACH
DATT - LPF
SMUTE - 3D Enhance
BICK
Audio
I/F
- Frequency
Compensation
- 5-BiQuads
- ALC/Limiter
LRCK
SDTI
PMHPR
Headphone(Rch)
MCKO
MUTET
PLL
MCKI
VCOC
MINH
PMPLL
MIN+
Mono In
MINPMMIN
HVDD VSS2
Figure 2. Block Diagram (Differential mode, HPBTL bit = “1”, PSEUDO bit = “0”)
AVDD VSS1
DVDD
VCOM
VSS3
I2C
CAD0/CSN
Control
Register
SCL/CCLK
SDA/CDTI
PMDAC
PMHPL
HPG
VOL
HPL
Headphone
HPR
PMHPR
HPG
VOL
PDN
DACH
Digital
Processing
BICK
- HPF
D/A
DACH
MUTET
DATT - LPF
SMUTE - 3D Enhance
Audio
I/F
- Frequency
Compensation
- 5-BiQuads
- ALC/Limiter
LRCK
SDTI
MCKO
PLL
PMHPL or PMHPR
MCKI
VCOC
HVCM
PMPLL
COMMON
TEST
MINH
MIN+
Mono In
MINPMMIN
HVDD VSS2
Figure 3. Block Diagram (Pseudo cap-less mode, HPBTL bit = “0”, PSEUDO bit = “1”)
MS0991-E-00
2008/09
-3-
[AK4373]
■ Ordering Guide
−30 ∼ +85°C
32pin QFN (0.5mm pitch)
Evaluation board for AK4373
AK4373EN
AKD4373
HPL / HPL+
HPR / HPL-
VSS2
HVDD
SPP / HPR+ / TEST
SPN / HPR- / HVCM
MCKO
MCKI
24
23
22
21
20
19
18
17
■ Pin Layout
LRCK
MIN-
29
Top View
12
NC
NC
30
11
SDTI
NC
31
10
CDTI / SDA
NC
32
9
CCLK / SCL
8
13
CSN / CAD0
AK4373EN
7
28
PDN
MIN+
6
BICK
I2C
14
5
27
VCOC
LOUT
4
DVDD
AVDD
15
3
26
VSS1
ROUT
2
VSS3
VCOM
16
1
25
NC
MUTET
MS0991-E-00
2008/09
-4-
[AK4373]
■ Comparison table between AK4343 and AK4373
1. Function
Function
DAC Resolution
HP-Amp S/N
HP-Amp Output Type
Single-ended
Five Programmable Biquads
Line Output Pins
MCKI Input Level
Analog Mixing
Receiver Amp
SPK AMP
No
Independent from HP/SPK
CMOS
3-Stereo
Yes
[email protected], 5V
AK4373
24bit
96dB(single), 96dB(BTL)
Single-ended, Differential
or Pseudo cap-less
Yes
Shared with HPL/HPR
CMOS or 0.4Vpp AC coupling
1-Mono (Single/Differential)
No
[email protected], 4.0V
AK4343
TEST1
AVSS
VCOC / RIN3
TEST2
DVSS
SPN
SPP
HVSS
HPR
HPL
MIN / LIN3
RIN2 / IN2−
LIN2 / IN2+
LIN1 / IN1−
RIN1 / IN1+
AK4373
NC
VSS1
VCOC
NC
VSS3
SPN / HPR− / HVCM
SPP / HPR+ / TEST
VSS2
HPR / HPL−
HPL / HPL+
MIN+
MINNC
NC
NC
2. Pin
Pin#
1
3
5
12
16
19
20
22
23
24
28
29
30
31
32
AK4343
16bit
90dB
MS0991-E-00
2008/09
-5-
[AK4373]
3. Register
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select 1
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
0
0
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
AVL7
DVL7
RGAIN1
AVR7
DVR7
0
0
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
0
0
0
0
0
0
0
0
0
0
0
0
F2A7
0
F2B7
0
D6
PMVCM
D5
PMMIN
PMHPL
DACS
D4
PMSPK
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
AVL4
DVL4
0
AVR4
DVR4
DVOLC
0
MDIF2
HPF
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
HPBTL
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
AVL3
DVL3
0
AVR3
DVR3
BST1
AVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
HPMTN
MINS
MGAIN1
LOPS
PLL2
PLL1
PS0
FS3
WTM2
ZTM1
0
ALC
REF6
REF5
AVL6
AVL5
DVL6
DVL5
LMTH1
0
AVR6
AVR5
DVR6
DVR5
0
SMUTE
0
0
INL1
HPG
GN0
LPF
F3A6
F3A5
0
F3A13
F3B6
F3B5
0
F3B13
EQA6
EQA5
EQA14
EQA13
EQB6
EQB5
0
EQB13
EQC6
EQC5
EQC14
EQC13
F1A6
F1A5
0
F1A13
F1B6
F1B5
0
F1B13
PMAINR3
PMAINL3
PMAINR2
0
0
MICR3
MICL3
0
0
0
0
RINR3
0
0
0
RINH3
0
0
0
RINS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F2A6
F2A5
F2A4
F2A3
0
F2A13
F2A12
F2A11
F2B6
F2B5
F2B4
F2B3
0
F2B13
F2B12
F2B11
These bits were added to the AK4373.
These bits were removed from the AK4343.
These bits name were changed.
MS0991-E-00
D2
PMDAC
MCKAC
PMMP
MINL
DIF2
FS2
WTM0
LMAT0
REF2
AVL2
DVL2
FRN
AVR2
DVR2
BST0
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
D0
0
PMPLL
PSEUDO
MGAIN0
0
DIF1
FS1
RFST1
RGAIN0
REF1
AVL1
DVL1
VBAT
AVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
DIF0
FS0
RFST0
LMTH0
REF0
AVL0
DVL0
0
AVR0
DVR0
DEM0
DACH
0
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINL2
PMMICR
PMMICL
0
LINL3
LINH3
LINS3
0
0
0
0
0
0
0
F2A2
F2A10
F2B2
F2B10
AIN3
RINR2
RINH2
RINS2
0
0
0
0
0
0
0
F2A1
F2A9
F2B1
F2B9
RCV
LINL2
LINH2
LINS2
0
0
0
0
0
0
0
F2A0
F2A8
F2B0
F2B8
2008/09
-6-
[AK4373]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
D5
D4
D3
0
0
EQ5
EQ4
0
0
0
0
E1A6
E1A5
E1A4
E1A3
E1A14
E1A13
E1A12
E1A11
E1B6
E1B5
E1B4
E1B3
E1B14
E1B13
E1B12
E1B11
E1C6
E1C5
E1C4
E1C3
E1C14
E1C13
E1C12
E1C11
E2A6
E2A5
E2A4
E2A3
E2A14
E2A13
E2A12
E2A11
E2B6
E2B5
E2B4
E2B3
E2B14
E2B13
E2B12
E2B11
E2C6
E2C5
E2C4
E2C3
E2C14
E2C13
E2C12
E2C11
E3A6
E3A5
E3A4
E3A3
E3A14
E3A13
E3A12
E3A11
E3B6
E3B5
E3B4
E3B3
E3B14
E3B13
E3B12
E3B11
E3C6
E3C5
E3C4
E3C3
E3C14
E3C13
E3C12
E3C11
E4A6
E4A5
E4A4
E4A3
E4A14
E4A13
E4A12
E4A11
E4B6
E4B5
E4B4
E4B3
E4B14
E4B13
E4B12
E4B11
E4C6
E4C5
E4C4
E4C3
E4C14
E4C13
E4C12
E4C11
E5A6
E5A5
E5A4
E5A3
E5A14
E5A13
E5A12
E5A11
E5B6
E5B5
E5B4
E5B3
E5B14
E5B13
E5B12
E5B11
E5C6
E5C5
E5C4
E5C3
E5C14
E5C13
E5C12
E5C11
These bits were added to the AK4373.
These bits were removed from the AK4343.
MS0991-E-00
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
2008/09
-7-
[AK4373]
PIN/FUNCTION
No.
Pin Name
I/O
1
NC
-
2
VCOM
O
3
4
VSS1
AVDD
-
5
VCOC
O
6
I2C
I
7
PDN
I
11
CSN
CAD0
CCLK
SCL
CDTI
SDA
SDTI
12
NC
13
14
15
16
17
18
LRCK
BICK
DVDD
VSS3
MCKI
MCKO
8
9
10
I
I
I
I
I
I/O
I
I/O
I/O
I
O
Function
No Connect Pin
No internal bonding. This pin should be open or connected to the ground.
Common Voltage Output Pin, 0.5 x AVDD
Bias voltage of DAC outputs.
Analog Ground Pin
Analog Power Supply Pin 2.2 ∼ 3.6V
Output Pin for Loop Filter of PLL Circuit
This pin must be connected to VSS1 with one resistor and capacitor in series.
Control Mode Select Pin
“H”: I2C Bus, “L”: 3-wire Serial
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initialization of the control register.
The AK4373 must be reset once upon power-up.
Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode)
Chip Address 1 Select Pin (I2C pin = “H”: I2C Bus Mode)
Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode)
Control Data Clock Pin (I2C pin = “H”: I2C Bus Mode)
Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode)
Control Data Input Pin (I2C pin = “H”: I2C Bus Mode)
Audio Serial Data Input Pin
No Connect Pin
No internal bonding. This pin should be open or connected to the ground.
Input / Output Channel Clock Pin
Audio Serial Data Clock Pin
Digital Power Supply Pin. 1.6 ∼ 3.6V
Digital Ground Pin
External Master Clock Input Pin
Master Clock Output Pin
MS0991-E-00
2008/09
-8-
[AK4373]
No.
Pin Name
I/O
Function
Speaker Amp Negative Output Pin
Single-ended mode (HPBTL bit = PSEUDO bit = “0”)
Rch Headphone-Amp Negative Output Pin
19 HPR−
O
Differential mode (HPBTL bit = “1”, PSEUDO bit = “0”)
Common Output Voltage for Headphone-Amp Pin
HVCM
O
Pseudo cap-less mode (HPBTL bit = “0”, PSEUDO bit = “1”)
Speaker Amp Positive Output Pin
SPP
O
Single-ended mode (HPBTL bit = PSEUDO bit = “0”)
Rch Headphone-Amp Positive Output Pin
20 HPR+
O
Differential mode (HPBTL bit = “1”, PSEUDO bit = “0”)
This pin must be open.
TEST
O
Pseudo cap-less mode (HPBTL bit = “0”, PSEUDO bit = “1”)
21 HVDD
Headphone & Speaker Amp Power Supply Pin. 2.2 ∼ 4.0V
22 VSS2
Headphone & Speaker Amp Ground Pin
Rch Headphone-Amp Output Pin
HPR
O
Single-ended mode (HPBTL bit = PSEUDO bit = “0”)
Pseudo cap-less mode (HPBTL bit = “0”, PSEUDO bit = “1”)
23
Lch Headphone-Amp Negative Output Pin
O
HPL−
Differential mode (HPBTL bit = “1”, PSEUDO bit = “0”)
Lch Headphone-Amp Output Pin
HPL
O
Single-ended mode (HPBTL bit = PSEUDO bit = “0”)
24
Pseudo cap-less mode (HPBTL bit = “0”, PSEUDO bit = “1”)
Lch Headphone-Amp Positive Output Pin
HPL+
O
Differential mode (HPBTL bit = “1”, PSEUDO bit = “0”)
Mute Time Constant Control Pin
25 MUTET
O
Connected to the VSS2 pin with a capacitor for mute time constant.
Rch Line Output Pin
26 ROUT
O
This pin is internal connected to the HPR pin.
Lch Line Output Pin
27 LOUT
O
This pin is internal connected to the HPL pin.
Mono Signal Positive Input (Differential Input) or Mono Signal Input (Single-ended
28 MIN+
I
Input)
Mono Signal Negative Input (Differential Input)
29 MINI
If the MIN+ pin is used as single-ended, this pin should be connected to the VSS1
with a capacitor.
No Connect Pin
30 NC
No internal bonding. This pin should be open or connected to the ground.
No Connect Pin
31 NC
No internal bonding. This pin should be open or connected to the ground.
No Connect Pin
32 NC
No internal bonding. This pin should be open or connected to the ground.
Note 1. All input pins must not be left floating.
Note 2. DVDD or VSS3 voltage must be input to I2C pin.
Note 3. All analog input pins (MIN+/- pins) must be supplied signal via AC-coupling capacitor.
Note 4. Analog output pins (HPL, HPR, LOUT, and ROUT pins) must deliver signal via AC-coupling capacitor except
speaker output (SPP, SPN pins) and headphone output in Differential mode (HPL+/- and HPR+/- pins) and
headphone output in Pseudo cap-less mode (HPL and HPR pins).
SPN
O
MS0991-E-00
2008/09
-9-
[AK4373]
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Analog
Digital
Pin Name
VCOC, SPN/HPR−/HVCM, SPP/HPR+/TEST,
HPR/HPL-, HPL/HPL+, MIN+, MIN-, MUTET
MCKO
MCKI
Setting
These pins must be open.
This pin must be open.
This pin must be connected to VSS3.
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=0V; Note 5)
Parameter
Power Supplies:
Analog
Digital
Headphone-Amp / Speaker-Amp
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 7)
Digital Input Voltage (Note 8)
Ambient Temperature (powered applied)
Storage Temperature
Maximum Power Dissipation
(Note 9)
Symbol
AVDD
DVDD
HVDD
IIN
VINA
VIND
Ta
Tstg
Pd
min
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
-
max
4.6
4.6
4.6
±10
(AVDD+0.3) or 4.6
(DVDD+0.3) or 4.6
85
150
511
Units
V
V
V
mA
V
V
°C
°C
mW
Note 5. All voltages are with respect to ground.
Note 6. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 7. I2C, MIN+, MIN- pin
Note 8. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins
Pull-up resistors at SDA and SCL pins must be connected to (DVDD+0.3)V or less voltage.
Note 9. In case that the exposed pad is connected to the ground and PCB drawing density is 100%.This power is the
AK4373 internal dissipation that does not include power of externally connected speaker and headphone.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=0V; Note 5)
Parameter
Symbol
min
typ
Power Supplies Analog
AVDD
2.2
3.3
(Note 10) Digital
DVDD
1.6
3.3
HP / SPK-Amp
HVDD
2.2
3.3
Difference1
DVDD – AVDD
Difference2
DVDD – HVDD
-
max
3.6
3.6
4.0
+0.3
+0.3
Units
V
V
V
V
V
Note 5. All voltages are with respect to ground.
Note 10. The power-up sequence between AVDD, DVDD and HVDD is not critical. When only AVDD or HVDD is
powered OFF, the power supply current of DVDD at power-down mode may be increased. DVDD must not be
powered OFF while AVDD or HVDD is powered ON.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0991-E-00
2008/09
- 10 -
[AK4373]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=HVDD=3.3V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
DAC Characteristics:
Resolution
24
Bits
Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, Single-ended mode (Figure 4), HPBTL bit = “0”,
PSEUDO bit = “0”, HPG bit = “0”, HVDD=3.3V, C=1µF, RL=10kΩ, ALC=OFF,
AVOL=0dB, DVOL=0dB; unless otherwise specified.
Output Voltage (0dBFS) (Note 11)
1.78
1.98
2.18
Vpp
S/(N+D) (0dBFS)
77
dB
S/N (A-weighted)
86
96
dB
Interchannel Isolation
60
80
dB
Load Resistance
RL
10
kΩ
Load Capacitance
C1
30
pF
Note 11. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Line-Amp
LOUT/ROUT
pin
C
Measurement
Point
RL
C1
Figure 4. Line-Amp output circuit
Parameter
min
typ
max
Units
Headphone-Amp Characteristics: DAC → HPL/HPR pins, Single-ended mode (Figure 5), HPBTL bit = “0”,
PSEUDO bit = “0”, HPG bit = “0”, HVDD=3.3V, C=47µF, RL=22.8Ω, ALC=OFF,
AVOL=0dB, DVOL=0dB; unless otherwise specified.
Output Voltage (Note 12)
0dBFS
1.58
1.98
2.38
Vpp
0dBFS (Note 13)
3.00
Vpp
0dBFS (Note 14)
1.02
Vrms
S/(N+D)
50
60
dB
−3dBFS
65
dB
−3dBFS (Note 13)
0dBFS (Note 14)
20
dB
86
96
dB
S/N (A-weighted)
96
dB
(Note 13)
Interchannel Isolation
60
75
dB
Interchannel Gain Mismatch
0
0.8
dB
Load Resistance
RL=R1+R2
16
Ω
Load Capacitance
C1
30
pF
C2
300
pF
Note 12. Output voltage is proportional to AVDD voltage.
Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.
Note 13. HPG bit = “1”, HVDD=3.8V, C=47µF, RL=100Ω.
Note 14. HPG bit = “1”, HVDD=3.3V, C=47µF, RL=16Ω.
MS0991-E-00
2008/09
- 11 -
[AK4373]
HP-Amp
HPL/HPR
pin
C
Measurement
Point
R1
C1
C2
R2
Figure 5. HP-Amp Output Circuit in single-ended mode
Parameter
min
typ
Headphone-Amp Characteristics: DAC → HPL+/-, HPR+/- pins, Differential mode(Figure
PSEUDO bit = “0” , HPG bit = “0”, HVDD=3.3V,
AVOL=0dB, DVOL=0dB; unless otherwise specified.
Output Voltage (Note 15)
0dBFS
3.96
0dBFS (Note 16)
2.05
S/(N+D)
60
−3dBFS
0dBFS (Note 16)
20
S/N (A-weighted)
96
Interchannel Isolation
75
Interchannel Gain Mismatch
0.2
Load Resistance
RL =2 x R1 + R2
16
Load Capacitance
C1
C2
-
max
Units
6), HPBTL bit = “1”,
RL=32Ω, ALC=OFF,
30
300
Vpp
Vrms
dB
dB
dB
dB
dB
Ω
pF
pF
Note 15. Output voltage is proportional to AVDD voltage.
Vout = 1.2 x AVDD(typ)@HPG bit = “0”, 1.82 x AVDD(typ)@HPG bit = “1”.
Note 16. HPG bit = “1”, HVDD=3.3V, RL=32Ω.
HP-Amp
HPL+/HPR+
pin
R1
C1
C2
R2
Measurement
Point
HP-Amp
HPL-/HPRpin
C1
R1
C2
Figure 6. HP-Amp Output Circuit in differential mode
MS0991-E-00
2008/09
- 12 -
[AK4373]
Parameter
min
typ
max
Units
Headphone-Amp Characteristics: DAC → HPL/HPR pins, Pseudo cap-less mode(Figure 7), HPBTL bit = “0”,
PSEUDO bit = “1” , HPG bit = “0”, HVDD=3.3V, RL=22.8Ω, ALC=OFF,
AVOL=0dB, DVOL=0dB; unless otherwise specified.
Output Voltage (Note 17)
0dBFS
1.98
Vpp
0dBFS (Note 18)
0.98
Vrms
S/(N+D)
38
dB
−3dBFS
0dBFS (Note 18)
20
dB
S/N (A-weighted)
86
dB
Interchannel Isolation
38
dB
Interchannel Gain Mismatch
0
dB
Load Resistance
RL = R1 + R2
16
Ω
Load Capacitance
C1
30
pF
C2
300
pF
Note 17. Output voltage is proportional to AVDD voltage.
Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.
Note 18. HPG bit = “1”, HVDD=3.3V, RL=16Ω.
HP-Amp
HPL/HPR
pin
R1
C1
C2
Measurement
Point
VCOM Amp for
HP-Amp
R2
HVCM pin
C1
Note: Impedance between headphone and the HVCM pin must be as low as possible. If the impedance is
larger, crosstalk and distortion might be degraded.
Figure 7. HP-Amp Output Circuit in pseudo cap-less mode
MS0991-E-00
2008/09
- 13 -
[AK4373]
Parameter
min
typ
max
Units
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 19)
3.11
Vpp
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
3.13
3.92
4.71
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
2.04
Vrms
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/(N+D)
50
dB
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
20
50
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
20
dB
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/N (A-weighted)
87
97
dB
Load Resistance
8
Ω
Load Capacitance
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, CL=3μF,
Rseries=20Ω x 2, BTL, HVDD=3.8V; unless otherwise specified. (Figure 53)
Output Voltage
SPKG1-0 bits = “10”, -0.5dBFS
6.37
Vpp
(Note 19)
S/(N+D)
SPKG1-0 bits = “10”, -0.5dBFS
58
dB
(Note 20)
S/N (A-weighted)
97
dB
Load Resistance (Note 21)
50
Ω
Load Capacitance (Note 21)
3
μF
Mono Input: MIN+ pin (External Input Resistance=20kΩ) Single-ended Input MIN- pin is connected to VSS1 via input
capacitor.
Maximum Input Voltage (Note 22)
1.98
Vpp
Gain (Note 23)
HPBTL bit = “0”
MIN+ Æ HPL/HPR
0
dB
HPG bit = “0”
HPBTL bit = “0”
MIN+ Æ HPL/HPR
+3.6
dB
HPG bit = “1”
HPBTL bit = “1”
MIN+ Æ HPL+/-, HPR+/+6
dB
HPG bit = “0”
HPBTL bit = “1”
MIN+ Æ HPL+/-, HPR+/+9.6
dB
HPG bit = “1”
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
-0.07
+4.43
+8.93
dB
ALC bit = “0”, SPKG1-0 bits = “01”
+6.43
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+10.65
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+12.65
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+6.43
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+8.43
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+12.65
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+14.65
dB
MS0991-E-00
2008/09
- 14 -
[AK4373]
Mono Input: MIN+/MIN- pins (External Input Resistance=20kΩ) Differential Input
Maximum Input Voltage (Note 24)
1.98
Gain (Note 23)
HPBTL bit = “0”
MIN+/- Æ HPL/HPR
0
HPG bit = “0”
HPBTL bit = “0”
MIN+/- Æ HPL/HPR
+3.6
HPG bit = “1”
HPBTL bit = “1”
MIN+/- Æ HPL+/-, HPR+/+6
HPG bit = “0”
HPBTL bit = “1”
MIN+/- Æ HPL+/-, HPR+/+9.6
HPG bit = “1”
MIN+/MIN- Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
-0.07
+4.43
ALC bit = “0”, SPKG1-0 bits = “01”
+6.43
ALC bit = “0”, SPKG1-0 bits = “10”
+10.65
ALC bit = “0”, SPKG1-0 bits = “11”
+12.65
ALC bit = “1”, SPKG1-0 bits = “00”
+6.43
ALC bit = “1”, SPKG1-0 bits = “01”
+8.43
ALC bit = “1”, SPKG1-0 bits = “10”
+12.65
ALC bit = “1”, SPKG1-0 bits = “11”
+14.65
-
Vpp
-
dB
-
dB
-
dB
-
dB
+8.93
-
dB
dB
dB
dB
dB
dB
dB
dB
Note 19. Output voltage is proportional to AVDD voltage.
Vout = 1.00 x AVDD(typ)@SPKG1-0 bits = “00”, 1.25 x AVDD(typ)@SPKG1-0 bits = “01”, 2.04 x
AVDD(typ)@SPKG1-0 bits = “10”, 2.57 x AVDD(typ)@SPKG1-0 bits = “11” at Differential output.
Note 20. In case of measuring at SPP and SPN pins.
Note 21. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in Figure
56. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 20Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Note 22. Maximum voltage is in proportion to both AVDD and external input resistance (Rin).
Vin = 0.6 x AVDD x 20kΩ (typ)/Rin.
Note 23. The gain is in inverse proportional to external resistance.
Note 24. The Maximum voltage is in proportion to both AVDD and external input resistance (Rin).
Vin = (MIN+) – (MIN-) = 0.6 x AVDD x 20kΩ (typ)/Rin.
The signals with same amplitude and inverted phase should be input to MIN+ and MIN- pins, respectively.
MS0991-E-00
2008/09
- 15 -
[AK4373]
Parameter
min
typ
max
Units
Power Supplies:
Power-Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD (Note 25)
7.8
mA
AVDD+DVDD (Note 26)
8.1
12
mA
HVDD: HP-Amp Normal Operation
2.2
4
mA
No Output (Note 27)
HVDD: SPK-Amp Normal Operation
4.1
12
mA
No Output (Note 28)
Power-Down (PDN pin = “L”) (Note 29)
AVDD+DVDD+HVDD
1
20
μA
Note 25. PLL Master Mode (MCKI=12.288MHz) and PMDAC = PMHPL = PMHPR = PMVCM = PMPLL = MCKO =
M/S bits = “1”, PMMIN bit = “0”.
AVDD=3.9mA(typ), DVDD=3.9mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=3.1mA(typ), DVDD=2.7mA(typ).
Note 26. PLL Master Mode (MCKI=12.288MHz) and PMDAC = PMHPL = PMHPR = PMVCM = PMPLL = MCKO =
M/S bits = “1”, PMMIN bit = “1”.
AVDD=4.2mA(typ), DVDD=3.9mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=3.5mA(typ), DVDD=2.7mA(typ).
Note 27. PMDAC = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1” and PMSPK bit = “0”.
Note 28. PMDAC = PMSPK = PMVCM = PMPLL = PMMIN bits = “1” and PMHPL = PMHPR bits = “0”.
Note 29. All digital input pins are fixed to DVDD or VSS3.
■ Power Consumption for each operation mode
Common Conditions: Ta=25°C; VSS1=VSS2=VSS3=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS
input; (PMMIN bit = “0” )Headphone & Speaker = No output
Power Management Bit
00H
01H
DAC Æ SPK
PMMIN
PMSPK
PMDAC
PMHPL
PMHPR
All Power-down
DAC Æ
HP/Line Out
PMVCM
Mode
Typical Current
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
AVDD
DVDD
Total Power
HVDD
[V]
[mA]
[V]
[mA]
[V]
[mA]
[mW]
3.3
0
3.3
0
2.2
2.7
1.8
1.0
3.3
3.1
3.3
2.7
2.2
2.7
1.8
1.0
3.3
3.2
3.3
2.7
3.3
2.2
4.0
3.3
2.2
4.0
3.3
0
1.9
2.6
2.2
4.2
5.2
4.1
0
11.9
18.1
26.4
17.0
28.5
33.0
Table 1. Power Consumption for each operation mode (typ)
MS0991-E-00
2008/09
- 16 -
[AK4373]
FILTER CHARACTERISTICS
(Ta=-30 ~ 85°C; AVDD=2.2 ∼ 3.6V, DVDD=1.6 ∼ 3.6V; HVDD=2.2 ∼ 4.0V; fs=44.1kHz; DEM=OFF;
HPF=LPF=FIL3=EQ=5-BiQuads=ALC=OFF)
Parameter
Symbol
min
typ
max
DAC Digital Filter (LPF):
Passband (Note 30)
-0.05dB
PB
0
20.0
22.05
−6.0dB
Stopband
SB
24.1
Passband Ripple
PR
±0.02
Stopband Attenuation
SA
54
Group Delay (Note 31)
GD
25
DAC Digital Filter (LPF) + SCF:
FR
Frequency Response: 0 ∼ 20.0kHz
±1.0
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
Note 30. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.454*fs (@−0.05dB). Each response refers to that of 1kHz.
Note 31. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data of both channels
from the input register to the output of analog signal. HPF=LPF=FIL3=EQ=5-BiQuads=ALC=OFF.
DC CHARACTERISTICS
(Ta=-30 ~ 85°C; AVDD=2.2 ∼ 3.6V, DVDD=1.6 ∼ 3.6V; HVDD=2.2 ∼ 4.0V)
Parameter
Symbol
min
High-Level Input Voltage
2.2V≤DVDD≤3.6V
VIH
70%DVDD
1.6V≤DVDD<2.2V
VIH
80%DVDD
Low-Level Input Voltage
2.2V≤DVDD≤3.6V
VIL
1.6V≤DVDD<2.2V
VIL
Input Voltage at AC Coupling (Note 32)
VAC
0.4
High-Level Output Voltage
VOH
(Iout = −200μA)
DVDD−0.2
Low-Level Output Voltage
VOL
(Except SDA pin: Iout = 200μA)
VOL
(SDA pin, 2.0V≤DVDD≤3.6V: Iout = 3mA)
VOL
(SDA pin, 1.6V≤DVDD<2.0V: Iout = 3mA)
Input Leakage Current
Iin
Note 32. MCKI is connected to a capacitor. (Figure 8)
MS0991-E-00
typ
-
max
30%DVDD
20%DVDD
-
Units
V
V
V
V
Vpp
V
-
0.2
0.4
20%DVDD
±10
V
V
V
μA
2008/09
- 17 -
[AK4373]
SWITCHING CHARACTERISTICS
(Ta=-30 ~ 85°C; AVDD=2.2 ∼ 3.6V, DVDD=1.6 ∼ 3.6V; HVDD=2.2 ∼ 4.0V;CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
AC Pulse Width
tACW
18.5
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0991-E-00
2008/09
- 18 -
[AK4373]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0991-E-00
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2008/09
- 19 -
[AK4373]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 33)
tDBF
LRCK “↑” to BICK “↓” (Note 34)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 33)
tLRB
LRCK “↑” to BICK “↓” (Note 34)
tBLR
BICK “↑” to LRCK “↑” (Note 33)
tBLR
BICK “↓” to LRCK “↑” (Note 34)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
2
Audio Interface Timing (Right/Left justified & I S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 35)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 35)
tBLR
BICK “↑” to LRCK Edge (Note 35)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
-
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
-
ns
ns
ns
ns
ns
ns
−40
50
50
-
40
-
ns
ns
ns
50
50
50
50
-
-
ns
ns
ns
ns
Note 33. MSBS, BCKP bits = “00” or “11”.
Note 34. MSBS, BCKP bits = “01” or “10”.
Note 35. BICK rising edge must not occur at the same time as LRCK edge.
MS0991-E-00
2008/09
- 20 -
[AK4373]
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 37)
CCLK “↑” to CSN Edge (Note 37)
Control Interface Timing (I2C Bus mode): (Note 36)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 38)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Capacitive Load on Bus
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 39)
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
Cb
tSU:STO
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
μs
ns
tPD
150
-
-
ns
Note 36. I2C is a registered trademark of Philips Semiconductors.
Note 37. CCLK rising edge must not occur at the same time as CSN edge.
Note 38. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 39. The AK4373 can be reset by the PDN pin = “L”.
■ Timing Diagram
1/fCLK
tACW
1000pF
tACW
Measurement
Point
MCKI Input
100kΩ
VAC
VSS3
VSS3
Figure 8. MCKI AC Coupling Timing
MS0991-E-00
2008/09
- 21 -
[AK4373]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 9. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 10. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0991-E-00
2008/09
- 22 -
[AK4373]
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 11. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”)
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 12. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0991-E-00
2008/09
- 23 -
[AK4373]
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 13. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”)
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 14. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”)
MS0991-E-00
2008/09
- 24 -
[AK4373]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 15. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 16. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0991-E-00
2008/09
- 25 -
[AK4373]
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 17. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 18. Clock Timing (EXT Slave mode)
MS0991-E-00
2008/09
- 26 -
[AK4373]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Figure 19. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
VIH
CSN
VIL
tCSH
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
A6
A5
R/W
VIL
Figure 20. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
VIL
VIH
CDTIO
D2
D1
D0
VIL
Figure 21. WRITE Data Input Timing
MS0991-E-00
2008/09
- 27 -
[AK4373]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 22. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 23. Power Down & Reset Timing
MS0991-E-00
2008/09
- 28 -
[AK4373]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices (Table 2 and Table 3).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 40)
1
1
See Table 5
Figure 24
PLL Slave Mode 1
Figure 25
1
0
See Table 5
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Figure 26
1
0
See Table 5
Figure 27
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
0
0
x
Figure 28
EXT Master Mode
0
1
x
Figure 29
Note 40. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 2. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
L
GND
EXT Slave Mode
0
L
Selected by
FS1-0 bits
EXT Master Mode
0
L
Selected by
FS1-0 bits
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(Selected by
PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 3. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4373 is power-down mode (PDN pin = “L”) and exits reset state, the AK4373 is slave mode. After exiting reset state,
the AK4373 goes to master mode by changing M/S bit = “1”.
When the AK4373 is in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and
BICK pins of the AK4373 should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 4. Select Master/Slave Mode
MS0991-E-00
2008/09
- 29 -
[AK4373]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4373 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
0
2
0
0
0
0
0
1
0
0
LRCK pin
BICK pin
1fs
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
9
12
13
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
1
0
1
Others
R and C of
VCOC pin
C[F]
R[Ω]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
15k
330n
10k
10n
10k
10n
PLL Lock
Time
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
200ms
40ms
40ms
(default)
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
25MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
Others
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency) (N/A: Not Available)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is the MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin) (N/A: Not Available)
When PLL2 bit is “0” (PLL reference clock input is the LRCK or BICK pin), the sampling frequency is selected by FS3
and FS2 bits. (Table 7).
FS3 bit
FS2 bit
Sampling Frequency
Mode
FS1 bit
FS0 bit
Range
0
0
x
0
x
(default)
7.35kHz ≤ fs ≤ 12kHz
0
1
x
1
x
12kHz < fs ≤ 24kHz
1
0
x
2
x
24kHz < fs ≤ 48kHz
Others
Others
N/A
(x: Don’t care, N/A: Not available)
Table 7. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference: Clock: LRCK or BICK pin)
MS0991-E-00
2008/09
- 30 -
[AK4373]
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L”
(Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
See Table 10
See Table 11
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ
“1”. After that, the clock selected by Table 10 is output from the MCKO pin when PLL is locked. DAC output invalid data
when the PLL is unlocked. The output signal should be muted by writing “0” to DACH and DACS bits.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0991-E-00
2008/09
- 31 -
[AK4373]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 25MHz or 27MHz) is input to the
MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is
selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between
32fs or 64fs, by BCKO bit (Table 11).
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 25MHz, 27MHz
DSP or μP
AK4373
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
Figure 24. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
BCKO bit
MS0991-E-00
2008/09
- 32 -
[AK4373]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the
AK4373 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs must be synchronized with MCKO output. The phase between MCKO and LRCK is not
important. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO
bit. Sampling frequency can be selected by FS3-0 bits (Table 6).
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 25MHz, 27MHz
AK4373
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
Figure 25. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0991-E-00
2008/09
- 33 -
[AK4373]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 7).
AK4373
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 26. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4373
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 27. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
The external clocks (BICK and LRCK) must always be present whenever the DAC is in operation (PMDAC bit = “1”). If
these clocks are not provided, the AK4373 may draw excess current and it is not possible to operate properly because
utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down
mode (PMDAC bit = “0”).
MS0991-E-00
2008/09
- 34 -
[AK4373]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4373 changes to EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of a normal audio DAC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks is not important. The input frequency of MCKI is selected by FS1-0 bits (Table 12).
Mode
0
1
2
3
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
256fs
(default)
7.35kHz ∼ 48kHz
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
512fs
7.35kHz ∼ 26kHz
x
1
1
512fs
7.35kHz ∼ 48kHz
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
FS3-2 bits
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins at fs=8kHz is shown in Table 13.
Mode
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
0
256fs
56dB
2
512fs
3
512fs
75dB
1
1024fs
93dB
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4373 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the
power-down mode (PMDAC bit = “0”).
AK4373
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 28. EXT Slave Mode
MS0991-E-00
2008/09
- 35 -
[AK4373]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4373 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (Table 14).
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
256fs
(default)
7.35kHz ∼ 48kHz
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
512fs
7.35kHz ∼ 26kHz
x
1
1
512fs
7.35kHz ∼ 48kHz
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
Mode
0
1
2
3
FS3-2 bits
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through the HPL/HPR pins at fs=8kHz is shown in Table 15.
Mode
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
0
256fs
56dB
2
512fs
3
512fs
75dB
1
1024fs
93dB
Table 15. Relationship between MCKI and S/N of HPL/HPR pins
MCKI should always be present whenever the DAC is in operation (PMDAC bit = “1”). If MCKI is not provided, the
AK4373 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the DAC should be in the power-down mode (PMDAC bit = “0”).
AK4373
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
Figure 29. EXT Master Mode
■ MCKO output frequency
MCKO output frequency can be controlled by PS1/0 bits when MCKO bit is “1” regardless of any clock mode
(PLL/EXT, Master/Slave).
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 16. MCKO Output Frequency (EXT Mode, MCKO bit = “1”)
MS0991-E-00
2008/09
- 36 -
[AK4373]
■ System Reset
The PDN pin must be held to “L” upon power-up. The 4373 should be reset by bringing PDN pin “L” for 150ns or more.
All of the internal register values are initialized by the system reset. After exiting reset, VCOM, DAC, HPL, HPR, LOUT,
ROUT, SPP and SPN switch to the power-down state. The contents of the control register are maintained until the reset is
completed.
The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to “1”. The DAC is in power-down
mode until MCKI is input.
■ Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (Table 17). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4373 in master mode, but must be input to the AK4373 in slave mode.
Mode
0
1
2
3
4
5
6
7
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 bit
0
1
0
1
0
1
0
1
SDTI (DAC)
BICK
16 bit DSP Mode
≥32fs
16 bit LSB justified
≥32fs
16/20/24 bit MSB justified
32fs or ≥48fs
16/20/24 bit I2S compatible
32fs or ≥48fs
20 bit LSB justified
≥40fs
24 bit LSB justified
≥48fs
20 bit DSP Mode
≥40fs
24 bit DSP Mode
≥48fs
Table 17. Audio Interface Format
Figure
Table 18
Figure 34
Figure 36
Figure 37
Figure 35
Figure 35
Table 18
Table 18
(default)
In Modes 1- 5 the SDTI is latched on the rising edge (“↑”) of BICK.
In Modes 0/6/7 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18, Table 19 and Table 20).
DIF2
0
DIF1
0
DIF0
0
MSBS
BCKP
0
0
0
1
1
0
1
1
Audio Interface Format
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the rising edge (“↑”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the falling edge (“↓”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd falling edge (“↓”) of the
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd rising edge (“↑”) of the
BICK after the rising edge (“↑”) of LRCK..
Table 18. Audio Interface Format in Mode 0
MS0991-E-00
Figure
Figure 30
(default)
Figure 31
Figure 32
Figure 33
2008/09
- 37 -
[AK4373]
DIF2
1
DIF2
1
DIF1
1
DIF1
1
DIF0
0
DIF0
1
MSBS
BCKP
0
0
0
1
1
0
1
1
MSBS
BCKP
0
0
0
1
1
0
1
1
Audio Interface Format
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the rising edge (“↑”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the falling edge (“↓”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd falling edge (“↓”) of the
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd rising edge (“↑”) of the
BICK after the rising edge (“↑”) of LRCK..
Table 19. Audio Interface Format in Mode 6
Audio Interface Format
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the rising edge (“↑”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the falling edge (“↓”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd falling edge (“↓”) of the
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the 2nd rising edge (“↑”) of the
BICK after the rising edge (“↑”) of LRCK..
Table 20. Audio Interface Format in Mode 7
MS0991-E-00
Figure
Figure 38
(default)
Figure 39
Figure 40
Figure 41
Figure
Figure 42
(default)
Figure 43
Figure 44
Figure 45
2008/09
- 38 -
[AK4373]
LRCK
(Master)
LRCK
(Slave)
31
0
1
8
2
9
10
11
12
13
14
15
16
17 18
24
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTI(i)
0
63
Rch
15 14
0
1
8
7
6
14
2
15
5
16
4
3
17
2
18
1
0
30
31
15 14
32
33
8
7
46
34
6
47
5
4
3
48
49
50
26
27
26
2
1
0
62
63
30
31
BICK(64fs)
Rch
Lch
SDTI(i)
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 30. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
31
0
1
8
2
9
10
11
12
13
14
15
16
17 18
24
25
29
0
BICK(32fs)
Lch
SDTI(i)
0
63
Rch
15 14
0
1
8
7
6
14
2
15
5
16
4
17
3
2
18
1
0
30
31
15 14
32
8
33 34
7
46
6
47
5
4
3
48
49
50
26
27
26
2
1
0
62
63
30
31
BICK(64fs)
Rch
Lch
SDTI(i)
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 31. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
31
0
1
8
2
9
10
11
12
13
14
15
16
17 18
24
25
29
0
BICK(32fs)
Lch
SDTI(i)
0
63
Rch
15 14
0
1
8
7
14
2
6
15
5
16
4
17
3
2
18
1
30
0
31
15 14
32
33
34
8
7
46
6
47
5
48
4
49
3
50
2
1
62
0
63
BICK(64fs)
Lch
SDTI(i)
15 14
Rch
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 32. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
MS0991-E-00
2008/09
- 39 -
[AK4373]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTI(i)
0
15
Rch
15 14
0
1
8
7
14
2
6
15
5
16
4
17
3
2
1
18
30
0
31
15 14
32
33
8
7
46
34
6
47
5
48
4
49
3
50
2
1
62
0
63
BICK(64fs)
Lch
SDTI(i)
Rch
15 14
2
1
0
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 33. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
LRCK
BICK
(32fs)
SDTI
Mode 1
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
1
0
15
14
0
19
0
19
0
15
14
BICK
SDTI
Mode 1
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 34. Mode 1 Timing
LRCK
BICK
SDTI
Mode 4
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDTI
Mode 5
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 35. Mode 4, 5 Timing
MS0991-E-00
2008/09
- 40 -
[AK4373]
Rch
Lch
LRCK
BICK
SDTI
16bit
15
14
0
SDTI
20bit
19
18
4
1
0
SDTI
24bit
23
22
8
3
4
1
0
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
0
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
Figure 36. Mode 2 Timing
Lch
LRCK
Rch
BICK
SDTI
16bit
15
14
0
SDTI
20bit
19
18
4
1
0
SDTI
24bit
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
BICK
(32fs)
SDTI
16bit
0
1
0
0
15
Figure 37. Mode 3 Timing
MS0991-E-00
2008/09
- 41 -
[AK4373]
LRCK
(Master)
LRCK
(Slave)
63
0
1
18
2
19
20
21
22
38
39
40
41
42
46
47
48
49
50
62
63
48
49
50
62
63
48
49
50
62
63
48
49
50
62
63
BICK(64fs)
Rch
Lch
SDTI(i)
19 18
2
1
0
19 18
2
1
0
1/fs
19:MSB, 0:LSB
Figure 38. Mode 6 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
18
2
19
20
21
22
38
39
40
41
42
46
47
BICK(64fs)
Rch
Lch
SDTI(i)
19 18
2
1
0
19 18
2
1
0
1/fs
19:MSB, 0:LSB
Figure 39. Mode 6 Timing (BCKP = “1”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
18
2
19
20
21
22
38
39
40
41
42
46
47
BICK(64fs)
Lch
SDTI(i)
Rch
19 18
2
1
0
19 18
2
1
0
1/fs
19:MSB, 0:LSB
Figure 40. Mode 6 Timing (BCKP = “0”, MSBS = “1”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
18
2
19
20
21
22
38
39
40
41
42
46
47
BICK(64fs)
Lch
SDTI(i)
19 18
Rch
2
1
0
19 18
2
1
0
1/fs
19:MSB, 0:LSB
Figure 41. Mode 6 Timing (BCKP = “1”, MSBS = “1”)
MS0991-E-00
2008/09
- 42 -
[AK4373]
LRCK
(Master)
LRCK
(Slave)
63
0
1
22
2
23
24
25
26
46
47
48
49
50
54
55
56
57
58
62
63
56
57
58
62
63
56
57
58
62
63
56
57
58
62
63
BICK(64fs)
Rch
Lch
SDTI(i)
23 22
2
1
0
23 22
2
1
0
1/fs
23:MSB, 0:LSB
Figure 42. Mode 7 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
22
2
23
24
25
26
46
47
48
49
50
54
55
BICK(64fs)
Rch
Lch
SDTI(i)
23 22
2
1
0
23 22
2
1
0
1/fs
23:MSB, 0:LSB
Figure 43. Mode 7 Timing (BCKP = “1”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
22
2
23
24
25
26
46
47
48
49
50
54
55
BICK(64fs)
Lch
SDTI(i)
Rch
23 22
2
1
0
23 22
2
1
0
1/fs
23:MSB, 0:LSB
Figure 44. Mode 7 Timing (BCKP = “1”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
63
0
1
22
2
23
24
25
26
46
47
48
49
50
54
55
BICK(64fs)
Lch
SDTI(i)
23 22
Rch
2
1
0
23 22
2
1
0
1/fs
23:MSB, 0:LSB
Figure 45. Mode 7 Timing (BCKP = “1”, MSBS = “1”)
MS0991-E-00
2008/09
- 43 -
[AK4373]
■ Digital EQ/HPF/LPF
The AK4373 performs high/low pass filter, stereo separation emphasis, gain compensation, five programmable biquads,
ALC (Automatic Level Control) and digital volume by digital domain for input data (Figure 46). HPF, LPF, FIL3, and EQ
blocks are IIR filters of 1st order. The filter coefficient of HPF, LPF, FIL3, and EQ blocks can be set to any value.
Refer to the section of “Five Programmable Biquads”, “ALC operation” and “Digital Output Volume” about five
programmable biquads, ALC and digital volume, respectively.
FIL3 coefficient also sets the attenuation of the stereo separation emphasis.
The combination of GN1-0 bit (Table 21) and EQ coefficient set the compensation gain.
FIL3 block becomes HPF when F3AS bits are “0” and become LPF when F3AS bits are “1”.
When EQ, HPF and LPF bits are “0”, EQ, HPF and LPF blocks become “through” (0dB). When each filter coefficient is
changed, each filter should be set to “through”.
Stereo
Separation
emphasis
HPF
Any coefficient
F1A13-0
F1B13-0
LPF
Gain compensation
FIL3
Any coefficient
F2A13-0
F2B13-0
Any coefficient
F3A13-0
F3B13-0
F3AS
0dB ∼ -10dB
EQ
Any coefficient
EQA15-0
EQB13-0
EQC15-0
+12dB ∼ 0dB
Gain
Five
Biquads
ALC
DVOL
GN1-0
+24/+12/0dB
Figure 46. Digital EQ/HPF/LPF (default)
GN1
GN0
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 21. Gain select of gain block (x: Don’t care)
MS0991-E-00
2008/09
- 44 -
[AK4373]
[Filter Coefficient Setting]
(1) High Pass Filter (HPF)
fs: Sampling frequency
fc: Cut-off frequency
f: Input signal frequency
Register setting (Note 41)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1−z
H(z) = A
Amplitude
−1
1 + Bz −1
2 − 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
Phase
θ(f) = tan −1
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
(2) Low Pass Filter (LPF)
fs: Sampling frequency
fc: Cut-off frequency
f: Input signal frequency
Register setting (Note 41)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F2B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
Amplitude
1 + z −1
H(z) = A
1 + Bz −1
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0991-E-00
Phase
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2008/09
- 45 -
[AK4373]
(3) Stereo Separation Emphasis Filter (FIL3)
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 41)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
Amplitude
1 − z −1
H(z) = A
2 − 2cos (2πf/fs)
M(f) = A
1 + Bz −1
1 + B2 + 2Bcos (2πf/fs)
Phase
θ(f) = tan −1
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 41)
FIL3: F3AS bit = “1”, F3A [13:0] bits =A, F3B [13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
Transfer function
1+z
H(z) = A
1 + 1 / tan (πfc/fs)
Amplitude
−1
1 + Bz −1
B=
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0991-E-00
Phase
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2008/09
- 46 -
[AK4373]
(4) EQ
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
f: Input signal frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Note 41)
EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C
(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
,
B=
1 + 1 / tan (πfc1/fs)
Transfer function
A + Cz
H(z) =
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
Amplitude
−1
1 + Bz −1
1 − 1 / tan (πfc1/fs)
2
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Phase
2
A + C + 2ACcos (2πf/fs)
M(f) =
1 + B2 + 2Bcos (2πf/fs)
θ(f) = tan −1
(AB−C)sin (2πf/fs)
A + BC + (AB+C)cos (2πf/fs)
Note 41. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sign bit.
MS0991-E-00
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[AK4373]
[Filter Coefficient Setting Example]
1) HPF block
Example: fs=44.1kHz, fc=100Hz
F1A[13:0] bits = 01 1111 1100 0110
F1B[13:0] bits = 10 0000 0111 0100
2) LPF block
Example: fs=44.1kHz, fc=10kHz
F2A[13:0] bits = 01 0001 0010 1100
F2B[13:0] bits = 00 0010 0101 0111
3) FIL3 block
Example: fs=44.1kHz, fc=4kHz, Gain=-6dB, F3AS bit = “1” (LPF)
F3A[13:0] bits = 00 0011 1010 0010
F3B[13:0] bits = 10 1110 1000 0000
4) EQ block
Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB
Gain[dB]
+8dB
fc1
fc2
Frequency
EQA[15:0] bits = 0000 1001 0110 1110
EQB[13:0] bits = 10 0001 0101 1001
EQC[15:0] bits = 1111 1001 1110 1111
MS0991-E-00
2008/09
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[AK4373]
■ Five Programmable Biquads
This block can be used as Equalizer or Notch Filter. 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) is ON/OFF
independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When the Equalizer is OFF, the audio data passes this block by
0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the
coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0
bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the coefficient of EQ5. The EQx (x=1∼5)
coefficient should be set when EQx bit = “0” or PMDAC bit = “0”.
fs: Sampling frequency
fo1 ~ fo5: Center frequency
fb1 ~ fb5: Band width where the gain is 3dB different from center frequency
K1 ~ K5 : Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 42)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
An = Kn x
tan (πfbn/fs)
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer function
H(z) = 1 + h1(z) + h2(z) + h3(z) + h4(z) + h5(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency should be set as below.
fon / fs < 0.497
Note 42. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sign bit.
MS0991-E-00
2008/09
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[AK4373]
■ ALC Operation
The ALC (Automatic Level Control) is controlled by ALC block when ALC bit is “1”.
1.
ALC Limiter Operation
During ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 22), the AVL and
AVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 23).
When ZELMN bit = “0” (zero cross detection is enabled), the AVL and AVR values are changed by ALC limiter
operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero
crossing timeout period of both ALC limiter and recovery operation (Table 24). When ALC output level exceeds
full-scale, IVL and IVR values are immediately (Period: 1/fs) changed. When ALC output level is less than full-scale,
IVL and IVR values are changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), AVL and AVR values are immediately (period: 1/fs) changed
by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is done continuously until the input signal level becomes ALC limiter detection level (Table 22)
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0
0
1
0
1
ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
(default)
ALC1 Limiter ATT Step (0.375dB/step)
ALC1 Output ≥ LMTH
1
2
2
1
Table 23. ALC Limiter ATT Step
(default)
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC Zero Crossing Timeout Period
MS0991-E-00
(default)
2008/09
- 50 -
[AK4373]
2.
ALC Recovery Operation
ALC recovery operation wait for the WTM2-0 bits (Table 25) to be set after completing ALC limiter operation. If the
input signal does not exceed “ALC recovery waiting counter reset level” (Table 22) during the wait time, ALC recovery
operation is completed. The AVL and AVR values are automatically incremented by RGAIN1-0 bits (Table 26) up to the
set reference level (Table 27) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 24). Then
the AVL and AVR are set to the same value for both channels. ALC recovery operation is executed at a period set by
WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, ALC recovery
operation waits until WTM2-0 period and the next recovery operation is completed. If ZTM1-0 is longer than WTM2-0
and no zero crossing occurs, ALC recovery operation is made at a period set by ZTM1-0 bits.
For example, when the current AVOL value is 30H and RGAIN1-0 bits are set to “01”, AVOL is changed to 32H by the
auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the AVOL value exceeds
the reference level (REF7-0), the AVOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
ALC operation corresponds to the impulse noise. When the impulse noise is input, ALC recovery operation is faster than
a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone instantaneously, quality
of small signal level in the large noise can be improved by this fast recovery operation. The speed of fast recovery
operation is set by RFST1-0 bits (Table 28).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 25. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 26. ALC Recovery GAIN Step
MS0991-E-00
(default)
(default)
2008/09
- 51 -
[AK4373]
REF7-0
GAIN(dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
0.375dB
E1H
+30.0
(default)
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 27. Reference Level at ALC Recovery operation
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 28. Fast Recovery Speed Setting (N/A: not available)
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2008/09
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[AK4373]
3.
Example of ALC Operation
Table 29 shows the examples of the ALC setting.
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of AVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
011
23.2ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
1 step
1 step
4 times
Enable
00
1 step
00
1 step
00
4 times
1
Enable
Table 29. Example of the ALC setting
The following registers should not be changed during ALC operation. These bits should be changed after ALC operation
is finished by ALC bit = “0” or PMDAC bit = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (AVL/R7-0) * The value of AVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=01H
ALC Operation
Note : WR : Write
Figure 47. Registers set-up sequence at ALC operation
MS0991-E-00
2008/09
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[AK4373]
■ Digital Volume at ALC Block (Manual Mode)
The digital volume at ALC block changes to a manual mode when ALC bit is “0”. This mode is used in the case shown
below.
1.
2.
After exiting reset state, set-up the registers for ALC operation (ZTM1-0, LMTH1-0 and etc)
When the registers for ALC operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
AVL7-0 and AVR7-0 bits set the gain of the volume control at ALC block (Table 30). The AVOL value is changed at
zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits.
When ALC is not used, AVL7-0 and AVR7-0 bits should be set to “91H” (0dB).
AVL7-0
GAIN (dB)
Step
AVR7-0
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
0.375dB
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54
00H
MUTE
Table 30. ALC Block Digital Volume Setting
MS0991-E-00
(default)
2008/09
- 54 -
[AK4373]
When writing to the AVL7-0 and AVR7-0 bits continuously, the control register should be written by an interval more
than zero crossing timeout. If not, AVL and AVR are not changed since zero crossing counter is reset at every write
operation. If the same register value as the previous write operation is written to AVL and AVR, this write operation is
ignored and zero crossing counter is not reset. Therefore, AVL and AVR can be written by an interval less than zero
crossing timeout.
ALC bit
ALC Status
Disable
Enable
AVL7-0 bits
E1H(+30dB)
AVR7-0 bits
C6H(+20dB)
Internal AVL
E1H(+30dB)
Internal AVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
Disable
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
Figure 48. AVOL value during ALC operation
(1) The AVL value becomes the start value if the AVL and AVR are different when the ALC starts. The wait time from
ALC bit = “1” to ALC operation start by AVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout
period (ZTM1-0 bits).
(2) Writing to AVL and AVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the
AVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be
set to “1” by an interval more than zero crossing timeout period after ALC bit = “0”.
MS0991-E-00
2008/09
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[AK4373]
■ De-emphasis Filter
The AK4373 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter (Table 31).
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 31. De-emphasis Control
■ Digital Output Volume
The AK4373 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and
DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or
MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit
= “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function.
The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 33). When
DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs ([email protected]=44.1kHz)
from 00H (+12dB) to FFH (MUTE).
DVL/R7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
18H
0dB
(default)
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 32. Digital Volume Code Table
DVTM bit
0
1
Transition time between DVL/R7-0 bits = 00H and FFH
Setting
fs=8kHz
fs=44.1kHz
1061/fs
133ms
24ms
256/fs
32ms
6ms
Table 33. Transition Time Setting of Digital Output Volume
MS0991-E-00
(default)
2008/09
- 56 -
[AK4373]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit changed to “1”, the output signal is
attenuated by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the
DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation
is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal
source without stopping the signal transmission (Figure 49).
S M U T E bit
D VTM bit
D VL/R 7-0 bits
D VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 49. Soft Mute Function
(1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the
value set by the DVL/R7-0 bits.
MS0991-E-00
2008/09
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[AK4373]
■ Analog Mixing: Monaural input
When PMMIN bit is set to “1”, the mono input is powered-up. When MINH/S bits are set to “1”, the input signal from the
MIN+/MIN- pin is output to HP-Amp/Speaker-Amp. The external resisters Ri adjust the signal gain of MIN+/MINinput. If the Analog Mixing block will use as a single-ended, the MIN- pin should be connected to VSS1 in series with
capacitor to avoid induced external noise.(Figure 51)
When the headphone output type is Differential (HPBTL bit = “1”), HVDD should be the same as the voltage of AVDD
to use the path from MIN to HP-Amp(MINH bit = “1”).
DACH/S bit
DAC
MINH/S bit
−
−
+
+
HP Amp / SPK Amp
Rin
Rin
MIN- pin
20k(typ)
MIN+ pin
20k(typ)
20k(typ)
−
+
−
+
Figure 50. Block Diagram of Monaural input (Differential Input)
DACH/S bit
DAC
MINH/S bit
−
−
+
+
HP Amp / SPK Amp
MIN- pin
Rin
MIN+ pin
20k(typ)
20k(typ)
20k(typ)
−
+
−
+
Figure 51. Block Diagram of Monaural input (Single Input)
MS0991-E-00
2008/09
- 58 -
[AK4373]
■ Analog Output Control
HPBTL and PSEUDO bits select the output type, Single-ended, Differential or Pseudo cap-less (Table 34). Available pins
and bits are changed at each output type.
HPBTL bit
0
1
0
1
PSEUDO bit
Headphone Output Type
Figure
0
Single-ended (default)
Figure 1
0
Differential
Figure 2
1
Pseudo cap-less
Figure 3
1
N/A
Table 34. Headphone Output Type Select (N/A: Not Available)
Table
Table 35
Table 36
Table 37
Available pin / bit
Pin / Control
Pin
HPL/R, LOUT/ROUT
SPP/SPN
Power management
PMHPL/R
PMSPK(SPPSN)
Switch Control from MIN to HP-Amp
MINH
MINS
Switch Control from DAC to HP-Amp
DACH
DACS
Gain Control
HPG
SPKG[1:0]
Table 35. Available pin / bit (Single-ended, HPBTL bit = PSEUDO bit = “0”)
Available pin / bit
Pin / Control
Pin
HPL+/HPR +/Power management
PMHPL
PMHPR
Switch Control from MIN to HP-Amp
MINH
MINH
Switch Control from DAC to HP-Amp
DACH
DACH
Gain Control
HPG
HPG
Table 36. Available pin / bit (Differential, HPBTL bit = “1”, PSEUDO bit = “0”)
Available pin / bit
Pin / Control
Pin
HPL/R
HVCM
Power management
PMHPL/R
PMHPL or PMHPR
Switch Control from MIN to HP-Amp
MINH
Switch Control from DAC to HP-Amp
DACH
Gain Control
HPG
Table 37. Available pin / bit (Pseudo cap-less, HPBTL bit = “0”, PSEUDO bit = “1”)
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2008/09
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[AK4373]
■ Stereo Line Output (LOUT/ROUT pins)
The common voltage is 0.5 x HVDD when VBAT bit = “0” (Table 40). The load resistance is 10kΩ (min).
Stereo line out amplifier is shared with Headphone amplifier (HPBTL bit = PSEUDO bit = “0” in Table 38). When
PMHPL/R and HPMTN bits are “1”, the stereo line output is powered-up (Figure 52).
Stereo line out amplifier is prohibited from using headphone output at the same time.
■ Headphone Output
The power supply voltage for the Headphone-Amp is supplied from the HVDD pin and the output level is centered on the
HVDD/2 when VBAT bit = “0”. If HVDD voltage becomes lower, the output signal might be distorted while the
amplitude is maintained. The load resistance is 16Ω (min). HPBTL and PSEUDO bits select the output type, Single-ended
or Differential or Pseudo cap-less. When the HPBTL bit is “1”, HPL/HPR/SPP/SPN pins become
HPL+/HPL-/HPR+/HPR- pins, respectively. When the PSEUDO bit is “1”, the SPN pin become the HVCM pin. HPG bit
selects the output voltage (Table 38).
HPBTL
0
0
1
1
0
0
1
PSEUDO
HPG
Output Type
Output pins
Output Voltage [Vpp]
0
0
Single-ended
HPL, HPR
0.6 x AVDD
0
1
Single-ended
HPL, HPR
0.91 x AVDD
0
0
Differential
HPL+/-, HPR+/1.2 x AVDD
0
1
Differential
HPL+/-, HPR+/1.82 x AVDD
1
0
Pseudo cap-less
HPL, HPR, HVCM
0.6 x AVDD
1
1
Pseudo cap-less
HPL, HPR, HVCM
0.91 x AVDD
1
x
N/A
Table 38. Headphone-Amp Output Type and Output Voltage (x: Don’t care, N/A: Not available)
When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL/R and HPL+/- and
HPR+/- and HVCM pins) go to “L” (VSS2). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at
VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant
is in proportional to HVDD voltage and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0μF±30%, HVDD=3.6V:
Rising time (0.8 x HVDD/2): 150ms(typ), 260ms(max) at HPMTN bit = “0” Æ “1”
Time until the common voltage goes to VSS2: 140ms(typ), 260ms(max) at HPMTN bit = “1” Æ “0”
When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go
to “L” (VSS2).
PMHPL bit,
PMHPR bit
HPMTN bit
HPL/R pins
HPL+/- pins
HPR+/- pins
HVCM pin
(1) (2)
(3)
(4)
Figure 52. Power-up/Power-down Timing for Headphone-Amp
(1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still VSS2.
(2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising.
(3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.
(4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are VSS2. If the power supply is switched
off or Headphone-Amp is powered-down before the common voltage changes to VSS2, POP noise occurs.
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[AK4373]
<External Circuit of Headphone-Amp>
1) Single-ended Output (HPBTL bit = “0”, PSEUDO bit = “0”)
The cut-off frequency (fc) of Headphone-Amp depends on an external resistor and a capacitor. Table 39 shows the cut off
frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 2.7, 3.3 and 3.8V. The output voltage of headphone is 0.6 x AVDD (Vpp).
HP-AMP
C
R
Headphone
16Ω
AK4373
Figure 53. External Circuit Example of Headphone (Single-ended output)
HPG bit
R [Ω]
0
0
6.8
16
0
1
100
C [μF]
fc [Hz]
Output Power [mW]@0dBFS(Note 43)
HVDD=2.7V HVDD=3.3V HVDD=3.8V
AVDD=2.7V AVDD=3.3V AVDD=3.3V
220
45
20
30
100
100
100
70
10
15
47
149
100
50
5.0
7.5
47
106
67
44
220
45
(Note 44)
(Note 44)
100
100
22
62
0.9
1.3
10
137
Table 39. External Circuit Example (Single-ended output)
30
15
7.5
70
1.3
Note 43. Output power at 16Ω load.
Note 44. Output signal is clipped.
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[AK4373]
2) Differential Output (HPBTL bit = “1” PSEUDO bit = “0”)
For differential output, no external AC coupling capacitor is required.
Power management (power up/down control) of L/Rch is controlled by setting PMHPL/PMHPR bits respectively. The
common voltage control of Headphone-Amp is controlled by setting HTMTN bit. The common voltage is shown in Table
40. HPBTL bit should be changed when both speaker and headphone amps are powered-down.
AK4373
HPL+ pin
+
−
Headphone Lch
+
−
Headphone Rch
HPL− pin
HPR+ pin
HPR− pin
Figure 54. External Circuit Example of Headphone (Differential output)
MS0991-E-00
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[AK4373]
3) Pseudo cap-less Output (HPBTL bit = “0”, PSEUDO bit =”1”)
In case of pseudo cap less, no external AC coupling capacitor is required as well as BTL mode. This pseudo cap less mode
is also available for normal 3-pin headphone mini jack while BTL mode requires a closed system with 4-wire connection.
Power management (power up/down control) of VCOM Amp for HP-Amp is controlled by setting PMHPL bit or
PMHPR bit. The common voltage control of Headphone-Amp and VCOM-Amp is controlled by setting HTMTN bit. The
common voltage is shown in Table 40. PSEUDO bit should be changed when both speaker and headphone amps are
powered-down.
In this mode, HPBTL and DACS and MINS bits must be “0”.
HP-Amp
HPL pin
Headphone
R
16Ω
VCOM Amp for
HP-Amp
HVCM pin
HP-Amp
16Ω
HPR pin
R
Figure 55. External Circuit Example of Headphone (pseudo cap-less output)
<Headphone-Amp PSRR>
When HVDD is directly supplied from the battery in the mobile phone system, RF noise may influences headphone
output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is improved. In this
case, HP-Amp common voltage is 0.64 x AVDD (typ). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when
HVDD voltage becomes lower than 4.2V, the output signal will be clipped easily.
VBAT bit
Common Voltage [V]
0
0.5 x HVDD
Table 40. HP-Amp Common Voltage
MS0991-E-00
1
0.64 x AVDD
2008/09
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[AK4373]
■ Speaker Output (SPP/SPN pins)
Recommended power supply range is 2.6V to 4.0V. If HVDD voltage becomes low, the output signal might be distorted
while the amplitude is maintained. Speaker-Amp is available at HPBTL bit = PSEUDO bit = “0”.
Speaker Type
Dynamic Speaker
Piezo (Ceramic) Speaker
Load Resistance (min)
8Ω
50Ω
Load Capacitance (max)
30pF
3μF
Note 21. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in
34HFigure 56. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 20Ω or more series
resistors should be connected at both SPP and SPN pins, respectively.
Table 41. Speaker Type and Power Supply Range
The DAC signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is set by
SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
SPKG1-0 bits
00
01
10
11
Gain
ALC bit = “0”
ALC bit = “1”
+4.43dB
+6.43dB
+6.43dB
+8.43dB
+10.65dB
+12.65dB
+12.65dB
+14.65dB
Table 42. SPK-Amp Gain
(default)
SPK-Amp Output (DAC Input = 0dBFS)
ALC bit = “0”
ALC bit = “1”
(LMTH1-0 bits = “00”)
00
3.30Vpp
3.11Vpp
01
4.15Vpp (Note 45)
3.92Vpp
3.3V
10
6.75Vpp (Note 45)
6.37Vpp (Note 45)
11
8.50Vpp (Note 45)
8.02Vpp (Note 45)
3.3V
00
3.30Vpp
3.11Vpp
01
4.15Vpp
3.92Vpp
4.0V
10
6.75Vpp (Note 45)
6.37Vpp (Note 45)
11
8.50Vpp (Note 45)
8.02Vpp (Note 45)
Note 45. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp (HVDD=3.3V) or 4.8Vpp (HVDD=4V) or less and output
signal is not clipped.
Table 43. SPK-Amp Output Level
AVDD
HVDD
SPKG1-0 bits
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[AK4373]
<ALC Operation Example of Speaker Playback>
fs=44.1kHz
Operation
−2.5dBFS
Enable
11.6ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits
Maximum gain at recovery operation
011
23.2ms
C1H
+18dB
Gain of AVOL
91H
0dB
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
ALC
Data
00
0
10
Limiter ATT step
00
Recovery GAIN step
00
ALC enable
1
Table 44. ALC Operation Example of Speaker Playback
1 step
1 step
Enable
<Caution for using Piezo Speaker>
When a piezo speaker is used, two resistances more than 20Ω should be connected between SPP/SPN pins and speaker in
series, respectively, as shown in Figure 56. Zener diodes should be inserted between speaker and GND as shown in Figure
56, in order to protect SPK-Amp of the AK4373 from the power that the piezo speaker outputs when the speaker is
pressured. Zener diodes of the following zener voltage should be used.
0.92 x HVDD ≤ Zener voltage of zener diodo (ZD in Figure 56) ≤ HVDD+0.3V
Ex) In case of HVDD = 3.8V: 3.5V ≤ ZD ≤ 4.1V
For example, zener diode which zener voltage is 3.9V (Min: 3.7V, Max: 4.1V) can be used.
ZD
SPK-Amp
SPP
≥20Ω
SPN
≥20Ω
ZD
Figure 56. Speaker Output Circuit (Load Capacitance > 30pF)
MS0991-E-00
2008/09
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[AK4373]
<Speaker-Amp Control Sequence>
Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pin are in Hi-Z state.
When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, the SPP pin is
placed in Hi-Z state and the SPN pin changes to HVDD/2 voltage. Power-save mode can reduce pop noise at power-up
and power-down.
PMSPK
0
1
SPPSN
Mode
SPP
SPN
x
Power-down
VSS2
VSS2
0
Power-save
Hi-Z
HVDD/2
1
Normal Operation
Normal Operation Normal Operation
Table 45. Speaker-Amp Mode Setting (x: Don’t care)
(default)
PMSPK bit
SPPSN bit
SPP pin
VSS2
SPN pin
Hi-Z
Hi-Z
HVDD/2
HVDD/2
VSS2
VSS2
VSS2
>1ms
>0
Figure 57. Power-up/Power-down Timing for Speaker-Amp
MS0991-E-00
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[AK4373]
■ Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”) Write Only
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Read/Write (Fixed to “1”), Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (“↑”) of CCLK. Address and data are latched on the 16th CCLK rising edge (“↑”) after CSN
falling edge(“↓”). Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK Clock, “H” or “L”
CDTI “H” or “L”
Clock, “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1”
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 58. Serial Control I/F Timing
MS0991-E-00
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[AK4373]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4373 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 59 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 65). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure
60). If the slave address matches that of the AK4373, the AK4373 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 66). R/W bit value of “1” indicates that the read operation is to be executed. “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4373. The format is MSB first, and those most
significant bit is fixed to zeros (Figure 61). The data after the second byte contains control data. The format is MSB first,
8bits (Figure 62). The AK4373 generates an acknowledge after each byte is received. A data transfer is always terminated
by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines
STOP condition (Figure 65).
The AK4373 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4373
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 67) except for the START and STOP conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 59. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
CAD0
R/W
A2
A1
A0
D2
D1
D0
(CAD0 must match with the CAD0 pin)
Figure 60. The First Byte
0
A6
A5
A4
A3
Figure 61. The Second Byte
D7
D6
D5
D4
D3
Figure 62. Byte Structure after The Second Byte
MS0991-E-00
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[AK4373]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4373. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 4FH prior to generating stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK4373 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4373 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4373 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the AK4373
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 63. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4373 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates stop condition instead, the AK4373 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 64. RANDOM ADDRESS READ
MS0991-E-00
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[AK4373]
SDA
SCL
S
P
start condition
stop condition
Figure 65. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 66. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 67. Bit Transfer on the I2C-Bus
MS0991-E-00
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[AK4373]
■ Register Map
Add
r
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select 1
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
D6
D5
D4
D3
D2
D1
D0
0
0
SPPSN
0
PLL3
PS1
DVTM
0
REF7
AVL7
DVL7
RGAIN1
AVR7
DVR7
0
0
0
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
0
F1B7
0
0
0
0
0
0
0
0
0
0
0
0
0
F2A7
0
F2B7
0
PMVCM
HPMTN
MINS
0
PLL2
PS0
WTM2
0
REF6
AVL6
DVL6
LMTH1
AVR6
DVR6
0
0
0
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
0
0
0
0
0
0
0
0
0
0
0
F2A6
0
F2B6
0
PMMIN
PMHPL
DACS
0
PLL1
FS3
ZTM1
ALC
REF5
AVL5
DVL5
0
AVR5
DVR5
SMUTE
0
HPG
LPF
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
0
0
0
0
0
0
0
0
0
0
0
0
F2A5
F2A13
F2B5
F2B13
PMSPK
PMHPR
0
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
AVL4
DVL4
0
AVR4
DVR4
DVOLC
0
0
HPF
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
0
0
0
0
0
0
0
0
0
0
0
0
F2A4
F2A12
F2B4
F2B12
0
M/S
HPBTL
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
AVL3
DVL3
0
AVR3
DVR3
0
AVOLC
0
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
0
0
0
0
0
0
0
0
0
0
0
0
F2A3
F2A11
F2B3
F2B11
PMDAC
MCKAC
0
0
DIF2
FS2
WTM0
LMAT0
REF2
AVL2
DVL2
FRN
AVR2
DVR2
0
HPM
0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
0
0
0
0
0
0
0
0
0
0
0
0
F2A2
F2A10
F2B2
F2B10
0
MCKO
0
PMPLL
0
0
DIF0
FS0
RFST0
LMTH0
REF0
AVL0
DVL0
0
AVR0
DVR0
DEM0
DACH
0
PFSEL
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
0
0
0
0
0
0
0
0
0
0
0
0
F2A0
F2A8
F2B0
F2B8
MS0991-E-00
PSEUDO
0
DIF1
FS1
RFST1
RGAIN0
REF1
AVL1
DVL1
VBAT
AVR1
DVR1
DEM1
MINH
0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
0
0
0
0
0
0
0
0
0
0
0
F2A1
F2A9
F2B1
F2B9
2008/09
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[AK4373]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
Note 46. PDN pin = “L” resets the registers to their default values.
Note 47. Unused bits indicated “0” must contain a “0” value.
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■ Register Definitions
Addr
00H
Register Name
Power Management 1
Default
D7
0
0
D6
PMVCM
0
D5
PMMIN
0
D4
PMSPK
0
D3
0
0
D2
PMDAC
0
D1
0
0
D0
0
0
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMMIN: MIN Input Power Management
0: Power-down (default)
1: Power-up
The PMMIN bit must be set to “1” at the same time when the PMHPL bit, PMHPR bit or PMSPK bit is set to
“1”.
PMVCM: VCOM Power Management
0: Power-down (default)
1: Power-up
When any blocks are powered-up, the PMVCM bit must be set to “1”. The PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H and MCKO bits are “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless of the setting of this address. In this case, register is initialized to the default
value.
When all power management bits are “0” in the 00H, 01H addresses and MCKO bit is “0”, all blocks are
powered-down. The register values remain unchanged. The register values remain unchanged. Power supply current
is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin must be “L”.
When DAC is not used, external clocks may not be present. When DAC is used, external clocks must always be
present.
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Addr
01H
Register Name
Power Management 2
Default
D7
0
0
D6
HPMTN
0
D5
PMHPL
0
D4
PMHPR
0
D3
M/S
0
D2
MCKAC
0
D1
MCKO
0
D0
PMPLL
0
PMPLL: PLL Power Management
0: EXT Mode and Power-Down (default)
1: PLL Mode and Power-up
MCKO: Master Clock Output Enable on all clock mode (PLL Master/Slave Mode1, 2 /EXT Master, Slave Mode)
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
MCKAC: MCKI Input Mode Select
0: CMOS input (default)
1: AC coupling input
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
PMHPR: Headphone-Amp Rch Power Management
0: Power-down (default)
1: Power-up
PMHPL: Headphone-Amp Lch Power Management
0: Power-down (default)
1: Power-up
HPMTN: Headphone-Amp Mute Control
0: Mute (default)
1: Normal operation
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Addr
02H
Register Name
Signal Select 1
Default
D7
SPPSN
0
D6
MINS
0
D5
DACS
0
D4
0
0
D3
HPBTL
0
D2
0
0
PSEUDO, HPBTL: Headphone Output Type Select
HPBTL bit
PSEUDO bit
Headphone Output Type
Figure
0
0
Single-ended (default)
Figure 1
1
0
Differential
Figure 2
0
1
Pseudo cap-less
Figure 3
1
1
N/A
Table 46. Headphone Output Type Select (N/A: Not Available)
D1
PSEUDO
0
D0
0
0
Table
Table 35
Table 36
Table 37
DACS: Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
MINS: Switch Control from MIN to Speaker-Amp
0: OFF (default)
1: ON
When MINS bit is “1”, monaural signal is input to Speaker-Amp.
SPPSN: Speaker-Amp Power-Save Mode
0: Power-Save Mode (default)
1: Normal Operation
When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, the SPP pin goes to Hi-Z and the
SPN pin is outputs HVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled.
Addr
03H
Register Name
Signal Select 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
SPKG1
0
D3
SPKG0
0
D2
0
0
D1
0
0
D0
0
0
D1
DIF1
1
D0
DIF0
0
SPKG1-0: Speaker-Amp Output Gain Select (Table 42)
Addr
04H
Register Name
Mode Control 1
Default
D7
PLL3
0
D6
PLL2
0
D5
PLL1
0
D4
PLL0
0
D3
BCKO
0
D2
DIF2
0
DIF2-0: Audio Interface Format (Table 17)
Default: “010” (Left justified)
BCKO: BICK Output Frequency Select at Master Mode (Table 11)
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0000” (LRCK pin)
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Addr
05H
Register Name
Mode Control 2
Default
D7
PS1
0
D6
PS0
0
D5
FS3
0
D4
MSBS
0
D3
BCKP
0
D2
FS2
0
D1
FS1
0
D0
FS0
0
FS3-0: Sampling Frequency Select (Table 6 and Table 7.) and MCKI Frequency Select (Table 12.)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (Table 18)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Polarity at DSP Mode (Table 18)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (Table 10)
Default: “00” (256fs)
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Addr
06H
Register Name
Timer Select
Default
D7
DVTM
0
D6
WTM2
0
D5
ZTM1
0
D4
ZTM0
0
D3
WTM1
0
D2
WTM0
0
D1
RFST1
0
D0
RFST0
0
D2
LMAT0
0
D1
RGAIN0
0
D0
LMTH0
0
D2
REF2
0
D1
REF1
0
D0
REF0
1
RFST1-0: ALC First recovery Speed (Table 28)
Default: “00”(4times)
WTM2-0: ALC Recovery Waiting Period (Table 25.)
Default: “000” (128/fs)
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 24.)
Default: “00” (128/fs)
DVTM: Digital Volume Transition Time Setting (Table 33.)
0: 1061/fs (default)
1: 256/fs
This is the transition time between DVL/R7-0 bits = 00H and FFH.
Addr
07H
Register Name
ALC Mode Control 1
Default
D7
0
0
D6
0
0
D5
ALC
0
D4
ZELMN
0
D3
LMAT1
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 22.)
Default: “00”
LMTH1 bit is D6 bit of 0BH.
RGAIN1-0: ALC Recovery GAIN Step (Table 26.)
Default: “00”
RGAIN1 bit is D7 bit of 0BH.
LMAT1-0: ALC Limiter ATT Step (Table 23.)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
Addr
08H
Register Name
ALC Mode Control 2
Default
D7
REF7
1
D6
REF6
1
D5
REF5
1
D4
REF4
0
D3
REF3
0
REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 27.)
Default: “E1H” (+30.0dB)
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Addr
09H
0CH
Register Name
Lch Input Volume Control
Rch Input Volume Control
Default
D7
AVL7
AVR7
1
D6
AVL6
AVR6
1
D5
AVL5
AVR5
1
D4
AVL4
AVR4
0
D3
AVL3
AVR3
0
D2
AVL2
AVR2
0
D1
AVL1
AVR1
0
D0
AVL0
AVR0
1
AVL7-0, AVR7-0: ALC Block Digital Volume; 0.375dB step, 242 Level (Table 30.)
Default:“E1H” (+30dB)
Addr
0AH
0DH
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
Default
D7
DVL7
DVR7
0
D6
DVL6
DVR6
0
D5
DVL5
DVR5
0
D4
DVL4
DVR4
1
D3
DVL3
DVR3
1
D2
DVL2
DVR2
0
D1
DVL1
DVR1
0
D0
DVL0
DVR0
0
D5
0
0
D4
0
0
D3
0
0
D2
FRN
0
D1
VBAT
0
D0
0
0
D2
0
0
D1
DEM1
0
D0
DEM0
1
DVL7-0, DVR7-0: Output Digital Volume (Table 32.)
Default: “18H” (0dB)
Addr
0BH
Register Name
ALC Mode Control 3
Default
D7
RGAIN1
0
D6
LMTH1
0
VBAT: HP-Amp Common Voltage (Table 40.)
0: 0.5 x HVDD (default)
1: 0.64 x AVDD
FRN: Fast Recovery Enable
0: Enable(default)
1:Disable
LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 22.)
RGAIN1: ALC Recovery GAIN Step (Table 26.)
Addr
0EH
Register Name
Mode Control 3
Default
D7
0
0
D6
0
0
D5
SMUTE
0
D4
DVOLC
1
D3
0
0
DEM1-0: De-emphasis Frequency Select (Table 31)
Default: “01” (OFF)
DVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of
DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and
DVR7-0 bits control Rch level, respectively.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
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Addr
0FH
Register Name
Mode Control 4
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
AVOLC
1
D2
HPM
0
D1
MINH
0
D0
DACH
0
DACH: Switch Control from DAC to Headphone-Amp
0: OFF (default)
1: ON
MINH: Switch Control from MIN to HP-Amp
0: OFF (default)
1: ON
When MINH bit is “1”, monaural signal is input to HP-Amp.
HPM: Headphone-Amp Mono Output Select
0: Stereo (default)
1: Mono
When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2.
HPM bit must be changed when DAC is powered-down.
AVOLC: ALC Block Digital Volume Control Mode Select
0: Independent
1: Dependent (dfault)
When AVOLC bit = “1”, AVL7-0 bits control both Lch and Rch volume level, while register values of
AVL7-0 bits are not written to AVR7-0 bits. When AVOLC bit = “0”, AVL7-0 bits control Lch level and
AVR7-0 bits control Rch level, respectively.
Addr
10H
Register Name
Power Management 3
Default
D7
0
0
D6
0
0
D5
HPG
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D2
FIL3
0
D1
0
0
D0
0
0
HPG: Headphone-Amp Gain Select (Table 38.)
0: 0dB (default)
1: +3.6dB
HPG bit must be changed when the Headphone-Amp is powered-down.
Addr
11H
Register Name
Digital Filter Select 1
Default
D7
GN1
0
D6
GN0
0
D5
LPF
0
D4
HPF
0
D3
EQ
0
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are valid. When FIL3 bit is “0”, FIL3 block is
through (0dB).
EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are valid. When EQ bit is “0”, EQ
block is through (0dB).
HPF: High pass filter Coefficient Setting Enable
0: Disable (default)
1: Enable
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are valid. When HPF bit is “0”, HPF block is
through (0dB).
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LPF: Low pass filter Coefficient Setting Enable
0: Disable (default)
1: Enable
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are valid. When LPF bit is “0”, LPF block is
through (0dB).
GN1-0: Gain Select at GAIN block (Table 21.)
Default: “00”
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Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
2CH
2DH
2EH
2FH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
Default
D7
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
0
F1B7
0
F2A7
0
F2B7
0
0
D6
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
F2A6
0
F2B6
0
0
D5
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
0
D4
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
0
D3
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
0
D2
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
0
D1
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
0
D0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
0
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3 (Stereo Separation Emphasis Filter) Select
0: HPF (default)
1: LPF
EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
Default: “0000H”
F1A13-0, F1B13-0: High pass filer Coefficient (14bit x 2)
Default: “0000H”
F2A13-0, F2B13-0: Low pass filer Coefficient (14bit x 2)
Default: “0000H”
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Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”,
EQ4 block is through (0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”,
EQ5 block is through (0dB).
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Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
default: “0000H”
MS0991-E-00
2008/09
- 83 -
[AK4373]
SYSTEM DESIGN
Figure 68, Figure 69 and Figure 70 shows the system connection diagram for the AK4373. The evaluation board
[AKD4373] demonstrates the optimum layout, power supply arrangements and measurement results.
[Headphone: Single-ended Mode]
Headphone
10u
Dyn amic SPK
R1 , R2 : Sho rt
ZD1, ZD 2: Ope n
Pie zo SPK
R1 , R2 : ≥1 0Ω
ZD1, ZD 2: R equ ired
22
21
20
19
18
17
VSS2
HVDD
SPP/HPR+/TEST
SPN/HPR-/HVCM
MCKO
MCKI
R2
23
HPR/HPL-
BICK
14
LRCK
13
NC
12
30 NC
SDTI
11
31 NC
CDTI
10
32 NC
CCLK
9
27 LOUT
2.2u
I2C
PDN
CSN
7
8
5
μP
Rp
0.1u
0.1u
1
DSP
6
Top View
VCOC
29 MIN-
AVDD
AK4373EN
4
28 MIN+
VSS1
Ri
15
NC
Mono In
DVDD
26 ROUT
3
Ri
16
VCOM
1u
0.1u
VSS3
2
1u
Line Out
24
25 MUTET
HPL/HPL+
1u
R1
0.1u
ZD1
10
ZD2
220u
220u
Power Supply
2 .2 ∼ 3.6V
Speaker
Cp
Analog Ground
Digital Ground
Notes:
- VSS1, VSS2 and VSS3 of the AK4373 must be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed.
- When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in
Table 5.
- When piezo speaker is used, 2.6 ∼ 4.0V power must be supplied to HVDD and 20Ω or more series resistors
must be connected to both SPP and SPN pins, respectively.
- When the AK4373 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4373.
- If the Analog Mixing block is used as a single-ended, the MIN- pin must be connected to VSS1 in series with a
capacitor to avoid induced external noise.
Figure 68. Typical Connection Diagram (Single-ended mode, HPBTL bit = PSEUDO bit = “0”)
MS0991-E-00
2008/09
- 84 -
[AK4373]
[Headphone: Differential mode]
Headphone Lch
10u
23
22
21
20
19
18
17
HPR/HPL-
VSS2
HVDD
SPP/HPR+/TEST
SPN/HPR-/HVCM
MCKO
MCKI
25 MUTET
24
1u
HPL/HPL+
0.1u
10
Power Supply
2 .2 ∼ 3.6V
Headphone Rch
16
DVDD
15
BICK
14
LRCK
13
NC
12
30 NC
SDTI
11
31 NC
CDTI
10
32 NC
CCLK
9
26 ROUT
27 LOUT
PDN
CSN
7
8
VCOC
I2C
6
5
0.1u
2.2u
DSP
μP
Rp
AVDD
4
1
0.1u
VCOM
Top View
VSS1
29 MIN-
3
Ri
AK4373EN
NC
Mono In
28 MIN+
2
Ri
0.1u
VSS3
Cp
Analog Ground
Digital Ground
Notes:
- VSS1, VSS2 and VSS3 of the AK4373 must be distributed separately from the ground of external controllers.
- All digital input pins must not be left floating.
- When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed.
- When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in
Table 5.
- When the AK4373 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4373.
- If the Analog Mixing block will is used as a single-ended, the MIN- pin must be connected to VSS1 in series
with a capacitor to avoid induced external noise.
Figure 69. Typical Connection Diagram (Differential mode, HPBTL bit = “1”, PSEUDO bit = “0”)
MS0991-E-00
2008/09
- 85 -
[AK4373]
[Headphone: Pseudo cap-less mode]
Headphone
10u
20
19
18
17
MCKO
MC KI
21
HVDD
SPP/HPR+/TEST
22
V SS2
SPN/HPR-/HVCM
23
HPR/HPL-
25 MUTET
24
1u
HPL/HPL+
0.1u
10
Power Supply
2.2 ∼ 3.6V
VSS3
16
DVDD
15
BICK
14
LRCK
13
NC
12
30 NC
SDTI
11
31 NC
CDTI
10
32 NC
CCLK
9
26 ROUT
27 LOUT
I2C
PDN
CSN
7
8
VCOC
6
5
DSP
μP
Rp
AVDD
4
2.2u
0.1u
1
0.1u
VSS 1
Top View
VCOM
29 MIN-
3
Ri
AK4373EN
NC
Mono In
28 MIN+
2
Ri
0.1u
Cp
Analog Ground
Digital Ground
Notes:
- VSS1, VSS2 and VSS3 of the AK4373 must be distributed separately from the ground of external controllers.
- All digital input pins must not be left floating.
- When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed.
- When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in
Table 5.
- When the AK4373 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4373.
- If the Analog Mixing block is used as a single-ended, the MIN- pin must be connected to VSS1 in series with a
capacitor to avoid induced external noise.
Figure 70. Typical Connection Diagram (Pseudo cap-less mode, HPBTL bit = “0”, PSEUDO bit = “1”)
MS0991-E-00
2008/09
- 86 -
[AK4373]
1. Grounding and Power Supply Decoupling
The AK4373 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and HVDD are
usually supplied from the system’s analog supply. If AVDD, DVDD and HVDD are supplied separately, the power-up
sequence is not critical. VSS1, VSS2 and VSS3 of the AK4373 must be connected to the analog ground plane. System
analog ground and digital ground must be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors must be as close to the AK4373 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4373.
3. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit)
and a negative full scale for 800000H(@24bit). The Line Output-Amp, Headphone-Amp and Speaker-Amp outputs are
centered at HVDD/2 when VBAT bit is “0”. (Table 40)
MS0991-E-00
2008/09
- 87 -
[AK4373]
CONTROL SEQUENCE
■ Clock Set up
When DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Power Supply
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 71. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM must first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4373 starts to output the LRCK and the BICK clocks after the PLL becomes stable. Then normal
operation starts.
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
MS0991-E-00
2008/09
- 88 -
[AK4373]
2. PLL Slave Mode (LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 72. Clock Set Up Sequence (2)
<Example>
(2) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(3) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM must first be powered up before the other block operates.
(5) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 4ms(max)
when BICK is a PLL reference clock.
(6) Normal operation stats after that the PLL is locked.
MS0991-E-00
2008/09
- 89 -
[AK4373]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 73. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM must first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
MS0991-E-00
2008/09
- 90 -
[AK4373]
4. EXT Slave Mode
Example:
Audio I/F Format: MSB justified
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 74. Clock Set Up Sequence (4)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(2) DIF1-0 and FS1-0 bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM must first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
MS0991-E-00
2008/09
- 91 -
[AK4373]
5. EXT Master Mode
Example:
Audio I/F Format: MSB justified
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D6)
(3) Addr:04H, Data:02H
Addr:05H, Data:00H
Addr:01H, Data:08H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:01H, D3)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:40H
Figure 75. Clock Set Up Sequence (5)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(2) MCKI must be input.
(3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
MS0991-E-00
2008/09
- 92 -
[AK4373]
■ Speaker-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
1,111
Example:
(1)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
ALC: Enable
(13)
DACS bit
(Addr:02H, D5)
(2)
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
ALC Control 3
(Addr:0BH)
(1) Addr:05H, Data:27H
00
01
(2) Addr:02H, Data:20H
(3)
00H
3CH
(3) Addr:03H, Data:08H
(4)
E1H
C1H
(4) Addr:06H, Data:3CH
(5)
00H
00H
(5) Addr:08H, Data:E1H
1
(6) Addr:0BH, Data:00H
(6)
ALC bit
(Addr:07H, D5)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
0
(7)
E1H
(7) Addr:07H, Data:20H
91H
(8)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
(8) Addr:09H & 0CH, Data:91H
28H
(9)
(14)
PMDAC bit
(9) Addr:0AH & 0DH, Data:28H
(Addr:00H, D2)
(10) Addr:00H, Data:74H
PMMIN bit
(Addr:00H, D5)
(11) Addr:02H, Data:A0H
(10)
PMSPK bit
(Addr:00H, D4)
Playback
(11)
SPPSN bit
(Addr:02H, D7)
(12) Addr:02H, Data:20H
(12)
SPP pin
Hi-Z
Normal Output
Hi-Z
(13) Addr:02H, Data:00H
SPN pin
HVDD/2 Normal Output HVDD/2
(14) Addr:00H, Data:40H
Figure 76. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4373 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” Æ “01”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(8) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(10) Power Up of DAC and Speaker-Amp: PMDAC = PMSPK bits = “0” → “1”
When ALC bit is “1”, ALC operation starts from the gain set by AVL/R7-0 bits.
(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(13) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”
(14) Power Down DAC and Speaker-Amp: PMDAC = PMSPK bits = “1” → “0”
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■ Headphone-amp Output (Single-Ended or Differential or Pseudo cap-less)
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
Example:
DACH bit
(2)
(Addr:0FH, D0)
HPBTL,PSEU
DO bits
IVL/R7-0 bits
(12)
"00"(Single-ended)/ "10"(FullDifferential)/ "01"(Pseudo cap-less)
"0"
E1H
PLL, Master M ode
Audio I/F F ormat :MSB justified
Sam pling Frequency: 44.1kHz
Digital Volume: −8 dB
Bass B oost Level : M iddle
(1) Addr:05H, Data:27H
(3)
(Addr:02H, D3,D1)
(Addr:09H&0CH, D7-0)
1,111
(1)
(2) Addr:0FH, Data:09H
91H
(4)
(3) Addr:02H, Data:00H/08H/02H
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
28H
(4) Addr:09H&0CH, Data:91H
(5)
PMDAC bit
(5) Addr:0AH&0DH, Data:28H
(Addr:00H, D2)
(6)
(11)
(6) Addr:00H, Data:64H
PMMIN bit
(Addr:00H, D5)
PMHPL/R bits
(7) Addr:01H, Data:39H
(7)
(10)
(8) Addr:01H, Data:79H
(Addr:01H, D5-4)
HPMTN bit
Playback
(8)
(9)
(Addr:01H, D6)
HPL/R pins
HPL+/- pins
HPR+/- pins
HVCM pin
(9) Addr:01H, Data:39H
Normal Output
(10) Addr:01H, Data:09H
(11) Addr:00H, Data:40H
(12) Addr:0FH, Data:08H
Figure 77. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4373 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”
(3) Select output type of the headphone (HPBTL and PSEUDO bits “00”= Single-ended, “10”=Differential,
“01”=Pseudo cap-less)
(4) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC: PMDAC bit = “0” → “1”
When ALC bit is “1”, ALC operation starts from the gain set by AVL/R7-0 bits.
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”
Output voltage of headphone-amp is still VSS2.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
The rise time depends on HVDD and the capacitor value which connected with the MUTET pin. When
HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τr = 100ms(typ), 250ms(max).
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
The fall time depends on HVDD and the capacitor value which connected with the MUTET pin. When
HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τ f = 100ms(typ), 250ms(max).
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage changes
to GND, the pop noise occurs. It takes twice of τf that the common voltage changes to GND.
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC: PMDAC bit = “1” → “0”
(12) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
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■ Stop of Clock
Master clock can be stopped when DAC is not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 78. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 79. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
3. PLL Slave (MCKI pin)
Example
(1)
Audio I/F Format: MSB justified
PLL Reference clock: MCKI
BICK frequency: 64fs
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 80. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
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4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 81. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
5. EXT Master Mode
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format :MSB justified
Input MCKI frequency:1024fs
(1) Stop the external MCKI
Figure 82. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”.
■ Power down
Power supply current can also be shut down (typ. 1μA) by stopping clocks and setting PDN pin = “L”. When PDN pin =
“L”, the registers are initialized.
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[AK4373]
PACKAGE
32pin QFN (Unit: mm)
5.00 ± 0.10
0.40 ± 0.10
4.75 ± 0.10
24
17
16
4.75 ± 0.10
B
3.5
5.00 ± 0.10
25
32
1
1
3.5
0.50
+0.07
-0.05
32
C0.42
8
A
0.23
Exposed
Pad
9
0.85 ± 0.05
0.10 M AB
0.08 C
0.04
0.01+- 0.01
0.20
C
Note) The exposed pad on the bottom surface of the package must be open or connected to the ground.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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MARKING
AKM
AK4373
XXXXX
1
XXXXX : Date code identifier (5 digits)
REVISION HISTORY
Date (YY/MM/DD)
08/09/09
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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