AK4679 English Data Sheet

[AK4679]
AK4679
24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP
GENERAL DESCRIPTION
The AK4679 is a 24bit stereo CODEC and a built-in Microphone-Amplifier, Receiver-Amplifier, Mono
Class-D Speaker-Amplifier, Cap-less Class-G Headphone-Amplifier and Line-Amplifier as well as
HF/Audio DSP. The AK4679 features AKM DSP core to deal with hands free function for wide band and
dual PCM I/F in addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth
I/F. The playback features also include 5-band Parametric EQ and Dynamic Range Control; therefore the
AK4679 can automatically adjust the volume to a comfortable level that has no distortion and provides
great flexibility. The AK4679 is available in a 78pin BGA, utilizing less board space than competitive
offerings.
FEATURES
‹
CODEC&Amp block
1. Recording Function (Stereo CODEC)
• 4 Stereo Input Selectors
• 4 Stereo Inputs (Single-ended) or 3 Mono Input (Full-differential)
• MIC Amplifier: +24dB ~ −6dB, 3dB step
• 2 Output MIC Power Supplies
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• ADC CHARACTERISTICS: S/(N+D): 80dB, DR, S/N: 87dB (MIC-Amp=+18dB)
S/(N+D): 80dB, DR, S/N: 92dB (MIC-Amp=0dB)
• Stereo Digital MIC Interface
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 3-band Programmable Notch Filter
• Audio Interface Format: 24/16bit MSB justified, 24/16bit I2S, 16bit DSP Mode
2. Playback Function (Stereo CODEC)
• Digital Volume (+6dB ~ −57.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• Dynamic Range Control
• 5-band Parametric Equalizer
• Stereo Line Output (Selectable Full-differential / Single-ended)
• Mono Receiver-Amp
- BTL Output
- Output Power: 60mW @ 32Ω
- Analog Volume: +12 ~ −30dB & Mute, 3dB Step
• Cap-less Stereo Class-G Headphone-Amp
- Output Power: 25mW @ 32Ω, 45mW @ 16Ω
- Analog Volume: +6 ~ −62dB & Mute, 2dB Step
- Zero crossing Detection
- Pop Noise Free at Power-ON/OFF
• Mono Class-D Speaker-Amp
- BTL Output
- Short Protection Circuit
- Output Power: 1.1W @ 8Ω, SVDD=4.2V, THD+N = 10%
0.89W @ 8Ω, SVDD=4.2V, THD+N = 1%
- Analog Volume: +12 ~ −30dB & Mute, 3dB Step
- Pop Noise Free at Power-ON/OFF
• Audio Interface Format:
- 24/16bit MSB justified, 16bit LSB justified, 16/24bit I2S, 16bit DSP Mode
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3. Dual PCM I/F for Baseband & Bluetooth Interface
• Four sample Rate Converters (Up sample: up to x6: Down sample: down to x1/6)
• Sample Rate:
- PORTA (Mono): 8 ~ 16kHz
- PORTB (Stereo): 8 ~ 48kHz
• Digital Volume
• Slave Mode
• Audio Interface Format:
- 16bit Linear, 8bit A-law, 8bit μ-law
- Short/Long Frame, I2S, MSB justified
4. Power Management
5. Master Clock(Audio I/F):
(1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz,
24MHz, 25MHz, 26MHz, 27MHz (MCKI pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
6. Output Master Clock Frequencies(Audio I/F): 32fs/64fs/128fs/256fs
7. Sampling Frequency (Audio I/F)
• PLL Slave Mode (BICK pin): 8kHz ~ 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
8kHz ∼ 48kHz (256fs), 8kHz ~ 24kHz (512fs), 8kHz ~ 12kHz (1024fs)
8. Audio I/F: Master/Slave mode
‹
DSP block
9. Embedded DSP
- Flexible programming with built-in program and data memories
- Hardware accelerator
- Word length: 24bit (Data RAM 24bit floating point)
- Multiplier 20 x 20 Æ 40bit (double precision available)
- Divider 20 / 20 Æ 20bit
- ALU: 44bit arithmetic operation (with overflow margin 4bit)
24bit floating point arithmetic and logic operation
- Program RAM: 4096w x 36bit
- Coefficient RAM: 2048w x 20bit
- Data RAM: 2048w x 24bit (24bit floating point)
- Offset Register: 32w x 15bit
- Delay RAM: 16384w x 24bit (24bit floating point)
- 5625 steps at fs16KHz, 1875 steps at fs48KHz
- Internal clock generator
10. DSP Serial Audio Interface Format
- 24bit Left justified, I2S,
- 16/24 bit linear, 8bit A-law, 8bit µ-law PCM
- Sampling rate 8 KHz ~ 48 KHz
- Up/Down sampling rate converter for Port#2 (8KHz → 16KHz)
11. Operational, sleep, suspend mode
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‹
General
12. μP I/F: I2C Bus (Ver 1.0, 400kHz Fast Mode), SPI (DSP block only)
13. Ta = −30 ~ 85°C
14. Power Supply:
• SVDD (SPK/RCV/LINE-Amp):
3.0 ~ 5.5V
• AVDD (Analog):
1.7 ~ 2.0V
• DVDD (Digital Core):
1.7 ~ 2.0V
• PVDD (HP-Amp & Charge Pump):
1.7 ~ 2.0V
• TVDDA, TVDDE (Digital I/F):
1.6 ~ 3.6V
• VDDE (DSP Core)
1.1 ~ 1.3V
15. Package : 78pin FBGA(4.5 x 4.5 mm, 0.4mm pitch)
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■ Block Diagram
SVDD
VSS3
AVDD
VSS1
VCOM
PMMP2
MPWR
MPWR2
MIC Power
Supply
PMMP1
MPWR
MPWR1
MIC Power
Supply
MIC-Amp
PMADL
LIN1/IN1+
Internal
MIC
RIN1/IN1−
To ADC Lch
To ADC Rch
LIN2/IN2External
MIC
PMADR
RIN2/IN2+
LIN3/IN3+
RIN3/IN3−
LIN4
RIN4
LOUT/LOP
PMLO
From DAC Lch
From DAC Rch
Stereo Line Out
ROUT/LON
PMRO
PMHPL
HPL
Headphone Out
PMHPR
HPR
To HP-Amp
PVDD
PMRCV
RCP
Receiver Out
From PVDD pin
RCN
VEE
PMSPK
SPP
Speaker Out
To Headphone-Amp
Charge Pump
SPN
CPA
CNA
Class-D SPK-Amp
SPFIL
CNB
CPB
Figure 1. Analog Block Diagram
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DVDD
VSS2
VSS5
TVDDA
PMADL or PMADR
From Lch MIC-Amp
From Rch MIC-Amp
ADC
HPF1
SCLA
PMPFIL
bit
Control
Register
HPF2
SDAA
LPF
Stereo
Separation
PDNA
3-band
Notch
BICK
ALC
LRCK
MIX
SDTO
Audio
I/F
SDTI
PMDAL or PMDAR
To Lch Output
To Rch Output
DAC
S
E
L
DRC
SVOLA
PMEQ
PMDRC
S
E
L
DATT-A 5-band
SMUTE
EQ
MCKI
DASEL1-0
PLL
PMMIX
PMPLL
PMOSC
MIX1L
MIX1R
OSC
PMSRAO
MIX2A
SDOAD
SRCAO
MIX2B
SVB2-0
PMPCMA
MIX2C
Mono
PCM I/F
(PORTA)
SVOLB
DATT-B
SRCAI
BICKA
SYNCA
SDTOA
SDTIA
BVL6-0
PMSRAI
CVL6-0
DATT-C
PMPCMB
BICKB
PMSRBO
SDOBD
MIX3
SRCBO
BIVOL
SRCBI
BIV2-0
PCM I/F
(PORTB)
SYNCB
SDTOB
SDTIB
PMSRBI
Figure 2. Digital Block Diagram
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VSS4
PDNE
TVDDE
VDDE
TEST
SYNC1
PCM
BCLK1
Interface1
SDIN1
(Port#1)
SDOUT1
AKM
DSP
Core
DIN1
PCM
Interface2
DOUT2
DOUT4/GP1
SDOUT3/GP0
SDOUT2
PCM
Interface4
(Port#4)
SDOUT4/GP1
SDIN4
JX0
BCLK3/JX0
SDIN3
DIN4
JX1
BCLK2
SDIN2
DIN2
DOUT1
SYNC3/JX1
(Port#2)
SYNC2
PCM
Interface3
(Port#3)
WDT/CRC
DIN3
DOUT3/GP0
STO/RDY
RDY
I2CE
Control
Interface
CGU
(CLK
Gen
Unit)
SCLK/CAD0
SI/CAD1
DSPCLK
CSN/SCLE
Memory
SO/SDAE
Figure 3. DSP Block Diagram
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CP0, CP1
Pointer
DP0, DP1
Data RAM
Coefficient RAM
Delay RAM
16384w x 24-Bit
2048w x 24-Bit
2048w x 20-Bit
Offset Reg
32w x 15-Bit
DLP0, DLP1
CBUS(20-Bit)
DBUS(24-Bit)
MPX20
Micon I/F
MPX20
X
Control
PRAM
DEC
Y
Serial I/F
4096w x 36-Bit
Multiply
20 x 20 → 40-Bit
PC
Stack: 5 levels(max)
TMP
24-Bit
40-Bit
12 x 24-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
2 x 16/24-Bit
DIN4
2 x 16/24-Bit
DIN3
2 x 16/24-Bit
DIN2
2 x 16/24-Bit
DIN1
ALU
2 x 16/24-Bit
DOUT4
44-Bit
2 x 16/24-Bit
DOUT3
2 x 16/24-Bit
DOUT2
2 x 16/24-Bit
DOUT1
SHIFT
44-Bit
40-Bit
A
B
Overflow Margin: 4-Bit
40-Bit
DR0 ∼ 3
40-Bit
Accelerator
Over Flow Data
Generator
Division 20÷20→20
Peak Detector
Figure 4. DSP Core
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■ Ordering Guide
−30 ∼ +85°C
78pin BGA (0.4mm pitch) Black type
Evaluation board for AK4679
AK4679EG
AKD4679
■ Pin Layout Top View
Top View
9
8
7
6
5
4
3
2
1
A
9
8
7
6
5
LIN1/
IN1+/
DMDAT
RIN1/
CSN/
VSS1
IN1-/
SCLE
DMCLK
LOUT/ SCLK_
VCOM
LOP
CAD0
ROUT/
SI/
AVDD
LON
CAD1
SO/
MPWR1 MPWR2
SDAE
LIN2/
IN2-
RIN2/
IN2+
B
C
D
E
F
G
H
J
LIN3/
IN3+
HPR
PVDD
CNA
VSS5
CNB
RIN3/
IN3-
HPL
VEE
VEE
CPA
CPB
PDNE
RIN4
LIN4
PDNA
SDAA
VSS2
SYNC2
BCLK1
SCLA
SDTO
TVDDA
JX1/
SYNC3
SDIN1
SYNC1
LRCK
BICK
SDTOB
SDTI
SYNCB
MCKI
TEST
SDOUT3
SYNCA
/GP0
JX0/
STO/
BCLK3
RDY
4
RCP
RCN
SDOUT2
3
SVDD
VSS3
SDIN4
SDIN2
SDIN3
2
SPN
VSS3
I2CE
SDOUT4
/GP1
SDTIA
BCLK2
BICKA
BICKB
SDTOA
1
SVDD
SPP
SPFIL
TVDDE
DVDD
VSS4
VDDE
SDOUT1
SDTIB
A
B
C
D
E
F
G
H
J
Total 78pin
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PIN/FUNCTION
No.
Pin Name
Power Supply
A6
AVDD
A7
VCOM
A8
VSS1
E1
DVDD
J6
TVDDA
J7
VSS2
A1,A3 SVDD
B2,B3 VSS3
F9
PVDD
H9
VSS5
F8,G8 VEE
H8
CPA
G9
CNA
J8
CPB
J9
CNB
A5
MPWR1
B5
MPWR2
Audio Interface
J3
MCKI
J5
BICK
H5
LRCK
J4
SDTI
H6
SDTO
PCM Interface
G2
BICKA
G4
SYNCA
E2
SDTIA
J2
SDTOA
H2
BICKB
H3
SYNCB
J1
SDTIB
H4
SDTOB
Analog Input
LIN1
C9
IN1+
DMDAT
RIN1
C8
IN1−
DMCLK
LIN2
A9
IN2RIN2
B9
IN2+
LIN3
D9
IN3+
RIN3
D8
IN3−
F7
LIN4
E7
RIN4
I/O
O
O
I
O
I
O
O
Function
Analog Power Supply Pin, 1.7 ∼ 2.0V
Common Voltage Output Pin
Ground 1 Pin
Digital Core Power Supply Pin, 1.7 ~ 2.0V
Digital I/O Power Supply Pin, 1.6 ∼ 3.6V
Ground 2 Pin
Analog Amp Power Supply Pin, 3.0 ~ 5.5V
Ground 3 Pin
HP-Amp & Charge Pump Power Supply Pin
Ground 5 Pin
Charge Pump Circuit Negative Voltage Output Pin
Positive Charge Pump Capacitor Terminal A Pin
Negative Charge Pump Capacitor Terminal A Pin
Positive Charge Pump Capacitor Terminal B Pin
Negative Charge Pump Capacitor Terminal B Pin
MIC Power Supply 1 Pin
MIC Power Supply 2 Pin
I
I/O
I/O
I
O
External Master Clock Input Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
I
I
I
O
I
I
I
O
Serial Data Clock A Pin
Sync Signal A Pin
Serial Data Input A Pin
Serial Data Output A Pin
Serial Data Clock B Pin
Sync Signal B Pin
Serial Data Input B Pin
Serial Data Output B Pin
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input, DMIC bit = “0”)
Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input, DMIC bit = “0”)
Digital Microphone Data Input Pin (DMIC bit = “1”)
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input, DMIC bit = “0”)
Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input, DMIC bit = “0”)
Digital Microphone Clock Pin (DMIC bit = “1”)
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Lch Analog Input 4 Pin
Rch Analog Input 4 Pin
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PIN/FUNCTION (Cont.)
No.
Pin Name
Analog Output
ROUT
B6
LON
LOUT
B7
LOP
A4
RCP
B4
RCN
E8
HPL
E9
HPR
B1
SPP
A2
SPN
I/O
NO
Pin Name
DSP I/O
G1 VDDE
D1 TVDDE
F1 VSS4
I/O
Function
Rch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output)
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Lch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output)
Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Receiver-Amp Positive Output Pin
Receiver-Amp Negative Output Pin
Lch Headphone-Amp Output Pin
Rch Headphone-Amp Output Pin
Speaker-Amp Positive Output Pin
Speaker-Amp Negative Output Pin
Speaker-Amp Filter Pin
C1
SPFIL
O
Connect 2.2nF between SPFIL pin and VSS1.
Control Interface for Audio Block
G6
SCLA
I
Control Data Clock Pin
H7
SDAA
I/O Control Data Input Pin
Power-Down Mode Pin
G7
PDNA
I
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
Note 1. All input pins except analog input pins (LIN1/IN1+, RIN1/IN1−, LIN2/IN2-, RIN2/IN2+, LIN3/IN3+,
RIN3/IN3−, LIN4, RIN4) must not be allowed to float.
I/O pins (LRCK, BICK and SDAA pins) should be processed appropriately.
D7
PDNE
G3
STO
RDY
G5
SYNC1
F6
BCLK1
F5
H1
D6
F2
D3
C4
SDIN1
SDOUT1
SYNC2
BCLK2
SDIN2
SDOUT2
SYNC3
JX1
BCLK3
JX0
SDIN3
SDOUT3
GP0
SDIN4
D5
F3
E3
F4
C3
O
O
O
O
O
O
O
O
O
O
Function
-
Core Power Supply Pin 1.2V
I/O power Supply Pin 1.6∼3.6V
Ground pin 0V
Power-Down Mode Pin
I “H”: Power-up, “L”: Power-down, reset the control register.
The AK4679 DSP must be reset once upon power-up.
Status Output Pin
(STRDY bit = “0”)
O
Data Write Ready output pin for control I/F
(STRDY bit = “1”)
I Frame Sync 1 pin
Serial Data Clock 1 Pin
I
AK4679 DSP goes into stanby state when BCLK1 is not present.
Serial
Data Input 1 Pin
I
O Serial Data Output 1 Pin
O Frame Sync 1 pin
O Serial Data Clock 2 Pin
I Serial Data Input 2 Pin
O Serial Data Output 2 Pin
Frame Sync 3 pin
(SELPT bit = “1”)
I
Conditional Jump 1 Pin
(SELPT bit = “0”)
Serial Data Clock 3 Pin
(SELPT bit = “1”)
I
Conditional Jump 0 Pin
(SELPT bit = “0”)
I Serial Data Input 3 Pin
Serial Data Output 3 Pin
(SELDO3 bit = “0”)
O
DSP Programmable output 0 Pin
(SELDO3 bit = “1”)
I Serial Data Input 4 Pin
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Serial Data Output 4 Pin
(SELDO4 bit = “0”)
SDOUT4
O
GP1
DSP Programmable output 1 Pin
(SELDO4 bit = “1”)
C2 I2CE
I Control Interface Mode Select Pin for DSP Block “H”: I2CE, “L”: SPI
Serial Clock Input pin
SPI (I2CE pin = “L”)
SCLK
C7
I
CAD0
Slave Address 0 Input pin
I2C (I2CE pin = “H”)
Chip select pin
SPI (I2CE pin = “L”)
CSN
B8
I
SCLE
Control Interface clock input pin
I2C (I2CE pin = “H”)
SPI (I2CE pin = “L”)
SO
O Serial data output pin
C5
SDAE
I/O Control Interface input/output acknowledge pin
I2C (I2CE pin = “H”)
Serial data input pin
SPI (I2CE pin = “L”)
SI
C6
I
CAD1
Slave Address 1 Input pin
I2C(I2CE pin = “H”)
E4 TEST
I Test pin (pull-down resistor) must be connected to VSS4.
Note 2. All input pins must not be allowed to float.
Note 3. I2CE and CAD0/1 pins must be fixed to “L” (VSS4) or “H” (TVDDE).
D2
■ Handling of Unused Pin on the System
The unused input and output pins on the system should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR1, MPWR2, SPP, SPN, RCP, RCN, HPL,
HPR, ROUT/LON, LOUT/LOP, RIN4, LIN4,
RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-,
RIN1/IN1−, LIN1/IN1+, CPA, CNA, CPB, CNB,
VEE, SPFIL
SDTO, SDTOA, SDTOB
STO/RDY, SDOUT3/GPO, SDOUT4/GP1
MCKI, SDTI, SDTIA, SDTIB, BICKA, SYNCA,
BICKB, SYNCB
Setting
These pins should be open.
These pins should be open.
These pins should be connected to VSS2.
LRCK, BICK
These pins should be connected to VSS2
and M/S bit should be set to “0”.
SYNC1, BCLK1, SDIN3, SDIN4, SYNC3/JX1,
BCLK3/JX0, TEST
These pins should be connected to VSS4
■ Pin States in DSP Power-down Mode
The table below shows pin states when the PDNE pin= “L”.
NO
Pin Name
I/O
Pin state
Low
STO
G3
O
RDY
H1 SDOUT1
O SDIN2 data output
D6 SYNC2
O SYNC1 data output
F2 BCLK2
O BCLK1 data output
C4 SDOUT2
O SDIN1 data output
SDIN4 data output
SDOUT3
F4
O
GP0
SDIN3 data output
SDOUT4
D2
O
GP1
SO
O Low level (I2CE pin = “L”: SPI)
C5
SDAE
I/O Hi-z
(I2CE pin = “H” :I2C)
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ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4=VSS5=0V; Note 4, Note 5)
Parameter
Symbol
min
max
Unit
Power Supplies:
Analog
AVDD
2.5
V
−0.3
SPK/RCV/LINE-Amp
SVDD
6.0
V
−0.3
HP-Amp & Charge Pump
PVDD
2.5
V
−0.3
Digital Core
DVDD
2.5
V
−0.3
Digital I/O (Codec)
TVDDA
6.0
V
−0.3
DSP Core
VDDE
-0.3
1.6
V
Digital I/O (DSP)
TVDDE
-0.3
4.1
V
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage (Note 6)
VINA
AVDD + 0.3
V
−0.3
Digital Input Voltage (Note 8)
VIND1
TVDD + 0.3
V
−0.3
Digital Input Voltage (Note 7)
VINDE
TVDDE + 0.3
V
−0.3
Ambient Temperature (powered applied)
Ta
85
−30
°C
Storage Temperature
Tstg
150
−65
°C
Maximum Power Dissipation
Pd
1
W
−
Note 4. All voltages with respect to ground.
Note 5. VSS1 to VSS5 must be connected to the same analog ground plane.
Note 6. RIN4, LIN4, RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-, RIN1/IN1−, LIN1/IN1+ pins
Note 7. SDTI, LRCK, BICK, MCKI, PDNA, BICKA, SYNCA, SDITA, BICKB, SYNCB, SDTIB, SCLA and SDAA
pins. Pull-up resistors at SDAA and SCLA pins should be connected to (TVDDA+0.3)V or less voltage.
Note 8. SYNC1/2/3, BCLK1/2/3, SDIN1-4, SDOUT1-4, I2CE, STO/RDY, SCLK/CAD, SI/CAD0, CSN/SCLE and
SO/SDAE. Pull-up resistors at SDAE and SCLE pins should be connected to (TVDDE+0.3)V or less voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
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RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=VSS5=0V; Note 4)
Parameter
Symbol
min
typ
max
Unit
Power
Analog
AVDD
1.7
1.8
2.0
V
Supplies
SPK/RCV/LINE-Amp
SVDD
3.0
4.2
5.5
V
(Note 9) HP-Amp & Charge Pump
PVDD
1.7
1.8
2.0
V
Digital Core
DVDD
1.7
1.8
2.0
V
Digital I/O (Codec)
TVDDA
1.6
1.8
3.6
V
DSP Core
VDDE
1.1
1.2
1.3
V
Digital I/O (DSP)
TVDDE
1.6
1.8
3.6
V
Difference
AVDD – PVDD
0.2
V
−0.2
−
AVDD – DVDD
0.2
V
−0.2
−
PVDD – DVDD
0.2
V
−0.2
−
Note 4. All voltages with respect to ground.
Note 9. The power-up sequence between supplies (AVDD, SVDD, PVDD, DVDD or TVDD) is not critical. The PDNA
pin should be held “L” when power supplies are tuning on. The PDNA pin is allowed to be “H” after all power
supplies are applied and settled. The AK4679 should be operated along the recommended power-up/down
sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at speaker
output, receiver output, headphone outputs and line outputs.
* AVDD, PVDD, DVDD, VDDE, TVDDE and TVDDA can be powered OFF (Power is not applied)
when SVDD is powered ON (Power is applied) with both PDNA and PDNE pin “L”. When
turning on AVDD, PVDD, DVDD, VDDE, TVDDE and TVDDA again in this case, the PDNA pin
must be “L” until all other power supplies are powered ON. Also, when turning off AVDD,
PVDD, DVDD, VDDE, TVDDE and TVDDA both the PDNA and PDNE pin must be “L” before
other power supplies start to turn off.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1402-E-06
2013/02
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[AK4679]
ANALOG CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD=PVDD= DVDD=TVDDA= TVDDE=1.8V, SVDD=4.2V, VDDE=1.2V;
VSS1=VSS2=VSS3=VSS4 =VSS5 =0V; Signal Frequency=1kHz; 24bit Data; fs=44.1kHz, BICK=64fs; Measurement
Bandwidth=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins
Input Resistance
17
25
38
kΩ
Gain (Note 10)
Gain Setting
+24
dB
−6
Step Width
3
dB
MIC Power Supply: MPWR1, MPWR2 pin
Output Voltage (Note 11)
2.3
2.5
2.7
V
Load Resistance
1.0
kΩ
Load Capacitance
30
pF
Output Noise Level (A-weighted)
dBV
−107
PSRR (Note 12)
217Hz
100
dB
1kHz
100
dB
Stereo ADC Analog Input Characteristics:
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins(Single-ended Input) → Stereo ADC → Programmable Filter
(IVOL=0dB, EQ=ALC=OFF) → SDTO
Resolution
24
Bits
(Note 14)
0.204
0.227
0.250
Vpp
Input Voltage (Note 13)
1.62
1.8
1.98
Vpp
(Note 15)
(Note 14)
69
80
dB
S/(N+D) (−1dBFS)
80
dB
(Note 15)
(Note 14)
76
87
dB
D-Range (−60dBFS, A-weighted)
92
dB
(Note 15)
(Note 14)
76
87
dB
S/N (A-weighted)
92
dB
(Note 15)
(Note 14)
75
90
dB
Interchannel Isolation (Note 16)
100
dB
(Note 15)
(Note 14)
0
0.8
dB
Interchannel Gain Mismatch (Note 16)
0
0.8
dB
(Note 15)
Note 10. In case of full-differential input, MGAIN (min)=-3dB
Note 11. In case of MICL1 bit or MICL2 bit = “0”. Output voltage is proportional to AVDD (typ. 1.39 x AVDD V).
MICL1 bit or MICL2 bit = “1”: typ. 1.56 x AVDD V
Note 12. PSRR is referred to SVDD with 500mVpp sine wave.
Note 13. Input voltage which means ADC full-scale voltage is proportional to AVDD voltage.
Single-ended Input: Vin = 1.0 x AVDD Vpp(typ).
Full-Differential Input: Vin = (IN+) – (IN–) = 1.0 x AVDD Vpp(typ).
IN+ = 0.5 x AVDD(typ), IN– = 0.5 x AVDD(typ)
Pseudo-Differential Input: Vin = (IN+) – (IN–) = 1.0 x AVDD Vpp (typ).
IN+ = 1.0 x AVDD(typ), IN– = 0V (IN– pin should be connected to VSS1.)
Note 14. MGNL3-0=MGNR3-0 bits = “BH” (+18dB).
In case of Full-differential, S/(N+D) =75dB, DR=S/N=81dB
Note 15. MGNL3-0=MGNR3-0 bits = “5H” (0dB).
In case of Full-differential, S/(N+D) =79dB, DR=S/N=91dB
Note 16. This is a value between Lch and Rch of each input.
MS1402-E-06
2013/02
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[AK4679]
Parameter
min
typ
max
Unit
Stereo DAC Characteristics:
Resolution
24
Bits
Stereo Line Output Characteristics: Stereo DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
LVL=0dB, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 17)
1.62
1.8
1.98
Vpp
S/(N+D) (0dBFS)
70
80
dB
S/N (A-weighted)
82
92
dB
Interchannel Isolation
85
95
dB
Interchannel Gain Mismatch
0
0.8
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
PSRR (Note 18)
217Hz
75
dB
1kHz
75
dB
Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB, LVL=0dB,
LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 19)
3.24
3.6
3.96
Vpp
S/(N+D) (0dBFS)
73
dB
S/N (A-weighted)
95
dB
Load Resistance (LOP/LON pins, respectively)
10
kΩ
(Note 20)
Load Capacitance (LOP/LON pins, respectively)
30
pF
(Note 21)
PSRR (Note 18)
217Hz
70
dB
1kHz
70
dB
Mono Receiver-Amp Output Characteristics:
DAC(Stereo, Note 22) → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, RCVG=−6dB, RL=32Ω, BTL; unless
otherwise specified.
Output Voltage (Note 23)
0dBFS
1.76
1.96
2.16
Vpp
0dBFS, RCVG=0dB
3.91
Vpp
S/(N+D)
0dBFS
40
59
dB
0dBFS, RCVG=0dB
55
dB
S/N (A-weighted) (DAC Æ RCP/RCN pins)
84
94
dB
dBV
Output Noise Level (A-weighted, RCVG = −9dB)
−100
Load Resistance
32
Ω
Load Capacitance (Note 21)
30
pF
PSRR (Note 18)
217Hz
75
dB
1kHz
75
dB
Note 17. Output voltage is proportional to AVDD voltage. Vout = 1.0 x AVDD Vpp(typ)
Note 18. PSRR is referred to SVDD with 200mVpp sine wave.
Note 19. Output voltage is proportional to AVDD voltage. Vout = (LOP) – (LON) = 2.0 x AVDD Vpp(typ)
Note 20. This is a resistance value between output pin and VSS1. When a resistor is connected between output pins, load
resistance for each output pin is half. Therefore, it is necessary to decide load resistance in consideration of
these.
Note 21. This is a capacitance value between output pin and VSS1. When a capacitor is connected between output pins,
load capacitance for each output pin doubles. Therefore, it is necessary to decide load capacitance in
consideration of these.
Note 22. Input signal of left and right channels is same phase and level.
Note 23. Output voltage is proportional to AVDD voltage. Vout = (RCP) – (RCN) = 2.17 x AVDD Vpp(typ)
Po = 15mW @ 32Ω, Vout = 1.96Vpp. Po = 60mW @ 32Ω, Vout = 3.91Vpp.
MS1402-E-06
2013/02
- 15 -
[AK4679]
Parameter
min
typ
max
Unit
Headphone-Amp Characteristics: DAC(Stereo, Note 22) → HPL/HPR pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
HPG=0dB, RL=32Ω
Output Voltage (Note 24)
1.44
1.6
1.76
Vpp
0dBFS, RL = 32Ω, HPG=−4dB
1.6
Vpp
0dBFS, RL = 16Ω, HPG=−4dB
2.5
Vpp
0dBFS, RL = 32Ω, HPG=0dB
0.85
Vrms
0dBFS, RL = 16Ω, HPG=0dB
S/(N+D)
50
73
dB
0dBFS, RL = 32Ω, HPG=−4dB
67
dB
0dBFS, RL = 16Ω, HPG=−4dB
73
dB
0dBFS, RL = 32Ω HPG=0dB
20
dB
0dBFS, RL = 16Ω HPG=0dB
S/N (A-weighted)
85
95
dB
dBV
Output Noise Level (A-weighted, HPG=−14dB)
−106
Interchannel Isolation
60
80
dB
Interchannel Gain Mismatch
0
0.8
dB
Load Resistance
16
32
Ω
Load Capacitance (Note 25)
300
pF
PSRR (Note 26)
217Hz
70
dB
1kHz
60
dB
0
1
mV
DC-offset (HPG ≤ −4dB)
−1
Speaker-Amp Characteristics: DAC(stereo, Note 27) → SPP/SPN pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
SPKG=−6dB, RL=8Ω + 10μH
Output Power
SVDD=5.0V, THD+N = 10%
1.57
W
SVDD=4.2V, THD+N = 10%
1.1
W
SVDD=4.2V, THD+N = 1%
0.89
W
SVDD=3.7V, THD+N = 1%
0.69
W
5.0
5.4
6.2
Vpp
Output Voltage (−3dBFS) (Note 28)
S/(N+D) (SVDD=3.7V, Po=0.35W)
40
59
dB
Output Noise Level (A-weighted) (Note 29)
dBV
−82
−73
Load Resistance
8
Ω
Load Capacitance (Note 25)
300
pF
PSRR (Note 30)
217Hz
63
dB
1kHz
63
dB
DC-offset
0
10
mV
−10
Current Limit (Note 31)
40
80
mA
Note 24. The Output voltage is proportional to AVDD voltage. Vout = 1.4 x AVDD Vpp(typ).
Po = 10mW @ 32Ω, Vout = 1.6Vpp. Po = 25mW @ 32Ω, Vout = 2.5Vpp.
Po = 20mW @ 16Ω, Vout = 1.6Vpp. Po = 45mW @ 16Ω, Vout = 0.85Vrms.
Note 25. Load Capacitance for VSS1.
Note 26. PSRR is referred to PVDD with 200mVpp sine wave.
Note 27. Input signal of left and right channels is same phase and level.
Note 28. Output voltage is proportional to AVDD voltage. Vout = (SPP) – (SPN) = 3.0 x AVDD Vpp(typ).
Note 29. In case of mono signal input (e.g. Lch only) and SPKG=0dB, output noise level is -84dBV.
Note 30. PSRR is referred to SVDD with 200mVpp sine wave.
Note 31. The average current between SVDD and VSS3 when the SPP and SPN pins are shorted and output power is
890mW.
MS1402-E-06
2013/02
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[AK4679]
Parameter
Stereo Line Output Volume Characteristics:
Gain Setting
Step Width
Headphone Output Volume Characteristics:
Gain Setting
Step Width
Gain: +6 ~ −40dB
Gain: −40 ~ −62dB
Speaker Output Volume Characteristics:
Gain Setting
Step Width
Receiver Output Volume Characteristics:
Gain Setting
Step Width
min
typ
max
Unit
-9
1
3
+6
5
dB
dB
−62
1
-
2
2
+6
3
-
dB
dB
dB
−30
1
3
+12
5
dB
dB
−30
1
3
+12
5
dB
dB
MS1402-E-06
2013/02
- 17 -
[AK4679]
Parameter
min
typ
max
Unit
Power Supply Current:
Power Up (PDNE and PDNA pin = “H”, All Circuits Power-up)
AVDD + DVDD + PVDD +
(Note 32)
6.2
mA
TVDDA +TVDDE
9.6
14.4
mA
(Note 33)
SVDD (No Load)
(Note 32)
3.5
mA
4.2
6.3
mA
(Note 33)
VDDE
(Note 36)
3.1
mA
Power Down (PDNA pin = PDNE pin = “L”) (Note 34)
AVDD + PVDD + DVDD + TVDDA
1
10
μA
+TVDDE+ SVDD
SVDD (Note 35)
0
10
μA
VDDE
2.4
8
μA
Note 32. EXT Slave Mode, fs=44.1kHz, No input, No load, PMADL = PMADR = PMDAL = PMDAR = PMPFIL =
PMEQ = PMDRC = PMLO = PMRO = PMHPL = PMHPR = PMSPK = PMRCV = PMVCM bits = “1”, PMPLL
= PMMP1 = PMMP2 = M/S = PMOSC = PMMIX = PMSRAI = PMSRAO = PMSRBI = PMSRBO = PMPCMA
= PMPCMB bits = “0”.
AVDD= 3.9mA (typ), DVDD= 1.4mA (typ), PVDD= 0.75mA (typ), SVDD=3.5mA (typ), TVDD = 0.1mA
(typ).
Note 33. PLL Master Mode, Audio I/F sampling frequency =44.1kHz, PCM I/F A sampling frequency =16kHz, PCM I/F
B sampling frequency = 8kHz, No input, No load, PMADL = PMADR = PMDAL = PMDAR = PMPFIL =
PMEQ = PMDRC = PMLO = PMRO = PMHPL = PMHPR = PMSPK = PMRCV = PMVCM = PMPLL =
PMMP1 = PMMP2 = M/S = PMOSC = PMMIX = PMSRAI = PMSRAO = PMSRBI = PMSRBO = PMPCMA
= PMPCMB bits = “1”. PLL Reference Clock = MCKI = 11.2896MHz. In this case, output current of the
MPWR1 and MPWR2 pins are 0mA.
AVDD= 4.6mA (typ), DVDD= 4.0mA (typ), PVDD= 0.78mA (typ), SVDD=4.2mA (typ), TVDD = 0.2mA (typ)
Note 34. All digital input pins are fixed to each supply pin TVDDA, TVDDE or VSS2, VSS4.
Note 35. AVDD, DVDD, PVDD, TVDDA, VDDE and TVDDE are powered OFF.
Note 36. fs=8 kHz 16 bit (FSD bits=0h, LAW bits = 0h, DIFD bit = 3h, TESTC bits = 1h, DSP running with programmed
connecting DIN1 with DOUT2 and DIN2 with DOUT1.
■ Power Consumption for Each Operation Mode
Condition: Ta=25°C; AVDD=DVDD=PVDD=TVDD =1.8V, SVDD=4.2V; VDEE=1.2V,
VSS1=VSS2=VSS3=VSS4=VSS5=0V; fs=44.1kHz; fs2=16kHz, fs3=8kHz, External Slave Mode,
BICK=64fs; No data input, Receiver / Speaker / Headphone = No Load.
Mode
AVDD
[mA]
1.93
1.27
0.82
1.22
1.75
DVDD+PVDD
[mA]
TVDD
[mA]
SVDD
[mA]
0.003
0.9
0.003
1.3
1.35
Total Power
[mW]
5.0
6.9
3.7
8.5
9.4
LIN1/RIN1 Æ ADC (Note 37)
0.74
0.1
DAC Æ Lineout (Note 38)
0.46
0.02
DAC Æ HP (Note 39)
1.21
0.02
DAC Æ RCV (Note 40)
0.44
0.02
DAC Æ SPK (Note 41)
0.44
0.02
PCM I/F A Æ PCM I/F B &
0.21
1.19
0.1
0.003
2.7
PCM I/F B Æ PCM I/F A (Note 42)
Note 37. PMVCM = PMADL = PMADR bits = “1” , PFSDO bit = “0”
Note 38. PMVCM = PMDAL = PMDAR = PMLO = PMRO bits = “1” , DASEL1-0 bits = “10”
Note 39. PMVCM = PMDAL = PMDAR = PMHPL = PMHPR bits = “1” , DASEL1-0 bits = “10”
Note 40. PMVCM = PMDAL = PMDAR = PMRCV bits = “1” , DASEL1-0 bits = “10”
Note 41. PMVCM = PMDAL = PMDAR = PMSPK bits = “1” , DASEL1-0 bits = “10”
Note 42. PMVCM = PMOSC = PMPCMA = PMSRAI = PMSRAO = PMPCMB = PMSRBI = PMSRBO bits = “1”
Table 1. Power Consumption for Each Operation Mode (typ)
MS1402-E-06
2013/02
- 18 -
[AK4679]
SRC CHARACTERISTICS
(Ta=25°C; AVDD=PVDD= DVDD=TVDDA=TVDDE =1.8V, SVDD=4.2V, VDDE=1.2V;
VSS1=VSS2=VSS3=VSS4 =VSS5 =0V; Signal Frequency=1kHz; 16bit Data; Measurement Bandwidth=20Hz ∼
FSO/2kHz; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
SRC Characteristics (SRCAI): SDTIA Æ SRCAI Æ SDTO
Resolution
16
Bits
Input Sample Rate
FSI
8
16
kHz
Output Sample Rate
FSO
8
48
kHz
THD+N (Input = 1kHz, −1dBFS, Note 43)
FSO/FSI = 44.1kHz/8kHz
−88
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 43)
FSO/FSI = 44.1kHz/8kHz
98
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/2
6
SRC Characteristics (SRCAO): SDTI Æ SRCAO Æ SDTOA
Resolution
16
Bits
Input Sample Rate
FSI
8
48
kHz
Output Sample Rate
FSO
8
16
kHz
THD+N (Input = 1kHz, −1dBFS, Note 43)
FSO/FSI = 8kHz/44.1kHz
−75
dB
FSO/FSI = 16kHz /8kHz
−88
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 43)
FSO/FSI = 8kHz/44.1kHz
100
dB
FSO/FSI = 16kHz /8kHz
99
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
2
SRC Characteristics (SRCBI, SRCBO): SDTI Æ SRCBO Æ SDTOB, SDTIB Æ SRCBI Æ SDTO
Resolution
16
Bits
Input Sample Rate
FSI
8
48
kHz
Output Sample Rate
FSO
8
48
kHz
THD+N (Input = 1kHz, −1dBFS, Note 43)
FSO/FSI = 8kHz/44.1kHz
−75
dB
FSO/FSI = 44.1kHz/8kHz
−88
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 43)
FSO/FSI = 8kHz/44.1kHz
100
dB
FSO/FSI = 44.1kHz/8kHz
99
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
6
Note 43. Measured by Audio Precision System Two Cascade.
MS1402-E-06
2013/02
- 19 -
[AK4679]
FILTER CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD = PVDD =DVDD=1.7 ∼ 2.0V; SVDD=3.0 ∼ 5.5V, TVDDA=TVDDE =1.6 ∼ 3.6V,
VDDE=1.1~1.3V; fs=44.1kHz; Programmable Filter=OFF)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 44)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband (Note 44)
SB
26.1
kHz
Passband Ripple
PR
dB
±0.16
Stopband Attenuation
SA
73
dB
Group Delay (Note 45)
GD
20
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF): HPFC1-0 bits = “00”
Frequency Response
FR
3.4
Hz
−3.0dB
10
Hz
−0.5dB
22
Hz
−0.1dB
DAC Digital Filter (LPF):
Passband (Note 44)
PB
0
20.0
kHz
±0.05dB
22.05
kHz
−6.0dB
Stopband (Note 44)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.05
Stopband Attenuation
SA
54
dB
Group Delay (Note 45)
GD
25
1/fs
DAC Digital Filter (LPF) + SCF + SMF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
Note 44. The passband and stopband frequencies scale with fs (system sampling rate).
For example, DAC is PB=0.454 x fs (@±0.05dB). Each response refers to that of 1kHz.
Note 45. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
24-bit data of both channels from the input register to the output register of the ADC. This time includes group
delay of the HPF and Programmable filter. For the DAC, this time is from setting the 24-bit data of both channels
from the input register to the output of analog signal and includes selector block (SDMIN, PFMXL/R and
SRMXL/R), DRC, 5-band EQ and DATT-A. For the signal through the programmable filters, group delay is
increased 4/fs at Playback Mode from the value above if there is no phase changed by the IIR filter.
MS1402-E-06
2013/02
- 20 -
[AK4679]
FILTER CHARACTERISTICS (SRC)
(Ta=25°C; AVDD = PVDD =DVDD=1.7 ∼ 2.0V; SVDD=3.0 ∼ 5.5V, TVDDA=TVDDE =1.6 ∼ 3.6V,
VDDE=1.1~1.3V; Programmable Filter=OFF)
Parameter
Symbol
min
typ
max
Unit
Digital Filter
Passband −0.23dB 0.985 ≤ FSO/FSI ≤ 6.000
PB
0
0.4583FSI
kHz
PB
0
0.4167FSI
kHz
−0.20dB 0.905 ≤ FSO/FSI < 0.985
PB
0
0.3104FSI
kHz
−0.13dB 0.714 ≤ FSO/FSI < 0.905
PB
0
0.2813FSI
kHz
−0.11dB 0.656 ≤ FSO/FSI < 0.714
PB
0
0.2167FSI
kHz
−0.10dB 0.492 ≤ FSO/FSI < 0.656
PB
0
0.1948FSI
kHz
−0.09dB 0.452 ≤ FSO/FSI < 0.492
PB
0
0.1458FSI
kHz
−0.07dB 0.357 ≤ FSO/FSI < 0.452
PB
0
0.1271FSI
kHz
−0.07dB 0.324 ≤ FSO/FSI < 0.357
PB
0
0.0729FSI
kHz
−0.06dB 0.226 ≤ FSO/FSI < 0.324
PB
0
0.0625FSI
kHz
−0.17dB 0.1667 ≤ FSO/FSI < 0.226
Stopband
SB
0.5417FSI
kHz
0.985 ≤ FSO/FSI ≤ 6.000
SB
0.5021FSI
kHz
0.905 ≤ FSO/FSI < 0.985
SB
0.3958FSI
kHz
0.714 ≤ FSO/FSI < 0.905
SB
0.3667FSI
kHz
0.656 ≤ FSO/FSI < 0.714
SB
0.3021FSI
kHz
0.492 ≤ FSO/FSI < 0.656
SB
0.2802FSI
kHz
0.452 ≤ FSO/FSI < 0.492
SB
0.2313FSI
kHz
0.357 ≤ FSO/FSI < 0.452
SB
0.2125FSI
kHz
0.324 ≤ FSO/FSI < 0.357
SB
0.1583FSI
kHz
0.226 ≤ FSO/FSI <0.324
SB
0.1271FSI
kHz
0.1667 ≤ FSO/FSI < 0.226
87.0
Stopband
SA
dB
0.985 ≤ FSO/FSI ≤ 6.000
Attenuation
88.0
SA
dB
0.905 ≤ FSO/FSI < 0.985
87.5
SA
dB
0.714 ≤ FSO/FSI < 0.905
86.8
SA
dB
0.656 ≤ FSO/FSI < 0.714
86.4
SA
dB
0.492 ≤ FSO/FSI < 0.656
86.0
SA
dB
0.452 ≤ FSO/FSI < 0.492
86.6
SA
dB
0.357 ≤ FSO/FSI < 0.452
86.1
SA
dB
0.324 ≤ FSO/FSI < 0.357
85.7
SA
dB
0.226 ≤ FSO/FSI < 0.324
72.8
SA
dB
0.1667 ≤ FSO/FSI < 0.226
Group Delay (Note 46)
PCM I/F A Æ PCM I/F B (PMMIX bit=“0”)
GD
30/fs2+10.5/fs3
s
29.5/fs2+37.5/fs3
(PMMIX bit=“1”)
GD
s
+9.5/fs
PCM I/F B Æ PCM I/F A (PMMIX bit=“0”)
GD
30/fs2+10.5/fs3
s
29.5/fs2+37.5/fs3
(PMMIX bit=“1”)
GD
s
+9.5/fs
PCM I/F A Æ SDTO
GD
29.5/fs2+11.5/fs
s
PCM I/F B Æ SDTO
GD
29.5/fs2+12.5/fs
s
PCM I/F A Æ 5-band EQ Æ DATT-A Æ DRC
GD
29.5/fs2+32.5/fs
s
Æ DAC Digital Output (Note 47)
PCM I/F B Æ 5-band EQ Æ DATT-A Æ DRC
GD
29.5/fs2+33.5/fs
s
Æ DAC Digital Output (Note 47)
Note 46. This value is the time from the rising edge of LRCK, SYNCA or SYNCB after data is input to rising edge of
LRCK after data is output, when LRCK, SYNCA or SYNCB for Output data corresponds with SYNCA or
SYNCB for Input.
fs: LRCK Frequency, fs2: SYNCA Frequency, fs3: SYNCB Frequency.
Note 47. This value includes group delay of DAC digital filter.
MS1402-E-06
2013/02
- 21 -
[AK4679]
DC CHARACTERISTICS
(Ta=25°C; AVDD = PVDD =DVDD=1.7 ∼ 2.0V, VDDE=1.2V; SVDD=3.0 ∼ 5.5V, TVDDA =TVDDE=1.6 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Unit
High-Level Input Voltage 2.2V≤TVDDA≤3.6V
VIH1
70%TVDDA
V
(Note 48) 1.6V≤TVDDA<2.2V
VIH1
80%TVDDA
V
Low-Level Input Voltage 2.2V≤TVDDA≤3.6V
VIL1
30%TVDDA
V
(Note 48) 1.6V≤TVDDA<2.2V
VIL1
20%TVDDA
V
High-Level Output Voltage
VOH1
V
(Note 49)(Iout=−200μA)
TVDDA−0.2
Low-Level Output Voltage
V
VOL1
0.2
V
(Note 49)(Iout=200μA)
VOL2
0.4
V
(SDAA pin, 2.0V≤TVDDA≤3.6V: Iout=3mA)
VOL2
20%TVDDA
V
(SDAA pin, 1.6V≤TVDDA<2.0V: Iout=3mA)
Input Leakage Current (Note 50)
Iind
±2
μA
Digital MIC Interface (DMDAT pin Input; DMIC bit = “1”)
High-Level Input Voltage
VIH3
65%AVDD
V
Low-Level Input Voltage
VIL3
35%AVDD
V
Digital MIC Interface (DMCLK pin Output; DMIC bit = “1”)
High-Level Output Voltage
(Iout=−80μA)
VOH3
AVDD-0.4
V
Low-Level Output Voltage
(Iout= 80μA)
VOL3
0.4
V
Input Leakage Current
(Note 50)
Iin
±10
μA
Note 48. BICK, LRCK, SDTI, MCKI, PDNA, BICKA, SYNCA, SDTIA, BICKB, SYNCB, SDTIB, SCLA and SDAA
pins.
Note 49. BICK, LRCK SDTO, SDTOA and SDTOB pins
Note 50. SYNCB, BICKB, SDTIB, SDTI, LRCK, MCKI, BICK, SCLA, SDAA, SDTIA, BICKA and SYNCA pins.
I/O pins (LRCK, BICK and SDAA pins) are at the time of Input state.
Parameter
High level input voltage
Low level input voltage
High level output voltage Iout=-200μA (Note 51)
Low level output voltage Iout= 200μA (Note 51)
Symbol
VIH
VIL
VOH
VOL
min
70%TVDDE
TVDDE-0.2
-
typ
-
max
30%TVDDE
0.2
Unit
V
V
V
V
VOL
VOL
Iin
-
-
0.4
20%TVDDE
±10
V
V
μA
Low-level Output Voltage
(SDAE pin, TVDDE ≥ 2.0V: Iout=3mA)
(SDAE pin, TVDDE < 2.0V: Iout=3mA)
Input leakage current
Note 51. Except for the SDAE pin.
MS1402-E-06
2013/02
- 22 -
[AK4679]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=PVDD=1.7 ~ 2.0V, VDDE=1.1~1.3V, TVDDA=TVDDE=1.6 ~3 .6V, SVDD=3.0 ∼ 5.5V;
CL=20pF or 400pF (SDAA, SDAE pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
LRCK Output Timing
Frequency
fs
Table 7
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
ns
tBCK−60
1/fs − tBCK
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
1/(32fs)
ns
PLL3-0 bits = “0011”
tBCK
1/(64fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS1402-E-06
2013/02
- 23 -
[AK4679]
Parameter
External Slave Mode
MCKI Input Timing
Frequency
256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
LRCK Input Timing
Frequency
256fs
512fs
1024fs
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period (Note 52)
Symbol
min
typ
max
Unit
fCLK
fCLK
fCLK
tCLKL
tCLKH
2.048
4.096
8.192
0.4/fCLK
0.4/fCLK
-
12.288
12.288
12.288
-
MHz
MHz
MHz
ns
ns
fs
fs
fs
tLRCKH
Duty
8
8
8
tBCK−60
45
-
48
24
12
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
-
-
-
-
ns
s
ns
ns
-
12.288
12.288
12.288
-
MHz
MHz
MHz
ns
ns
tBCK
50
48
-
kHz
ns
%
1/(32fs)
1/(64fs)
50
-
ns
ns
%
tBCK
312.5 or
1/(126fs)
130
130
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
2.048
512fs
fCLK
4.096
1024fs
fCLK
8.192
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Output Timing
Frequency
fs
8
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
Note 52. The minimum value is longer time between 312.5ns and 1/(126fs)s.
MS1402-E-06
2013/02
- 24 -
[AK4679]
Parameter
Symbol
min
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
0.5 x tBCK − 40
LRCK “↑” to BICK “↑” (Note 53)
tDBF
0.5 x tBCK − 40
LRCK “↑” to BICK “↓” (Note 54)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
−70
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
−70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Slave Mode
tLRB
0.4 x tBCK
LRCK “↑” to BICK “↑” (Note 53)
tLRB
0.4 x tBCK
LRCK “↑” to BICK “↓” (Note 54)
tBLR
0.4 x tBCK
BICK “↑” to LRCK “↑” (Note 53)
tBLR
0.4 x tBCK
BICK “↓” to LRCK “↑” (Note 54)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
−40
BICK “↓” to LRCK Edge (Note 55)
tLRD
LRCK Edge to SDTO (MSB)
−70
(Except I2S mode)
tBSD
BICK “↓” to SDTO
−70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Slave Mode
tLRB
50
LRCK Edge to BICK “↑” (Note 55)
tBLR
50
BICK “↑” to LRCK Edge (Note 55)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Note 53. MSBS, BCKP bits = “00” or “11”.
Note 54. MSBS, BCKP bits = “01” or “10”.
Note 55. BICK rising edge must not occur at the same time as LRCK edge.
MS1402-E-06
typ
max
Unit
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
-
40
70
ns
ns
-
70
-
ns
ns
ns
-
80
ns
ns
ns
-
80
-
ns
ns
ns
2013/02
- 25 -
[AK4679]
Parameter
Symbol
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins):
SYNCA Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKA Frequency
fBCK2
BICKA Period
tBCK2
BICKA Pulse Width Low
tBCKL2
Pulse Width High
tBCKH2
tSYB2
SYNCA Edge to BICKA “↓” (Note 56)
tSYB2
SYNCA Edge to BICKA “↑” (Note 57)
tBSY2
BICKA “↓” to SYNCA Edge (Note 56)
tBSY2
BICKA “↑” to SYNCA Edge (Note 57)
SYNCA to SDTOA (MSB) (Except Short Frame)
tSYD2
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
SDTIA Hold Time
tSDH2
SDTIA Setup Time
tSDS2
SYNCA Pulse Width Low
tSYL2
Pulse Width High
tSYH2
Serial Interface Timing at MSB justified and I2S
BICKA Frequency
fBCK2
BICKA Period
tBCK2
BICKA Pulse Width Low
tBCKL2
Pulse Width High
tBCKH2
tSYB2
SYNCA Edge to BICKA “↑”
tBSY2
BICKA “↑” to SYNCA Edge
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
tBSD2
BICKA “↓” to SDTOA
SDTIA Hold Time
tSDH2
SDTIA Setup Time
tSDS2
SYNCA Duty Cycle
dSYC2
Note 56. MSBSA, BCKPA bits = “00” or “11”.
Note 57. MSBSA, BCKPA bits = “01” or “10”.
MS1402-E-06
min
typ
max
Unit
8
-
16
kHz
128
244
100
100
40
40
40
40
25
25
0.8 x tBCK2
0.8 x tBCK2
-
4096
60
60
60
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
256
312.5
130
130
50
50
50
50
45
50
3072
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
2013/02
- 26 -
[AK4679]
Parameter
Symbol
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins):
SYNCB Timing
Frequency
fs3
Serial Interface Timing at Short/long Frame Sync
BICKB Frequency
fBCK3
BICKB Period
tBCK3
BICKB Pulse Width Low
tBCKL3
Pulse Width High
tBCKH3
tSYB3
SYNCB Edge to BICKB “↓” (Note 58)
tSYB3
SYNCB Edge to BICKB “↑” (Note 59)
tBSY3
BICKB “↓” to SYNCB Edge (Note 58)
tBSY3
BICKB “↑” to SYNCB Edge (Note 59)
SYNCB to SDTOB (MSB) (Except Short Frame)
tSYD3
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
SDTIB Hold Time
tSDH3
SDTIB Setup Time
tSDS3
SYNCB Pulse Width Low
tSYL3
Pulse Width High
tSYH3
Serial Interface Timing at MSB justified and I2S
BICKB Frequency
fBCK3
BICKB Period
tBCK3
BICKB Pulse Width Low
tBCKL3
Pulse Width High
tBCKH3
tSYB3
SYNCB Edge to BICKB “↑”
tBSY3
BICKB “↑” to SYNCB Edge
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
tBSD3
BICKB “↓” to SDTOB
SDTIB Hold Time
tSDH3
SDTIB Setup Time
tSDS3
SYNCB Duty Cycle
dSYC3
Note 58. MSBSB, BCKPB bits = “00” or “11”.
Note 59. MSBSB, BCKPB bits = “01” or “10”.
MS1402-E-06
min
typ
max
Unit
8
-
48
kHz
128
244
100
100
40
40
40
40
25
25
0.8 x tBCK3
0.8 x tBCK3
-
4096
60
60
60
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
256
312.5
130
130
50
50
50
50
45
50
3072
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
2013/02
- 27 -
[AK4679]
Parameter
Symbol
SYNC1/3, BCLK1/BCLK3 Input Timing
SYNC1/3 Input Timing
SYNC1/3 frequency
fs
min
max
Unit
8
48
kHz
3072
kHz
BCLK1 Input Timing (Note 60, Note 61)
fBCLK
64
Pulse width Low
Pulse width High
tBCKL1
tBCKH1
0.4 x tBCLK
typ
ns
ns
0.4x tBCLK
Note 60. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be
stable
Note 61. fBCLK ≥ 4 x N x fs (N=1, 2, 3….)
Parameter
Symbol
SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4
tBSYD
Delay Time from BICLK1 “↑” to SYNC1 “↑”
(Note 62)
Delay Time from SYNC1 “↓” to BICK1 “↑”
(Note 62)
tSYBD
Serial Data Input Latch Setup Time
tB1IDS
Serial Data Input Latch Hold Time
tB1IDH
Delay Time from SYNC1 to Serial Data Output
tSY1OD
Delay Time from BICK1 “↓” to Serial Data Output (Note 63)
tB1OD
SDIN2, SDOUT2
SYNC2 Duty cycle
Serial Data Input Latch Setup Time
tB2IDS
Serial Data Input Latch Hold Time
tB2IDH
Delay Time from SYNC2 to Serial Data Outputs
tSY2OD
tB2OD
Delay Time from BCLK2 “↓”to Serial Data Output (Note 64)
SDINn → SDOUTn (n=1, 2, 3, 4)
Delay time from SDINn to SDOUTn Output
tIOD
Note 62. BICK1 edge must not occur at the same time as SYNC1 edge.
Note 63. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”.
Note 64. When the polarity of BICK2 is inverted, delay time is from BICK2 “↑”
MS1402-E-06
min
typ
max
Unit
40
40
ns
ns
ns
ns
ns
ns
40
40
%
ns
ns
ns
ns
60
ns
20
100
40
40
50
40
40
2013/02
- 28 -
[AK4679]
Parameter
Symbol
min
typ
max
Unit
2
Control Interface Timing (I C Bus mode): (Note 65, Note 66)
SCL Clock Frequency
fSCL
30
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
μs
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling (Note 67)
tHD:DAT
0
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Capacitive Load on Bus
Cb
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
50
ns
Digital Audio Interface Timing: CL=100pF
DMCLK Output Timing
Period
tSCK
1/(64fs)
ns
Rising Time
tSRise
10
ns
Falling Time
tSFall
10
ns
Duty Cycle
dSCK
45
50
55
%
Audio Interface Timing
DMDAT Setup Time
tDMS
50
ns
DMDAT Hold Time
tDMH
0
ns
Power-down & Reset Timing
tAPDA
1.5
μs
PDNA Accept Pulse Width (Note 68)
tAPDE
0.6
PDNE Accept Pulse Width (Note 68)
μs
PDN Reject Pulse Width (Note 68)
tRPD
50
ns
PMADL or PMADR “↑” to SDTO valid (Note 69)
tPDV
1059
1/fs
ADRST bit = “0”
tPDV
267
1/fs
ADRST bit = “1”
PMDML or PMDMR “↑” to SDTO valid (Note 70)
tPDV
1059
1/fs
ADRST bit = “0”
tPDV
267
1/fs
ADRST bit = “1”
tPDV2
164
1/fs2
PMSRAO “↑” to SDTOA valid (Note 71)
tPDV3
164
1/fs3
PMSRBO “↑” to SDTOB valid (Note 72)
Note 65. SDA means both SDAA and SDAE pins. SCL means both SCLA and SCLE pins.
Note 66. I2C-bus is a registered trademark of NXP B.V.
Note 67. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 68. The audio block of AK4679 can be reset by bringing PDNA pin = “L” to “H” only upon power up. The PDNA
pin must held “L” for more than 1.5μs for a certain reset. The DSP block can be reset by bringing PDNE pin =
“L” to “H” only upon power up. The PDNE pin must held “L” for more than 0.6μs for a certain reset. The
AK4679 is not reset by the “L” pulse less than 50ns.
Note 69. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
Note 70. This is the count of LRCK “↑” from the PMDML or PMDMR bit = “1”.
Note 71. This is the count of SYNCA “↑” from the PMSRAO bit = “1”.
Note 72. This is the count of SYNCB “↑” from the PMSRBO bit = “1”.
MS1402-E-06
2013/02
- 29 -
[AK4679]
Parameter
Symbol
Control Interface Timing (SPI mode)
SCLK Fall Time
tSF
SCLK Rise Time
tSR
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
SCLK High Level Width
tSCLKH
CSN High Level Width
tWRQH
From CSN “↑” to PDN “↑”
tRST1
From PDN “↑” to CSN “↓”
tIRRQ
From SCLK “↑” to CSN “↑”
tWSC
From SCLK “↑” to CSN “↑”
tSCW
tSIS
SI Latch Setup Time
SI Latch Hold Time
tSIH
Delay Time from SCLK “↓”to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 73)
tSOH
Note 73. Except when input the eighth bit of the command code.
MS1402-E-06
min
typ
max
Unit
30
30
4.0
ns
ns
MHz
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
120
120
500
600
100
500
800
100
100
100
100
2013/02
- 30 -
[AK4679]
■ Timing Diagram
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
50%TVDDA
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%TVDDA
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
Figure 5. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%TVDDA
tDBF
BICK
(BCKP = "0")
50%TVDDA
BICK
(BCKP = "1")
50%TVDDA
tBSD
SDTO
MSB
tSDS
50%TVDDA
tSDH
VIH1
SDTI
VIL1
Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “0”)
MS1402-E-06
2013/02
- 31 -
[AK4679]
tLRCKH
LRCK
50%TVDDA
tDBF
BICK
(BCKP = "1")
50%TVDDA
BICK
(BCKP = "0")
50%TVDDA
tBSD
SDTO
50%TVDDA
MSB
tSDS
tSDH
VIH1
SDTI
VIL1
Figure 7. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “1”)
50%TVDDA
LRCK
tMBLR
BICK
50%TVDDA
tLRD
tBSD
SDTO
50%TVDDA
tSDS
tSDH
VIH1
SDTI
VIL1
Figure 8. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
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[AK4679]
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "0")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "1")
VIL1
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = BICK pin, DSP mode, MSBS bit= “0”)
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "1")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "0")
VIL1
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = BICK pin, DSP mode, MSBS bit= “1”)
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[AK4679]
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
VIH1
BICK
VIL1
tBCKH
tBCKL
Figure 11. Clock Timing (PLL Slave mode; Except DSP mode)
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "0")
VIH1
BICK
(BCKP = "1")
VIL1
tBSD
SDTO
MSB
tSDS
SDTI
50%TVDD
tSDH
MSB
VIH1
VIL1
Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS bit= “0”)
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[AK4679]
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "1")
VIH1
BICK
(BCKP = "0")
VIL1
tBSD
SDTO
50%TVDD
MSB
tSDS
SDTI
tSDH
VIH1
MSB
VIL1
Figure 13. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS bit= “1”)
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH1
BICK
VIL1
tBCKH
tBCKL
Figure 14. Clock Timing (EXT Slave mode)
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[AK4679]
VIH1
LRCK
VIL1
tLRB
tBLR
VIH1
BICK
VIL1
tBSD
tLRD
SDTO
MSB
50%TVDD
tSDH
tSDS
VIH1
SDTI
VIL1
Figure 15. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
1/fs2
VIH1
SYNCA
VIL1
tSY H2
tSYL2
dSYC2 = tSYH 2 x fs2 x 100
tS YL2 x fs 2 x 100
tB CK2 = 1/fBCK 2
VIH1
VIL1
B ICKA
tBC KH2
tB CKL2
Figure 16. Clock Timing of PCM I/F A
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[AK4679]
VIH1
SYNCA
VIL1
tBSY2
tSYB2
VIH1
BICKA
VIL1
(BCKPA = “0”)
VIH1
BICKA
VIL1
(BCKPA = “1”)
tSYD2
tBSD2
SDTOA
50%TVDDA
tSDS2
tSDH2
VIH1
SDTIA
VIL1
Figure 17. PCM I/F A Timing at short and long frame sync (MSBSA bit= “0”)
VIH1
SYNCA
VIL1
tBSY2
tSYB2
VIH1
BICKA
VIL1
(BCKPA = “1”)
VIH1
BICKA
(BCKPA = “0”)
VIL1
tBSD2
SDTOA
50%TVDDA
tSDS2
tSDH2
VIH1
SDTIA
VIL1
Figure 18. PCM I/F A Timing at short and long frame sync (MSBSA bit= “1”)
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[AK4679]
VIH1
SYNCA
VIL1
tBSY2
tSYB2
VIH1
BICKA
VIL1
tSYD2
tBSD2
SDTOA
50%TVDDA
tSDS2
tSDH2
VIH1
SDTIA
VIL1
Figure 19. PCM I/F A Timing at MSB justified and I2S
1/fs3
VIH1
SYNCB
VIL1
tSY H3
tSYL3
dSYC3 = tSYH 3 x fs3 x 100
tS YL3 x fs 3 x 100
tB CK3 = 1/fBCK 3
VIH1
VIL1
B ICKB
tBC KH3
tB CKL3
Figure 20. Clock Timing of PCM I/F B
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[AK4679]
VIH1
SYNCB
VIL1
tBSY3
tSYB3
VIH1
BICKB
VIL1
(BCKPB = “0”)
VIH1
BICKB
VIL1
(BCKPB = “1”)
tSYD3
tBSD3
SDTOB
50%TVDDA
tSDS3
tSDH3
VIH1
SDTIB
VIL1
Figure 21. PCM I/F B Timing at short and long frame sync (MSBSB bit= “0”)
VIH1
SYNCB
VIL1
tBSY3
tSYB3
VIH1
BICKB
VIL1
(BCKPB = “1”)
VIH1
BICKB
(BCKPB = “0”)
VIL1
tBSD3
SDTOB
50%TVDDA
tSDS3
tSDH3
VIH1
SDTIB
VIL1
Figure 22. PCM I/F B Timing at short and long frame sync (MSBSB bit= “1”)
MS1402-E-06
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[AK4679]
VIH1
SYNCB
VIL1
tBSY3
tSYB3
VIH1
BICKB
VIL1
tSYD3
tBSD3
SDTOB
50%TVDDA
tSDS3
tSDH3
VIH1
SDTIB
VIL1
Figure 23. PCM I/F B Timing at MSB justified and I2S
tSCK
65%AVDD
DMCLK
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 24. DMCLK Clock Timing
65%AVDD
DMCLK
35%AVDD
tDMS
tDMH
VIH3
DMDAT
VIL3
Figure 25. Audio Interface Timing (DCLKP bit = “1”)
65%AVDD
DMCLK
35%AVDD
tDMS
tDMH
VIH3
DMDAT
VIL3
Figure 26. Audio Interface Timing (DCLKP bit = “0”)
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[AK4679]
1/fs
ts=1/fs
1/fs
SYNC1/3
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BCLK1/3
VIL
Figure 27. System Clock
VIH
VIL
SYNC1/3
tBSYD
tSYBD
VIH
VIL
BCLK1/3
tB1IDS
tB1IDH
VIH
VIL
SDIN1/3/4
tSY1OD
tB1OD
SDOUT1/3/4
50%TVDD
tIOD
VIH
VIL
SDIN2/4/3
Figure 28. Serial Data Interface (Port#1, 3, 4)
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[AK4679]
SYNC2
50%TVDD
BCLK2
50%TVDD
tB2IDS
tB2IDH
VIH
VIL
SDIN2
tB2OD
tSY2OD
SDOUT2
50%TVDD
tIOD
VIH
VIL
SDIN1
Figure 29. Serial Data Interface (Port#2)
VIH1 (VIH)
SDAA
(SDAE)
VIL1 (VIL)
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH1 (VIH)
SCLA
(SCLE)
VIL1 (VIL)
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
Start
tSU:STO
Stop
Figure 30. I2C Bus Mode Timing
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[AK4679]
tSR
tSF
VIH
SCLK
VIL
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH
PDNE
VIL
VIH
CSN
VIL
tRST1
tIRRQ
Figure 31. μP Interface 1 (SPI)
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[AK4679]
VIH
CSN
tWRQH
VIL
VIH
SI
VIL
tSIH
tSIS
VIH
SCLK
VIL
tWSC
tSCW
tWSC
tSCW
Figure 32. μP Interface 2 (SPI)
VIH
SCLK
VIL
VIH
SO
VIL
tSOH
tSOS
Figure 33. μP Interface 3 (SPI)
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[AK4679]
PMADL bit, PMADR bit,
PMDML or PMDMR bit
tPDV
SDTO
50%TVDDA
Figure 34. Power Down & Reset Timing 1
tAPDA
tAPDE
tRPD
PDN
VIL1
Figure 35. Power Down & Reset Timing 2
PMSRAO bit
tPDV2
SDTOA
50%TVDDA
Figure 36. Power Down & Reset Timing 3
PMSRBO bit
tPDV3
SDTOB
50%TVDDA
Figure 37. Power Down & Reset Timing 4
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[AK4679]
OPERATION OVERVIEW
The figure shown below is one the connection example with aAudio Processor, Base-band processor, BT module and
AK4679. Since the clock control block (CGU) provides DSP master clock, stable clock from Audio Processor or
Base-band must be supplied to the AK4679 during an operation.
Audio Processor
AK4679
Audio I/F I2S
BICK
SCLK
LRCK
LRCK
SDTI
SDO
SDTO
SDI
BCLK3
SYNC3
SDTI3
SDT03
DSP
BCLK1
Base Band
PCM I/F I2S
BICK
SYNC1
SYNC
SDTI1
SDOUT
SDTO1
SDIN
BICKA
SYNCA
SDTIA
SDTOA
SDTI4
Bluetooth
SDTO4
BCLK2
PCM I/F I2S
SYNC2
SDOUT
BICK
SYNC
SDTO2
SDIN
SDTI2
BICKB
SYNCB
SDTIB
SDTOB
Figure 38. Connection Diagram Example
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[AK4679]
■ CODEC System Clock (Audio I/F)
There are the following four clock modes to interface with external devices. (Table 2 and Table 3)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
Table 5
Figure
Figure 39
1
0
Table 5
Figure 40
x
x
Figure 41
Figure 42
0
0
0
1
Table 2. Clock Mode Setting (x: Don’t care)
MCKI pin
Selected by PLL3-0
bits
BICK pin
Output
(Selected by BCKO bit)
Input
GND
(Selected by PLL3-0 bits)
Input
Selected by FS1-0 bits
(≥ 32fs)
Output
Selected by FS1-0 bits
(Selected by BCKO bit)
Table 3. Clock pins state in Clock Mode
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode (Audio I/F)
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. The audio
I/F is in slave mode until the M/S bit is changed to “1” after the PDNA pin changes from “L” to “H”. The AK4679 goes
to master mode by changing M/S bit = “1”.
When the audio I/F is used in master mode, LRCK and BICK pins are Hi-Z state until M/S bit becomes “1”. LRCK and
BICK pins of the audio I/F should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid floating
state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 4. Select Master/Slave Mode
MS1402-E-06
(default)
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[AK4679]
■ PLL Mode (PMPLL bit = “1”) (Audio I/F)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates clock that is selected by the PLL3-0
and FS3-0 bits. The PLL lock time is shown in Table 5. This lock time is when the audio I/F is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
2
3
4
5
6
7
8
10
11
12
13
14
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
Others
Input
Frequency
PLL Lock
Time
(max)
2ms
2ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
10ms
32fs
64fs
11.2896MHz
12.288MHz
12MHz
24MHz
19.2MHz
13MHz
26MHz
13.5MHz
27MHz
25MHz
Others
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI and BICK pins, the sampling frequency is selected by FS3-0 bits as defined in
Table 6.
Sampling Frequency (Note
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
74)
0
0
0
0
0
8kHz mode
1
0
0
0
1
12kHz mode
2
0
0
1
0
16kHz mode
3
0
0
1
1
24kHz mode
5
0
1
0
1
11.025kHz mode
7
0
1
1
1
22.05kHz mode
10
1
0
1
0
32kHz mode
11
1
0
1
1
48kHz mode
15
1
1
1
1
44.1kHz mode
(default)
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (N/A: Not available)
Note 74. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL differs from the
sampling frequency of mode name in some combinations of MCKI frequency(PLL3-0 bits) and sampling
frequency (FS3-0 bits). Refer to Table 7 for the details of sampling frequency. In master mode, LRCK and BICK
output frequency correspond to sampling frequencies shown in Table 7. When the BICK pin is the PLL reference
clock input, the sampling frequency generated by PLL is the same sampling frequency of mode name.
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[AK4679]
Input Frequency
MCKI[MHz]
11.2896
Sampling Frequency
Sampling Frequency
Mode
generated by PLL [kHz](Note 75)
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
11.025kHz mode
11.025000
22.05kHz mode
22.050000
44.1kHz mode
44.100000
12
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
24
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
13.5
8kHz mode
8.000300
12kHz mode
12.000451
16kHz mode
16.000601
24kHz mode
24.000901
32kHz mode
32.001202
48kHz mode
48.001803
11.025kHz mode
11.025218
22.05kHz mode
22.050436
44.1kHz mode
44.100871
27
8kHz mode
8.000300
12kHz mode
12.000451
16kHz mode
16.000601
24kHz mode
24.000901
32kHz mode
32.001202
48kHz mode
48.001803
11.025kHz mode
11.025218
22.05kHz mode
22.050436
44.1kHz mode
44.100871
Sampling frequency that differs from sampling frequency of mode name
Note 75. These are rounded off to six decimal places.
Table 7. Sampling Frequency at PLL mode (Reference clock is MCKI)
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[AK4679]
Input Frequency
MCKI[MHz]
12.288
Sampling Frequency
Sampling Frequency
Mode
generated by PLL [kHz] (Note 75)
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
11.025kHz mode
11.025000
22.05kHz mode
22.050000
44.1kHz mode
44.100000
19.2
8kHz mode
8.000000
12kHz mode
12.000000
16kHz mode
16.000000
24kHz mode
24.000000
32kHz mode
32.000000
48kHz mode
48.000000
11.025kHz mode
11.025000
22.05kHz mode
22.050000
44.1kHz mode
44.100000
13
8kHz mode
7.999786
12kHz mode
11.999679
16kHz mode
15.999572
24kHz mode
23.999358
32kHz mode
31.999144
48kHz mode
47.998716
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
26
8kHz mode
7.999786
12kHz mode
11.999679
16kHz mode
15.999572
24kHz mode
23.999358
32kHz mode
31.999144
48kHz mode
47.998716
11.025kHz mode
11.024877
22.05kHz mode
22.049753
44.1kHz mode
44.099507
25
8kHz mode
8.000088
12kHz mode
12.000132
16kHz mode
16.000177
24kHz mode
24.000265
32kHz mode
32.000353
48kHz mode
48.000530
11.025kHz mode
11.025706
22.05kHz mode
22.051411
44.1kHz mode
44.102823
Sampling frequency that differs from sampling frequency of mode name
Note 75. These are rounded off to six decimal places.
Table 7. Sampling Frequency at PLL mode (Reference clock is MCKI) (2)
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[AK4679]
■ PLL Unlock State (Audio I/F)
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins output “L” before the PLL goes to lock state after PMPLL bit = “0” Æ “1” (Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit “0”.
PLL State
BICK pin
LRCK pin
After that PMPLL bit “0” Æ “1”
“L” Output
“L” Output
PLL Unlock (except above case)
Invalid
Invalid
PLL Lock
Table 9
1fs Output
Table 8. Clock Operation in PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) (Audio I/F)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 25MHz, 26MHz or
27MHz) is input to the MCKI pin, the BICK and LRCK clocks are generated by an internal PLL circuit. MCKI input
frequency is selected by PLL3-0 bits (Table 5). The BICK output frequency is selected between 32fs or 64fs, by BCKO
bit (Table 9). Sampling frequency mode is selected by FS3-0 bits (Table 6, Table 7).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 25MHz,
26MHz, 27MHz
CODEC
DSP
MCKI
BICK
LRCK
32fs, 64fs
1fs
BCLKx
SYNCx
SDTO
SDINx
SDTI
SDOUTx
Figure 39. PLL Master Mode (x=1 to 4)
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 9. BICK Output Frequency in Master Mode
BCKO bit
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[AK4679]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) (Audio I/F)
A reference clock of PLL is selected among the input clocks to BICK pin. The required clock to the CODEC is generated
by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
BICK input should be synchronized to LRCK input. Sampling frequency can be selected by FS3-0 bits (Table 6).
CODEC
DSP
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLKx
SYNCx
SDTO
SDINx
SDTI
SDOUTx
Figure 40. PLL Slave Mode (PLL Reference Clock: BICK pin) (x=1 to 4)
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[AK4679]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (Audio I/F)
When PMPLL bit is “0”, the audio I/F becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate the
CODEC are MCKI (256fs, 512fs, or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be
synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by
CM1-0 bits (Table 10) and sampling frequency is selected by FS3-0 bits (Table 11).
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this
case, BICK and LRCK can be stopped.
Mode
0
1
2
3
Mode
0
1
2
3
5
7
10
11
15
Others
CM1 bit
CM0 bit
MCKI Input Frequency
Sampling Frequency Range
0
0
256fs
(default)
24kHz ∼ 48kHz
0
1
512fs
8kHz ∼ 24kHz
1
0
1024fs
8kHz ∼ 12kHz
1
1
256fs
8kHz ∼ 24kHz
Table 10. MCKI Frequency in EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
FS3 bit
0
0
0
0
0
0
1
1
1
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
8kHz
0
0
1
12kHz
0
1
0
16kHz
0
1
1
24kHz
1
0
1
11.025kHz
1
1
1
22.05kHz
0
1
0
32kHz
0
1
1
48kHz
1
1
1
44.1kHz
Others
N/A
Table 11. Setting of Sampling Frequency (N/A: Not available)
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 12.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
82dB
512fs
82dB
1024fs
92dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
CODEC
MCKI
BICK
LRCK
256fs, 512fs, or
1024fs
≥ 32fs
1fs
DSP
BCLKx
SYNCx
SDTO
SDINx
SDTI
SDOUTx
Figure 41. EXT Slave Mode (x=1 to 4)
MS1402-E-06
2013/02
- 53 -
[AK4679]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (Audio I/F)
The audio I/F becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs, or 1024fs). The
input frequency of MCKI is selected by CM1-0 bits (Table 13) and sampling frequency is selected by FS3-0 bits (Table
14).
Mode
0
1
2
3
Mode
0
1
2
3
5
7
10
11
15
Others
CM1 bit
CM0 bit
MCKI Input Frequency
Sampling Frequency Range
0
0
256fs
(default)
24kHz ∼ 48kHz
0
1
512fs
8kHz ∼ 24kHz
1
0
1024fs
8kHz ∼ 12kHz
1
1
256fs
8kHz ∼ 24kHz
Table 13. MCKI Frequency in EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
FS3 bit
0
0
0
0
0
0
1
1
1
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
8kHz
0
0
1
12kHz
0
1
0
16kHz
0
1
1
24kHz
1
0
1
11.025kHz
1
1
1
22.05kHz
0
1
0
32kHz
0
1
1
48kHz
1
1
1
44.1kHz
Others
N/A
Table 14. Setting of Sampling Frequency (N/A: Not available)
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 15.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
82dB
512fs
82dB
1024fs
92dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
CODEC
MCKI
BICK
LRCK
256fs, 512fs, or
1024fs
32fs or 64fs
1fs
DSP
BCLKx
SYNCx
SDTO
SDINx
SDTI
SDOUTx
Figure 42. EXT Master Mode (x=1 to 4)
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency in Master Mode
MS1402-E-06
2013/02
- 54 -
[AK4679]
■ System Reset
Upon power-up, the PDNA and PDNE pis must be “L” and changed to “H” after all power supplies are supplied. The
period of “L” time more than 1.5μs is needed to reset the whole block of AK4679. All internal registers reset to their
initial values.
The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1”. The initialization
cycle time is set by ADRST bit (Table 17). During the initialization cycle, the ADC digital data outputs of both channels
are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the initialization cycle is
complete. When using a digital microphone, the initialization cycle is the same as ADC’s.
Note 76. The initial data of ADC has offset data that depends on the condition of the microphone and the cut-off
frequency of HPF. If this offset is not small, make initialization cycle longer by setting ADRST bit = “0” or do
not use the initial data of ADC.
ADRST bit
0
1
Digital Initialization Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
267/fs
33.4ms
16.7ms
Table 17. ADC Digital Initialization Cycle
fs = 44.1kHz
24ms
6.1ms
(default)
Audio block’s reset is released when the dummy command (Actually, the rising edge of 16th SCL) is input after
PDNA pins = “H”. Dummy command is executed by writing all “0” to the register address 00H.
S
T
A
R
T
SDAA
S
S
T
O
P
R/W="0"
Slave *
Address
Sub
Address(00H)
Data(00H)
N
A
C
K
N
A
C
K
P
N
A
C
K
(*: Refer to Figure 124)
Figure 43. Dummy Command for Audio Block
The system reset for DSP block are released when both PWSW bit and MRSTN bit are set after PDNE pins = “H”
S
T
A
R
T
SDAE
S
T
O
P
R/W="0"
Slave
S Address1
Command
Code (D0H)
Data(01H)
A
C
K
A
C
K
P
A
C
K
Figure 44. PWSW bit setting for DSP block
S
T
A
R
T
SDAE
S
S
T
O
P
R/W="0"
Slave
Address1
Command *
Code (D1H)
Data(01H)
A
C
K
A
C
K
P
A
C
K
(*: Refer to Figure 125)
Figure 45. MRSTN bit setting for DSP block
MS1402-E-06
2013/02
- 55 -
[AK4679]
■ Audio Interface Format
Four types of data formats are available and can be selected by setting the DIF1-0 bits (Table 18). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the audio I/F in master mode, but must be input to the audio I/F in slave mode.
0
1
DIF1
bit
0
0
DIF0
bit
0
1
2
1
0
3
1
1
Mode
SDTO (ADC)
SDTI (DAC)
16bit DSP Mode
24bit MSB justified
16bit DSP Mode
16bit LSB justified
24bit MSB
24bit MSB justified
justified
2
24/16 bit I S
24/16bit I2S
compatible
compatible
Table 18. Audio Interface Format
BICK
Figure
≥ 32fs
≥ 32fs
Table 19
Figure 50
≥ 48fs
Figure 51
32fs or
≥ 48fs
Figure 52
(default)
If 24-bit(16-bit) data that ADC outputs is converted to 8-bit data by removing LSB 16-bit(8-bit), “−1” at 24bit(16bit) data
is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to
“−65536” at 24-bit (“−256” at 16-bit) data which is a large offset. This offset can be removed by adding the offset of
“32768” at 24-bit (“128” at 16bit) to 24-bit(16-bit) data before converting to 8-bit data.
In Mode 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Mode 0 (16bit DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 19).
DIF1
bit
0
DIF0
bit
MSBS
bit
BCKP
bit
0
0
0
1
1
0
1
1
0
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
Table 19. Audio Interface Format in Mode 0
MS1402-E-06
Figure
Figure 46
(default)
Figure 47
Figure 48
Figure 49
2013/02
- 56 -
[AK4679]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 46. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 47. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “0”)
MS1402-E-06
2013/02
- 57 -
[AK4679]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
48
47
49
50
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 48. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
8
7
46
6
47
5
48
4
49
50
1
62
0
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
Lch
SDTI(i)
15 14
2
1
0
2
1
0
Rch
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 49. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “1”)
MS1402-E-06
2013/02
- 58 -
[AK4679]
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10
9
8
23 22 21
15 14 13 12 11 10
9
8
23
SDTI(i)
15 14 13
7
1
0
15 14 13
7
1
0
15
0
1
2
3
6
15
5
16
17
4
3
18
23
2
24
31
30
0
1
2
3
6
15
5
16
17
4
18
3
23
2
24
25
31
30
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
Don’t Care
8
7
6
5
15
14 13 8
23 22 21
0
2
1
8
Don’t Care
0
7
6
5
15
14 13 8
23
0
2
1
24
25
0
24bit: 23:MSB, 0:LSB
16bit: 15: MSB, 0:LSB
Lch Data
Rch Data
Figure 50. Mode 1 Timing
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 51. Mode 2 Timing
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
SDTI(i)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 52. Mode 3 Timing
MS1402-E-06
2013/02
- 59 -
[AK4679]
■ MIC/LINE Input Selector
The AK4679 has input selector. When MDIF1, MDIF2 and MDIF3 bits are “0”, INL1-0 and INR1-0 bits select
LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1, MDIF2 and MDIF3 bits are “1”,
LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 pins become IN1+/−, IN2−/+ and IN3+/− pins, respectively. In this case,
full-differential input is available (Figure 54). Digital microphone input is selected when DMIC bit = “1”.
MDIF1
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
MDIF2
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
MDIF3
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
INL1
INL0
INR1
INR0
Lch
Rch
bit
bit
bit
bit
0
0
0
0
LIN1
RIN1
0
0
0
1
LIN1
RIN2
0
0
1
0
LIN1
RIN3
0
0
1
1
LIN1
RIN4
0
1
0
0
LIN2
RIN1
0
1
0
1
LIN2
RIN2
0
1
1
0
LIN2
RIN3
0
1
1
1
LIN2
RIN4
1
0
0
0
LIN3
RIN1
1
0
0
1
LIN3
RIN2
1
0
1
0
LIN3
RIN3
1
0
1
1
LIN3
RIN4
1
1
0
0
LIN4
RIN1
1
1
0
1
LIN4
RIN2
1
1
1
0
LIN4
RIN3
1
1
1
1
LIN4
RIN4
1
0
0
0
RIN1
IN3+/−
1
0
0
1
RIN2
IN3+/−
1
0
1
1
RIN4
IN3+/−
0
0
0
1
LIN1
IN2+/−
1
0
0
1
LIN3
IN2+/−
1
1
0
1
LIN4
IN2+/−
1
0
0
1
IN3+/−
IN2+/−
0
0
0
1
RIN2
IN1+/−
0
0
1
0
RIN3
IN1+/−
0
0
1
1
RIN4
IN1+/−
0
0
0
1
IN1+/−
IN2+/−
Others
N/A
Table 20. MIC-Amp Input Signal at DMIC bit = “0” (N/A: Not available)
MS1402-E-06
(default)
2013/02
- 60 -
[AK4679]
AK4679
INL1-0 bits
LIN1/IN1+ pin
RIN1/IN1− pin
ADC Lch
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR1-0 bits
LIN2/IN2− pin
RIN2/IN2+ pin
ADC Rch
MDIF2 bit MIC-Amp Rch
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4 pin
RIN4 pin
Figure 53. Mic/Line Input Selector (DMIC bit = “0”)
AK4679
MPWR pin
1k
MIC-Amp
IN1+ pin
IN1− pin
1k
Figure 54. Connection Example for Full-differential Mic Input (MDIF1/2/3 bits = “1”)
AK4679
MIC-Amp
IN1+ pin
IN1− pin
Figure 55. Connection Example for Full-differential Mic Input (MDIF1/2/3 bits = “1”)
MS1402-E-06
2013/02
- 61 -
[AK4679]
■ MIC Gain Amplifier
The AK4679 has a gain amplifier for microphone input. The gain of MIC-Amp Lch and Rch is independently selected by
the MGNL3-0 and MGNR3-0 bits (Table 21).
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MGNL3
MGNL2
MGNL1
MGNL0
/MGNR3
/MGNR2
/MGNR1
/MGNR0
Input Gain
bits
bits
bits
bits
0
0
0
0
N/A
0
0
0
1
N/A
0
0
1
0
N/A
0
0
1
1
−6dB
0
1
0
0
−3dB
0
1
0
1
0dB
0
1
1
0
+3dB
0
1
1
1
+6dB
1
0
0
0
+9dB
1
0
0
1
+12dB
1
0
1
0
+15dB
1
0
1
1
+18dB
1
1
0
0
+21dB
1
1
0
1
+24dB
1
1
1
0
N/A
1
1
1
1
N/A
Table 21. Mic Input Gain (N/A: Not available)
MS1402-E-06
(default)
2013/02
- 62 -
[AK4679]
■ MIC Power
When PMMP1 bit (PMMP2 bit) = “1”, the MPWR1 pin (MPWR2 pin) supplies power for the microphone. This output
voltage is typically 2.5V @MICL1 bit (MICL2 bit) =“0” (SVDD=3.0 ~ 5.5V), and typically [email protected] bit (MICL2
bit) = “1” (SVDD=3.3 ~ 5.5V) (Table 22). The load resistance is minimum 1kΩ for each MPWR1 pin and MPWR2 pin.
In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel. Any capacitor must not be
connected directly to the MPWR1 pin (MPWR2 pin) (Figure 56).
MICL1 bit
MICL2 bit
0
1
Output Level (typ)
AVDD=1.8V
3.0 ~ 5.5V
1.39 x AVDD
2.5V
3.3 ~ 5.5V
1.56 x AVDD
2.8V
Table 22. MIC Power 1, MC Power 2 Output Level
SVDD Voltage Range
Output Level (typ)
(default)
PMMP1 bit
MPWR1 pin
0
Hi-Z
(default)
1
Output
Table 23. MIC Power 1 Status
PMMP2 bit
MPWR2 pin
0
Hi-Z
(default)
1
Output
Table 24. MIC Power 2 Status
MIC Power 2
MPWR2 pin
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR1 pin
≥ 2kΩ
MIC Power 1
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
AK4679
Microphone
RIN2 pin
Figure 56. MIC Block Circuit
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[AK4679]
■ Digital MIC
1. Connection to Digital MIC
The AK4679 can be connected to digital microphone by setting DMIC bit = “1”. When DMIC bit is set to “1”, the LIN1
and RIN1 pins become DMDAT (digital microphone data input) and DMCLK (digital microphone clock supply) pins
respectively. The same power supply as AVDD must be provided to the digital microphone. The Figure 57 and Figure 58
show mono/stereo connection examples. The DMCLK signal is output from the AK4679, and the digital microphone
outputs 1bit data, which generated by ΔΣModulator, from DMDAT. PMDML/R bits control power up/down of the digital
block (Decimation Filter and HPF1). PMADL/PMADR bits settings do not affect the digital microphone power
management. The DCLKE bit controls ON/OFF of the output clock from the DMCLK pin. When the AK4679 is powered
down (PDNA pin= “L”), the DMCLK and DMDAT pins are pulled-down by internal 2.7kΩ(typ.) resistor. However,
when the AK4679 is powered-up (PDNA pin = “H”), path of the internal pulled-down resistor is OFF. Therefore, external
pull-down resistor(R) should be connected to the DMDAT pin to avoid floating state.
AVDD
AK4679
VDD
DMCLK(64fs)
AMP
MCKI
PLL
ΔΣ
Modulator
Decimation
HPF1
Filter
DMDAT
Lch
Programmable
Filter
SDTO
ALC
R
VDD
AMP
ΔΣ
Modulator
Rch
Figure 57. Connection Example of Stereo Digital MIC
AVDD
AK4679
VDD
DMCLK(64fs)
AMP
PLL
MCKI
ΔΣ
Modulator
DMDAT
Decimation
HPF1
Filter
Programmable
Filter
ALC
SDTO
R
Figure 58. Connection Example of Mono Digital MIC
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[AK4679]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1, Lch data is input to the
Decimation Filter if DMCLK = “H”, Rch data is input if DMCLK = “L”. When DCLKP bit = “0”, Rch data is input to the
Decimation Filter if DMCLK = “H”, Lch data is input if DMCLK = “L”. The DMCLK pin outputs “L” when DCLKE bit
= “0”, and only supports 64fs. In this case, necessary clocks must be supplied to the AK4679 for ADC operation. The
output data through “the Decimation and Digital Filters” is the negative full-scale with 0% 1’s density of 1bit output data
and positive full-scale with the 100% 1’s density of 1bit output data.
DCLKP bit
0
1
DMCLK pin = “H”
DMCLK pin = “L”
Rch
Lch
Lch
Rch
Table 25. Data In/Output Timing with Digital MIC
(default)
DMCLK(64fs)
DMDAT (Lch)
Valid
Data
Valid
Data
Valid
Data
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 59. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 60. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
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[AK4679]
■ Digital Block
Digital block is composed as Figure 61. Each block can be powered-down by power management bits (PMADL,
PMADR, PMDAL, PMDAR, PMPFIL, PMEQ, PMDRC, PMSRAI, PMSRAO, PMSRBI and PMSRBO bits).
PMADL or PMADR
ADC
HPF1
HPFAD
PFSEL
PMPFIL bit
HPF2
HPF
LPF
LPF
FIL3, EQ0,
GN1-0
Stereo
Separation
3-band
Notch
EQ1-3
ALC, IVL/R
ALC
ADM
MIX
PFSDO
SDOD
SDOL/R1-0
SDTO Lch
PMDAL or PMDAR
PMDRC
S
E
L
DAC
SDTO Rch
SVAL/R2-0
DRC
PMEQ
OVL/R,
SMUTE
SVOLA
SDIM1-0
SRMXL/R1-0
5EQ
S
E
L
DATT-A 5-band
SMUTE
EQ
SDTI Lch
SDTI Rch
PFMXL/R1-0
DASEL1-0
PMOSC
PMMIX
MX1L2-0
MIX1L
OSC for SRC
MX1R2-0
MIX1R
PMSRAO
MX2A1-0
MIX2A
MIX2C MX2C1-0
Mono
MX2B1-0
SDOAD
SDTOA
SRCAO
MIX2B
SVOLB SVB2-0
DATT-B
SRCAI
PMSRAI
SDTIA
BVL6-0
SBMX1-0
CVL6-0
DATT-C
PMSRBO
MXSB2-0
MIX3
SRCBO
SDOBD
BIVOL
SDTOB Lch
SDTOB Rch
SDTIB Lch
SDTIB Rch
SRCBI
BIV2-0
PMSRBI
Figure 61. Path Select of Digital Block
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[AK4679]
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
HPF1: Include the Digital Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF2: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter”.)
LPF: Low Pass Filter (See “Digital Programmable Filter”.)
Stereo Separation: Stereo Separation Emphasis Filter & Gain Compensation. (See “Digital Programmable Filter”.)
Gain Compensation is composed with EQ0 and Gain blocks. This block adjusts the frequency response after Stereo
Separation Emphasis.
3-Band Notch: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter”.)
ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”.)
SVOLA: Side Tone Volume at Internal MIC/SPK or External Headset Phone Call. (See “Side Tone Volume”.)
5-Band EQ: Equalizer for playback path. (See “5-band Equalizer”.)
DATT-A: Digital Volume for playback path. (See “Digital Output Volume”.)
SMUTE: Soft mute. (See “Soft Mute”.)
DRC: Dynamic Range Control for playback path. (See “Dynamic Range Control”.)
DATT-B: Digital Volume for Recording of Received Voice. (See “Digital Volume for Recording of Received
Voice”)
DATT-C: Digital Volume of Received Voice. (See “Digital Volume for Received Voice”)
SVOLB: Side Tone Volume at B/T Headset Phone Call. (See “Side Tone Volume for B/T Phone Call”.)
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[AK4679]
Mode
PMADL bit
(PMDML bit)
Recording 1
1
1
0
1
1
0
0
0
Recording 1
& Playback 2
Playback 1
Playback 2
ADC
PMADR bit
(PMDMR bit)
PMPFIL
bit
PFSEL
bit
PFSDO PMDAL/R
bit
bits
PMEQ
bit
PMDRC
bit
DASEL1-0
bits
0
0
0
1
1
1
1
1
x
x
x
01
01
01
01
01
1
1
0
1
00
0
0
1
0
1
00
0
1
1
0
1
00
0
1
1
0
1
11
1
0
1
0
1
11
1
1
1
0
1
11
1
0
1
1
1
11
1
0
0
0
1
11
1
Table 26. Recode/Playback Mode (x: Don’t care)
1st Order
1st Order
1st Order
HPF1
HPF2
LPF
Stereo
Separation
Gain
Compensation
3 Band
Figure
Figure 62
Figure 63
Figure 64
Figure 65
ALC
Notch
(Volume)
Figure 62. Path at Recording Mode 1
ADC
1st Order
1st Order
1st Order
HPF1
HPF2
LPF
DAC
DRC
SMUTE
DATT-A
Stereo
Separation
Gain
Compensation
3 Band
ALC
Notch
(Volume)
5 Band
EQ
Figure 63. Path at Recording Mode 1 & Playback Mode 2
DAC
DRC
SMUTE
DATT-A
5 Band
EQ
ALC
(Volume)
3 Band
Notch
Gain
Compensation
1st Order
1st Order
LPF
HPF2
Stereo
Separation
Figure 64. Path at Playback Mode 1
DAC
DRC
SMUTE
DATT-A
5 Band
EQ
Figure 65. Path at Playback Mode 2
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[AK4679]
■ Digital Programmable Filter
(1) High Pass Filter (HPF2)
Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by
F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes
this block by 0dB gain. The coefficient must be set when HPF bit = “0” or PMPFIL bit = “0”. The HPF2 starts operation
4/fs(max) after when HPF bit = “1” and PMPFIL bit = “1” are set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 77)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when LPF bit
= “0” or PMPFIL bit = “0”. The LPF starts operation 4/fs(max) after when LPF bit = “1” and PMPFIL bit = “1” are set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 77)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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[AK4679]
(3) Stereo Separation Emphasis Filter (FIL3)
FIL3 is used to emphasize the stereo separation of stereo mic recording data or playback data. F3A13-0 and F3B13-0 bits
set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at
F3AS bit = “1”. FIL3 bit controls ON/OFF of FIL3. When Stereo Separation Emphasis Filter is OFF, the audio data
passes this block by 0dB gain. The coefficient should be set when FIL3 bit = “0” or PMPFIL bit = “0”. The FIL3 starts
operation 4/fs(max) after when FIL3 bit = “1” and PMPFIL bit = “1” are set.
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 77)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
A = 10K/20 x
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 77)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
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[AK4679]
(4) Gain Compensation (EQ0)
Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation
Emphasis Filter. Gain Compensation is composed with Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A15-0,
E0B13-0 and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits set the gain (Table 27). EQ0 bit controls ON/OFF of
EQ0. When EQ is OFF and the gain is 0dB, the audio data passes this block by 0dB gain. The coefficient should be set
when EQ0 bit = “0” or PMPFIL bit = “0”. EQ0 starts operation 4/fs(max) after when EQ0 bit = “1” and PMPFIL bit = “1”
are set.
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Note 77)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
,
B=
1 − 1 / tan (πfc1/fs)
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Transfer function
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 66. EQ0 Frequency Response
GN1 bit
GN0 bit
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 27. Gain select of gain block (x: Don’t care)
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[AK4679]
(5) 3-band Equalizer
This block can be used as Equalizer or Notch Filter. 3-band Equalizer (EQ1, EQ2 and EQ3) is selected ON/OFF
independently by EQ1, EQ2 and EQ3 bits. When Equalizer is OFF, the audio data passes this block by 0dB gain.
E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient
of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. The EQx (x=1∼3) coefficient must be set when
EQx bit = “0” or PMPFIL bit = “0”. EQ1-3 start operation 4/fs(max) after when (EQx (x=1~3) = “1”) and PMPFIL bit =
“1” is set
fs: Sampling frequency
fo1 ~ fo3: Center frequency
fb1 ~ fb3: Band width where the gain is 3dB different from center frequency
K1 ~ K3 : Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 77)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15; LSB= E1A0, E1B0, E1C0,
E2A0, E2B0, E2C0, E3A0, E3B0, E3C0)
tan (πfbn/fs)
An = Kn x
2
, Bn = cos(2π fon /fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn /fs)
,
Cn =
1 − tan (πfbn /fs)
1 + tan (πfb n/fs)
(n = 1, 2, 3)
Transfer function
H(z) = 1 + h1 (z) + h2(z) + h3(z)
1−z
hn (z) = An
−1
−2
1− B nz − Cn z
−2
(n = 1, 2, 3)
The center frequency should be set as below.
0.003 < fon / fs < 0.497
Note 77. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
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[AK4679]
■ ALC Operation
The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. ALC circuit operates at playback
path for Playback mode (Figure 64 and Figure 65) and operates at recording path for Recording mode (Figure 62 and
Figure 63).
1.
ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 28), the IVL
and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 29).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 30). When ALC output level exceeds full-scale at
LFST bit = “1”, IVL and IVR values are immediately (period: 1/fs) changed in 1 step(L/R common). When ALC output
level is less than full-scale, the IVL and IVR values are changed at the individual zero crossing point of each channels or
at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled.), IVL and IVR values are immediately (period: 1/fs) changed
by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting LMAT1-0 bits.
The attenuation operation is exceeded continuously until the input signal level becomes ALC limiter detection level
(Table 28) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when
the input signal level exceeds LMTH1-0 bits.
LMTH1
bit
0
0
1
1
LMTH0
bit
0
1
0
1
ALC Limier Detection Level
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level
LMAT1
bit
LMAT0
bit
0
0
1
1
0
1
0
1
ZTM1
bit
0
0
1
1
ALC Recovery Waiting Counter Reset Level
ZTM0
bit
0
1
0
1
ALC Limiter ATT Step
ALC Output
ALC Output
ALC Output
≥ LMTH
≥ FS
≥ FS + 6dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 29. ALC Limiter ATT Step
ALC Output
≥ FS + 12dB
1
2
8
8
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 30. ALC Zero Crossing Timeout Period
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[AK4679]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 31) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 28) during the wait time, the ALC
recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 32) up
to the set reference level (Table 33) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 30).
Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed in a period set
by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC
recovery operation waits until WTM2-0 period and the next recovery operation is executed. If ZTM1-0 bits is longer than
WTM2-0 bits and no zero crossing occurs, the ALC recovery operation is executed in a period set by ZTM1-0 bits.
For example, when the current IVL and IVR values are 30H and RGAIN1-0 bits are set to “01”, IVL and IVR values are
changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When
the IVL and IVR values exceed the reference level (REF7-0 bits), the IVL and IVR values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone
instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. The
speed of fast recovery operation is set by RFST1-0 bits (Table 34).
WTM2
bit
0
0
0
0
1
1
1
1
WTM1
bit
0
0
1
1
0
0
1
1
WTM0
ALC Recovery Operation Waiting Period
bit
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 31. ALC Recovery Operation Waiting Period
RGAIN1
bit
0
0
1
1
RGAIN0
GAIN STEP
bit
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 32. ALC Recovery GAIN Step
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[AK4679]
REF7-0 bits
GAIN (dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
(default)
:
:
0.375dB
92H
+0.375
91H
0.0
90H
−0.375
:
:
02H
−53.625
01H
−54.0
00H
MUTE
Table 33. Reference Level at ALC Recovery Operation
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 34. Fast Recovery Speed Setting (N/A: Not available)
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[AK4679]
3.
Example of ALC Operation
Table 35 and Table 36 show the examples of the ALC setting for mic recording and playback, respectively.
Register Name
Comment
LMTH1-0
ZELMN
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
* ZTM1-0 bits should be equal to or
shorter than WTM2-0 bits.
Recovery waiting period
Maximum gain at recovery operation
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Data
01
0
Gain of IVOL
fs=8kHz
Operation
−4.1dBFS
Enable
Data
01
0
fs=44.1kHz
Operation
−4.1dBFS
Enable
01
32ms
11
23.2ms
001
E1H
32ms
+30dB
100
E1H
46.4ms
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
1 step
1 step
4 times
Enable
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 35. Example of the ALC setting (Recording Path)
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits
Maximum gain at recovery operation
001
32ms
100
46.4ms
A1H
+6dB
A1H
+6dB
Gain of IVOL
91H
0dB
91H
0dB
00
00
00
1
1 step
1 step
4 times
Enable
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Data
01
0
01
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 36. Example of the ALC setting (Playback Path)
MS1402-E-06
Data
01
0
11
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[AK4679]
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST and FR bits
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Zero Crossing Timeout Period = [email protected]
Limiter and Recovery Step = 1
Fast Recovery = Enable (4 step)
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (IVL7-0)
(1) Addr=11H, Data=E1H
WR (IVR7-0)
(2) Addr=12H, Data=E1H
WR (REF7-0)
* The value of IVOL should be
(3) Addr=13H, Data=E1H
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0, FR)
(4) Addr=15H, Data=05H
WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN, LFST)
(5) Addr=16H, Data=01H
WR (ALC = “1”)
(6) Addr=17H, Data=03H
ALC Operation
Note : WR : Write
Figure 67. Registers set-up sequence at ALC operation
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■ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 bits and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example, in case of changing the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 37). When IVOLC bit is “0”, IVL7-0 and IVR7-0 bits
control Lch and Rch volume values independently. When IVOLC bit is “1”, IVL7-0 bits controls both channels. The
IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or
IVR7-0 bits are written during PMADL=PMADR=PMDML=PMDMR bits = “0”, IVOL operation starts with the written
values at the end of the ADC initialization cycle after PMADL, PMADR, PMDML or PMMDR bit is changed to “1”.
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
92H
91H
90H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+0.375
0.375dB
0.0
−0.375
:
−53.25
−53.625
−54
MUTE
Table 37. Input Digital Volume Setting
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(default)
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[AK4679]
■ Digital HPF1
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off frequencies of the
HPF1 are set by HPFC1-0 bits (Table 38). It is proportional to the sampling frequency (fs) and default is 3.4Hz (@fs =
44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (Recommend HPF enable).
HPFC1 bit
HPFC0 bit
0
0
1
1
0
1
0
1
fc
fs=44.1kHz
fs=22.05kHz
3.4Hz
1.7Hz
13.6Hz
6.8Hz
108.8Hz
54.4Hz
217.6Hz
108.8Hz
Table 38. HPF1 Cut-off Frequency
fs=8kHz
0.62Hz
2.47Hz
19.7Hz
39.5Hz
(default)
■ Side Tone Volume (SVOLA)
The AK4679 has the channel independent side tone volume (5 levels, 6dB step). The volume can be set by the
SVAL/R2-0 bits. The volume is included at mixing path from ALC to 5-band EQ. The output data of ALC is changed
from 0 to –24dB.
SVAL/R2-0 bits
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 39. Side Tone Volume A Code Table (N/A: Not available)
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[AK4679]
■ 5-Band Equalizer
The AK4679 has 5-Band Equalizer before DAC of Stereo CODEC. The 5-band Equalizer is selected ON/OFF by 5EQ
bit. When 5-band Equalizer is OFF, the audio data passes this block by 0dB gain. Each coefficient and transfer function of
5-band Equalizer is as follows. The coefficient must be set when 5EQ bit = “0” or PMEQ bit = “0”.
Gain range of 5-band equalizer is set from +12dB to -12dB (0.5dB step) independently by 5EQ1G5-0, 5EQ2G5-0,
5EQ3G5-0, 5EQ4G5-0 or 5EQ5G5-0 bits.
The 5-band Equalizer starts operation 4/fs(max) after when 5EQ bit = “1” and PMEQ bit = “1” is set.
1. EQ1: 1st order Low Pass Filter
<Low Pass Filter>
fs: Sampling frequency
fc: Cut-off frequency
k: Filter gain
Register setting (Note 78)
5E1A[13:0] bits =A, 5E1B[13:0] bits =B
(MSB=5E1A13, 5E1B13; LSB=5E1A0, 5E1B0)
1 − 1 / tan (πfc/fs)
1
A=k x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
h1L (z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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[AK4679]
2. EQ2, EQ3, EQ4: Equalizer
5E2A15-0, 5E2B15-0 and 5E2C15-0 bits set the coefficient of EQ2. 5E3A15-0, 5E3B15-0 and 5E3C15-0 bits set the
coefficient of EQ3. 5E4A15-0, 5E4B15-0 and 5E4C15-0 bits set the coefficient of EQ4.
fs: Sampling frequency
fo2 ~ fo4: Center frequency
fb2 ~ fb4: Band width where the gain is 3dB different from center frequency
k2 ~ k4: Filter gain
Register setting (Note 78)
EQ2: 5E2A[15:0] bits =A1, 5E2B[15:0] bits =B1, 5E2C[15:0] bits =C2
EQ3: 5E3A[15:0] bits =A2, 5E3B[15:0] bits =B2, 5E3C[15:0] bits =C3
EQ4: 5E4A[15:0] bits =A3, 5E4B[15:0] bits =B3, 5E4C[15:0] bits =C4
(MSB=5E2A15, 5E2B15, 5E2C15, 5E3A15, 5E3B15, 5E3C15, 5E4A15, 5E4B15, 5E4C15; LSB= 5E2A0,
5E2B0, 5E2C0, 5E3A0, 5E3B0, 5E3C0, 5E4A0, 5E4B0, 5E4C0)
An = kn x
tan (πfb n/fs)
2
, B n = cos(2π fon/fs) x
1 + tan (πfbn /fs)
1 + tan (πfbn /fs)
,
Cn =
1 − tan (πfbn /fs)
1 + tan (πfbn /fs)
(n = 2, 3, 4)
Transfer function
1 − z −2
hn (z) = An
1− B nz −1 − Cn z −2
(n = 2, 3, 4)
The center frequency should be set as below.
fon / fs < 0.497
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[AK4679]
3. EQ5: 1st order High Pass Filter
<High Pass Filter>
fs: Sampling frequency
fc: Cut-off frequency
k: Filter gain
Register setting (Note 78)
5E5A[13:0] bits =A, 5E5B[13:0] bits =B
(MSB=5E5A13, 5E5B13; LSB=5E5A0, 5E5B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=k x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer Function
1 − z −1
h5H (z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
Note 78. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
Total Transfer Function:
H(z) = K1 x h1L (z) + K2 x h2(z) + K3 x h3 (z) + K4 x h4(z) + K 5 x h5H(z)
K1 ~ 5: EQ Gain (+12 ~ -12dB, 0.5dB step). This value is changed by control register.
K1: 5EQ1G5-0 bits (Addr=6AH)
K2: 5EQ2G5-0 bits (Addr=6BH)
K3: 5EQ3G5-0 bits (Addr=6CH)
K4: 5EQ4G5-0 bits (Addr=6DH)
K5: 5EQ5G5-0 bits (Addr=6EH)
Default Center Frequency (Sampling Frequency = 44.1kHz):
EQ1: fc=100Hz
EQ2: fo2=250Hz (fb2=50Hz)
EQ3: fo3=1kHz (fb3=200Hz)
EQ4: fo4=3.5kHz (fb4=700Hz)
EQ5: fc=10kHz
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[AK4679]
EQ1G5-0 bits
EQ1G5-0 bits
EQ2G5-0 bits
EQ2G5-0 bits
EQ3G5-0 bits
GAIN (dB)
EQ3G5-0 bits
GAIN (dB)
EQ4G5-0 bits
EQ4G5-0 bits
EQ5G5-0 bits
EQ5G5-0 bits
30H
17H
+0.5
−12
2FH
16H
+1
−11.5
2EH
15H
+1.5
−11
2DH
14H
+2
−10.5
2CH
13H
+2.5
−10
2BH
12H
+3
−9.5
2AH
11H
+3.5
−9
29H
10H
+4
−8.5
28H
0FH
+4.5
−8
27H
0EH
+5
−7.5
26H
0DH
+5.5
−7
25H
0CH
+6
−6.5
24H
0BH
+6.5
−6
23H
0AH
+7
−5.5
22H
09H
+7.5
−5
21H
08H
+8
−4.5
20H
07H
+8.5
−4
1FH
06H
+9
−3.5
1EH
05H
+9.5
−3
1DH
04H
+10
−2.5
1CH
03H
+10.5
−2
1BH
02H
+11
−1.5
1AH
01H
+11.5
−1
19H
00H
+12
−0.5
18H
0
Table 40. 5-band Equalizer Gain Setting (Default: 0dB)
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[AK4679]
■ Dynamic Range Control
DRC Block
PMDRC
LPF
DLLPF1-0
DLLA13-0
DLLB13-0
DATT-A
SMUTE
Mono/
Stereo
DRCM1-0
LPF
NSLPF
NSLA13-0
NSLB13-0
Noise
Suppression
HPF
NSHPF
NSHA13-0
NSHB13-0
NSCE
NSTHL4-0
NSTHH4-0
NSREF3-0
NSATT2-0
NSGAIN2-0
NSIAFS1-0
NSOAFS1-0
HPF
LPF
DMHPF1-0
DMHA13-0
DMHB13-0
DMLPF1-0
DMLA13-0
DMLB13-0
HPF
DHHPF1-0
DHHA13-0
DHHB13-0
VOLL
DVLCL
VL1X/Y5-0
VL2X/Y5-0
VL3X/Y4-0
L1G6-0
L2G6-0
L3G6-0
L4G6-0
VOLM
DVLCM
VM1X/Y5-0
VM2X/Y5-0
VM3X/Y4-0
M1G6-0
M2G6-0
M3G6-0
M4G6-0
VOLH
VH1X/Y5-0
VH2X/Y5-0
VH3X/Y4-0
H1G6-0
H2G6-0
H3G6-0
H4G6-0
VOL
DRC
Limiter
DRCC1-0
DLMAT1-0
DRGAIN1-0
DVLCH
DAF1-0
DVLMAT2-0
DVRGAIN2-0
Figure 68. DRC Functions and Signal Path
DRCM1-0 bits select stereo or mono of DRC input data. In case of mono mode, the same data is input to both channels.
DRCM1 bit
DRCM0 bit
Lch
Rch
0
0
L
R
(default)
0
1
L
L
1
0
R
R
1
1
N/A
Table 41. DRC Stereo/Mono Select (N/A: Not available)
1. Noise Suppression Block
(1) Low Pass Filter (LPF)
This is composed with 1st order LPF. NSLA13-0 bits and NSLB13-0 bits set the coefficient of LPF. NSLPF bit controls
ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set
when NSLPF bit = “0” or PMDRC bit = “0”. The LPF starts operation 4/fs(max) after when NSLPF bit = “1” and
PMDRC bit = “1” are set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting
LPF: NSLA[13:0] bits =A, NSLB[13:0] bits =B
(MSB=NSLA13, NSLB13; LSB=NSLA0, NSLB0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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DAC
[AK4679]
(2) High Pass Filter (HPF)
This is composed 1st order HPF. The coefficient of HPF is set by NSHA13-0 bits and NSHB13-0 bits. NSHPF bit
controls ON/OFF of the HPF. When the HPF is OFF, the audio data passes this block by 0dB gain. The coefficient must
be set when NSHPF bit = “0” or PMDRC bit = “0”. The HPF starts operation 4/fs(max) after when NSHPF bit = “1” and
PMDRC bit = “1” are set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting
HPF: NSHA[13:0] bits =A, NSHB[13:0] bits =B
(MSB=NSHA13, NSHB13; LSB=NSHA0, NSHB0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(3) Noise Suppression
The Noise Suppression is enabled when NSCE bit (Noise suppression enable bit) = “1” during DRC operation (PMDRC
bit = “1”). This function attenuates output signal level automatically when minute amount of the signal is input.
NSCE bit: Noise Suppression Enable
0: Disable (default)
1: Enable
(3-1) Noise Level Suppressing Operation
The output signal is suppressed when the input moving average level set by NSIAF1-0 bits (Table 42) is lower than
“Noise Suppression Threshold Low Level” set by NSTHL4-0 bits (Table 43) during the normal operation.
This operation attenuats the volume automatically to the reference level set by NSREF3-0 bits (Table 44) with the soft
transition of the attenuation speed set by NSATT2-0 bits (Table 45).
Moving Average Parameter
fs=8kHz
fs=16kHz fs=44.1kHz
00
256/fs
32ms
16ms
5.8ms
01
512/fs
64ms
32ms
11.6ms
10
1024/fs
128ms
64ms
23.2ms
(default)
11
2048/fs
256ms
128ms
46.4ms
Table 42. Moving Average Parameter Setting at Noise Suppression Off
NSIAF1-0 bits
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[AK4679]
Noise Suppression
Step
Threshold Low Level [dB]
−36.0
−37.5
−39.0
:
1.5dB
−60.0
:
−81.0
−82.5
Table 43. Noise Suppression Threshold Low Level
NSTHL4-0 bits
00H
01H
02H
:
10H
:
1EH
1FH
(default)
NSREF3-0 bits
GAIN [dB]
Step
0H
(default)
−9
1H
−12
2H
−15
:
:
AH
−39
3dB
BH
−42
CH
−45
DH
−48
EH
−51
FH
−54
Table 44. Reference Value Setting when Noise Suppression is ON
NSATT2
bit
0
0
0
0
1
1
1
1
NSATT1 NSATT0
ATT Speed
bit
bit
8kHz
16kHz
44.1kHz
0
0
1.1dB/s
2.1dB/s
5.8dB/s
0
1
2.1dB/s
4.2dB/s
11.7dB/s
1
0
4.2dB/s
8.5dB/s
23.4dB/s
1
1
8.5dB/s
17.0dB/s
46.8dB/s
0
0
17.0dB/s
33.9dB/s
93.5dB/s
0
1
67.9dB/s
187.1dB/s
33.9dB/s
1
0
N/A
1
1
Table 45. Noise Suppression ATT Speed Setting (N/A: Not available)
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(default)
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[AK4679]
(3-2) Noise Suppression → Normal Operation
During noise suppressing operation, if the input moving average level set by NSOAF1-0 bits (Table 46) exceeds Noise
Suppression Threshold High Level set by NSTHH4-0 bits (Table 47), the operation switches to normal operation from
noise suppressing operation.
This recovery operation sets the volume automatically to 0dB with the soft transition of the recovery speed set by
NSGAIN2-0 bits (Table 48).
Moving Average Parameter
fs=8kHz
fs=16kHz fs=44.1kHz
00
4/fs
0.5ms
0.3ms
0.1ms
01
8/fs
1.0ms
0.5ms
0.2ms
10
16/fs
2.0ms
1.0ms
0.4ms
(default)
11
32/fs
4.0ms
2.0ms
0.7ms
Table 46. Moving Average Parameter Setting at Noise Suppression On
NSOAF1-0 bits
Noise Suppression
Step
Threshold High Level [dBFS]
−36.0
−37.5
−39.0
:
1.5dB
−60.0
:
−81.0
−82.5
Table 47. Noise Suppression Threshold High Level
NSTHH4-0 bits
00H
01H
02H
:
10H
:
1EH
1FH
(default)
NSGAIN2 NSGAIN1 NSGAIN0
Recovery Speed
bit
bit
bit
8kHz
16kHz
44.1kHz
0
0
0
0.3dB/ms
0.5dB/ms
1.5dB/ms
0
0
1
0.5dB/ms
1.1dB/ms
3.0dB/ms (default)
0
1
0
1.1dB/ms
2.2dB/ms
6.0dB/ms
0
1
1
2.2dB/ms
4.4dB/ms
12.2dB/ms
1
0
0
4.5dB/ms
9.0dB/ms
24.7dB/ms
1
0
1
N/A
1
1
0
1
1
1
Table 48. Recovery Speed Setting from Noise Suppression to Normal Operation (N/A: Not available)
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[AK4679]
2. Dynamic Volume Control Block
The AK4679 has the dynamic volume control (DVLC) circuits before DRC. DVLC divides frequency range into three
band (Low, Middle, High) and controls independently.
(1) Low Frequency Range
LPF
VOLL
DVLCL
VL1X/Y5-0
VL2X/Y5-0
VL3X/Y4-0
L1G6-0
L2G6-0
L3G6-0
L4G6-0
DLLPF1-0
“0” data
(DLLPF1-0 bits = “00”) DLLA13-0
DLLB13-0
Figure 69. DVLC Functions and Signal Path for Low Frequency Range
(1-1) Low Pass Filter (LPF)
This is composed with 1st or 2nd order LPF. DLLA13-0 bits and DLLB13-0 bits set the coefficient of LPF. DLLPF1-0
bits controls ON/OFF of the LPF. When the LPF is OFF, the audio data does not pass this block. The coefficient must be
set when DLLPF1-0 bits = “00” or PMDRC bit = “0”. The LPF starts operation 4/fs(max) after when DLLPF1-0 bits =
“01” or “10” and PMDRC bit = “1” are set.
DLLPF1 bit
DLLPF0 bit
Mode
0
0
OFF (“0” data)
(default)
0
1
1st order LPF
1
0
2nd order LPF
1
1
N/A
Table 49. DLLPF Mode Setting (N/A: Not available)
fs: Sampling frequency
fc: Cut-off frequency
Register setting
LPF: DLLA[13:0] bits =A, DLLB[13:0] bits =B
(MSB=DLLA13, DLLB13; LSB=DLLA0, DLLB0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function (1st order)
1 + z −1
H(z) = A
−1
1 + Bz
Transfer function (2nd order)
1 + z −1
1 + z −1
H(z) = A
x A
−1
1 + Bz
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.002 (fc min = 88Hz at 44.1kHz)
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[AK4679]
(1-2) Dynamic Volume Control Curve
The inflection points of the DVLC curve is set by three coordinate values (VL1X5-0, VL1Y5-0, VL2X5-0, VL2Y5-0,
VL3X4-0 and VL3Y4-0 bits). The setting of three inflection points are calculated the values of (X1L, Y1L), (X2L, Y2L),
(X3L, Y3L) in dB. The inflection points should be set in such a way that VL1X ≤ VL2X ≤ VL3X, VL1Y ≤ VL2Y ≤ VL3Y.
And the each slope is set by L1G6-0, L2G6-0, L3G6-0 and L4G6-0 bits. X4L is fixed full-scale, Y4L is calculated by the
L4G value. The initial value of the DVLC gain is set by the L1G.
Full scale
(X3L, Y3L)
DVLC Output Level
(X2L, Y2L)
(X1L, Y1L)
(X4L, Y4L)
L4G
L3G
L2G
L1G
(0, 0)
DVLC Input Level
Full scale
Figure 70. DVLC Curve for Low Frequency Range
VL1X/Y5-0 bits Dynamic Volume Control Point
Step
VL2X/Y5-0 bits
[dBFS]
00H
0
(default)
01H
−1.5
02H
−3.0
1.5dB
:
:
2EH
−69.0
2FH
−70.5
30H
N/A
N/A
:
:
3FH
N/A
Table 50. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available)
VL3X/Y4-0 bits
00H
01H
02H
:
1EH
1FH
Dynamic Volume Control Point
Step
[dBFS]
0
−1.5
−3.0
1.5dB
:
−45.0
−46.5
Table 51. DVLC Point Setting for X/Y3
MS1402-E-06
(default)
2013/02
- 89 -
[AK4679]
Slope Setting
Y1L
L1G =
X1L
L3G =
x 16, L2G =
(Y3L – Y2L )
(X3L – X2L)
(Y2L – Y1L )
(X2L – X1L)
x 16, L4G =
x 16,
(Y4L – Y3L )
(X4L – X3L)
x 16,
The results calculated by the equations above should be rounded off to integer. These integers are slope data.
L1G6-0 bits, L2G6-0 bits,
Slope Data
L3G6-0 bits, L4G6-0 bits
00H
0
(default)
01H
1
02H
2
:
:
7EH
126
7FH
127
Table 52. DVLC Slope Setting for Low Frequency Range
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[AK4679]
(2) Middle Frequency Range
Bypass (DMHPF1-0 = DMLPF1-0 bits = “00”)
HPF
LPF
DMHPF1-0
DMHA13-0
DMHB13-0
DMLPF1-0
DMLA13-0
DMLB13-0
VOLM
DVLCM
VM1X/Y5-0
VM2X/Y5-0
VM3X/Y4-0
M1G6-0
M2G6-0
M3G6-0
M4G6-0
Figure 71. DVLC Functions and Signal Path for Middle Frequency Range
(2-1) High Pass Filter (HPF)
This is composed with 1st or 2nd order HPF. The coefficient of HPF is set by DMHA13-0 bits and DMHB13-0 bits. HPF
bit controls ON/OFF of the HPF. When the HPF is OFF, the audio data passes this block by 0dB gain. The coefficient
must be set when DMHPF1-0 bits = “00” or PMDRC bit = “0”. The HPF starts operation 4/fs(max) after when
DMHPF1-0 bits = “01” or “10” and PMDRC bit = “1” are set.
DMHPF1 bit DMHPF0 bit
Mode
0
0
Bypass
(default)
0
1
1st order HPF
1
0
2nd order HPF
1
1
N/A
Table 53. DMHPF Mode Setting (N/A: Not available)
fs: Sampling frequency
fc: Cut-off frequency
Register setting
HPF: DMHA[13:0] bits =A, DMHB[13:0] bits =B
(MSB=DMHA13, DMHB13; LSB=DMHA0, DMHB0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function (1st order)
1 − z −1
H(z) = A
−1
1 + Bz
Transfer function (2nd order)
1 − z −1
1 − z −1
H(z) = A
x A
1 + Bz −1
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
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[AK4679]
(2-2) Low Pass Filter (LPF)
This is composed with 1st or 2nd order LPF. DLLA13-0 bits and DMLB13-0 bits set the coefficient of LPF. DMLPF1-0
bits controls ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient
must be set when DMLPF1-0 bits = “00” or PMDRC bit = “0”. The LPF starts operation 4/fs(max) after when DMLPF1-0
bits = “01” or “10” and PMDRC bit = “1” are set.
DMLPF1 bit DMLPF0 bit
Mode
0
0
Bypass
(default)
0
1
1st order LPF
1
0
2nd order LPF
1
1
N/A
Table 54. DMLPF Mode Setting (N/A: Not available)
fs: Sampling frequency
fc: Cut-off frequency
Register setting
LPF: DMLA[13:0] bits =A, DMLB[13:0] bits =B
(MSB=DMLA13, DMLB13; LSB=DMLA0, DMLB0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function (1st order)
1 + z −1
H(z) = A
−1
1 + Bz
Transfer function (2nd order)
1 + z −1
1 + z −1
H(z) = A
x A
−1
1 + Bz
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
MS1402-E-06
2013/02
- 92 -
[AK4679]
(2-3) Dynamic Volume Control Curve
The inflection points of the DVLC curve is set by three coordinate values (VM1X5-0, VM1Y5-0, VM2X5-0, VM2Y5-0,
VM3X4-0 and VM3Y4-0 bits). The setting of three inflection points are calculated the values of (X1M, Y1M), (X2M,
Y2M), (X3M, Y3M) in dB. The inflection points should be set in such a way that VM1X ≤ VM2X ≤ VM3X, VM1Y ≤
VM2Y ≤ VM3Y. And the each slope is set by M1G6-0, M2G6-0, M3G6-0 and M4G6-0 bits. X4M is fixed full-scale, Y4M
is calculated by the M4G value. The initial value of the DVLC gain is set by the M1G. When the HPF and LPF is bypass
(DMHPF1-0 = DMLPF1-0 bits = “00”), the audio data passes this block by 0dB gain.
Full scale
(X3M, Y3M)
DVLC Output Level
(X2M, Y2M)
(X1M, Y1M)
(X4M, Y4M)
M4G
M3G
M2G
M1G
(0, 0)
DVLC Input Level
Full scale
Figure 72. DVLC Curve for Middle Frequency Range
VM1X/Y5-0 bits Dynamic Volume Control Point
Step
VM2X/Y5-0 bits
[dBFS]
00H
0
(default)
01H
−1.5
02H
−3.0
1.5dB
:
:
2EH
−69.0
2FH
−70.5
30H
N/A
N/A
:
:
3FH
N/A
Table 55. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available)
VM3X/Y4-0 bits
00H
01H
02H
:
1EH
1FH
Dynamic Volume Control Point
Step
[dBFS]
0
−1.5
−3.0
1.5dB
:
−45.0
−46.5
Table 56. DVLC Point Setting for X/Y3
MS1402-E-06
(default)
2013/02
- 93 -
[AK4679]
Slope Setting
Y1M
M1G =
X1M
M3G =
x 16, M2G =
(Y3M – Y2M)
(X3M – X2M)
(Y2M – Y1M)
(X2M – X1M)
x 16, M4G =
x 16,
(Y4M – Y3M)
(X4M – X3M)
x 16,
The results calculated by the equations above should be rounded off to integer. These integers are slope data.
M1G6-0 bits, M2G6-0 bits,
Slope Data
M3G6-0 bits, M4G6-0 bits
00H
0
(default)
01H
1
02H
2
:
:
7EH
126
7FH
127
Table 57. DVLC Slope Setting for Middle Frequency Range
MS1402-E-06
2013/02
- 94 -
[AK4679]
(3) High Frequency Range
HPF
VOLH
DHHPF1-0
“0” data
(DHHPF1-0 bits = “00”) DHHA13-0
DHHB13-0
DVLCH
VH1X/Y5-0
VH2X/Y5-0
VH3X/Y4-0
H1G6-0
H2G6-0
H3G6-0
H4G6-0
Figure 73. DVLC Functions and Signal Path for High Frequency Range
(3-1) High Pass Filter (HPF)
This is composed with 1st or 2nd order HPF. The coefficient of HPF is set by DHHA13-0 bits and DHHB13-0 bits. HPF
bit controls ON/OFF of the HPF. When the HPF is OFF, the audio data does not pass this block. The coefficient must be
set when DHHPF1-0 bits = “00” or PMDRC bit = “0”. The HPF starts operation 4/fs(max) after when DHHPF1-0 bits =
“01” or “10” and PMDRC bit = “1” are set.
DHHPF1 bit DHHPF0 bit
Mode
0
0
OFF (“0” data)
(default)
0
1
1st order HPF
1
0
2nd order HPF
1
1
N/A
Table 58. DHHPF Mode Setting (N/A: Not available)
fs: Sampling frequency
fc: Cut-off frequency
Register setting
HPF: DHHA[13:0] bits =A, DHHB[13:0] bits =B
(MSB=DHHA13, DMHB13; LSB=DHHA0, DHHB0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function (1st order)
1 − z −1
H(z) = A
−1
1 + Bz
Transfer function (2nd order)
1 − z −1
1 − z −1
H(z) = A
x A
1 + Bz −1
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
MS1402-E-06
2013/02
- 95 -
[AK4679]
(3-2) Dynamic Volume Control Curve
The inflection points of the DVLC curve is set by three coordinate values (VH1X5-0, VH1Y5-0, VH2X5-0, VH2Y5-0,
VH3X4-0 and VH3Y4-0 bits). The setting of three inflection points are calculated the values of (X1H, Y1H), (X2H,
Y2HH), (X3H, Y3H) in dB. The inflection points should be set in such a way that VH1X ≤ VH2X ≤ VH3X, VH1Y ≤
VH2Y ≤ VH3Y. And the each slope is set by H1G6-0, H2G6-0, H3G6-0 and H4G6-0 bits. X4H is fixed full-scale, Y4H is
calculated by the H4G value. The initial value of the DVLC gain is set by the H1G.
Full scale
(X3H, Y3H)
DVLC Output Level
(X2H, Y2H)
(X1H, Y1H)
(X4H, Y4H)
H4G
H3G
H2G
H1G
(0, 0)
DVLC Input Level
Full scale
Figure 74. DVLC Curve for High Frequency Range
VH1X/Y5-0 bits Dynamic Volume Control Point
Step
VH2X/Y5-0 bits
[dBFS]
00H
0
(default)
01H
−1.5
02H
−3.0
1.5dB
:
:
2EH
−69.0
2FH
−70.5
30H
N/A
N/A
:
:
3FH
N/A
Table 59. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available)
VH3X/Y4-0 bits
00H
01H
02H
:
1EH
1FH
Dynamic Volume Control Point
Step
[dBFS]
0
−1.5
−3.0
1.5dB
:
−45.0
−46.5
Table 60. DVLC Point Setting for X/Y3
MS1402-E-06
(default)
2013/02
- 96 -
[AK4679]
Slope Setting
Y1H
H1G =
X1H
H3G =
x 16, H2G =
(Y3 H – Y2H )
(X3H – X2H)
(Y2 H – Y1H )
(X2H – X1H)
x 16, H4G =
x 16,
(Y4 H – Y3H )
(X4H – X3H)
x 16
The results calculated by the equations above should be rounded off to integer. These integers are slope data.
H1G6-0 bits, H2G6-0 bits,
Slope Data
H3G6-0 bits, H4G6-0 bits
00H
0
(default)
01H
1
02H
2
:
:
7EH
126
7FH
127
Table 61. DVLC Slope Setting for High Frequency Range
MS1402-E-06
2013/02
- 97 -
[AK4679]
(4) Dynamic Volume Control
The DVLC automatically controls the volume at the attenuation speed set by DVLMAT2-0 bits (Table 63) or the recovery
speed set by DVRGAIN2-0 bits (Table 64) in such a way that the input moving average level set by DAF1-0 bits (Table 62)
is reached the output level of the DVLC curve set by each frequency range.
DAF1-0 bits
00
01
10
11
DVLMAT2
bit
0
0
0
0
1
1
1
1
DVRGAIN2
bit
0
0
0
0
1
1
1
1
Moving Average Parameter
fs=8kHz
fs=16kHz fs=44.1kHz
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
2048/fs
256ms
128ms
46.4ms
(default)
Table 62. DVLC Moving Average Parameter Setting
DVLMAT1 DVLMAT0
ATT Speed
bit
bit
8kHz
16kHz
44.1kHz
0
0
1.1dB/s
2.1dB/s
5.8dB/s
0
1
2.1dB/s
4.2dB/s
11.7dB/s
1
0
4.2dB/s
8.5dB/s
23.4dB/s
1
1
8.5dB/s
17.0dB/s
46.8dB/s
0
0
17.0dB/s
33.9dB/s
93.5dB/s
0
1
33.9dB/s
67.9dB/s
187.1dB/s
1
0
67.9dB/s
135.8dB/s
374.3dB/s
1
1
N/A
Table 63. DVLC ATT Speed Setting (N/A: Not available)
DVRGAIN0
Recovery Speed
bit
bit
8kHz
16kHz
44.1kHz
0
0
0.07dB/s
0.13dB/s
0.37dB/s
0
1
0.13dB/s
0.27dB/s
0.73dB/s
1
0
0.27dB/s
0.53dB/s
1.46dB/s
1
1
0.53dB/s
1.06dB/s
2.92dB/s
0
0
1.06dB/s
2.12dB/s
5.84dB/s
0
1
2.12dB/s
4.24dB/s
11.7dB/s
1
0
4.24dB/s
8.48dB/s
23.4dB/s
1
1
N/A
Table 64. DVLC Recovery Speed Setting (N/A: Not available)
(default)
DVRGAIN1
MS1402-E-06
(default)
2013/02
- 98 -
[AK4679]
3. Dynamic Range Control Block
The AK4679 has the dynamic range control (DRC) circuits. The compression level is selected in three levels and set by
DRCC1-0 bits (Table 65).
When the DRC is OFF (DRCC1-0 bits = “00”), the audio data passes this block by 0dB gain. However limiter and
recovery operation is always ON. The compression level must be set when PMDRC bit = “0”.
DRC Output Level (dB)
0dB
DRC Off
Low
Mid
High
-6dB
-6dB
0dB
+3.5dB
DRC Input Level (dB)
Figure 75. DRC Gain Curve
DRCC1 bit
DRCC0 bit
Compression Level
0
0
OFF
0
1
Low
1
0
Middle
1
1
High
Table 65. DRC Compression Level Setting
1.
(default)
DRC Limiter Operation
During the DRC limiter operation, when the output level of DRC exceeds full-scale, the DRC volume are attenuated
automatically with the soft transition in the attenuation speed set by DLMAT2-0 bits (Table 66).
DLMAT2
bit
0
0
0
0
1
1
1
1
ATT Speed
DLMAT1 DLMAT0
bit
bit
8kHz
16kHz
44.1kHz
0
0
0.1dB/ms
0.3dB/ms
0.7dB/ms
0
1
0.3dB/ms
0.5dB/ms
1.5dB/ms
1
0
0.5dB/ms
1.1dB/ms
3.0dB/ms
1
1
1.1dB/ms
2.2dB/ms
6.0dB/ms
0
0
2.2dB/ms
4.4dB/ms
12.2dB/ms
0
1
4.5dB/ms
9.0dB/ms
24.7dB/ms
1
0
N/A
1
1
Table 66. DRC ATT Speed Setting (N/A: Not available)
MS1402-E-06
(default)
2013/02
- 99 -
[AK4679]
2.
DRC Recovery Operation
During the DRC recovery operation, when the DRC volume reaches 0dB or the output level of DRC exceeds limiter
detection level, the DRC volume are set automatically with the soft transition in the recovery speed set by DRGAIN1-0
bits (Table 67).
DRGAIN1
bit
0
0
1
1
Recovery Speed
DRGAIN0
bit
8kHz
16kHz
44.1kHz
0
1.1dB/s
2.1dB/s
5.9dB/s
1
2.1dB/s
4.2dB/s
11.7dB/s
0
4.2dB/s
8.5dB/s
23.4dB/s
1
8.5dB/s
17.0dB/s
46.7dB/s
Table 67. DRC Recovery Speed Setting
MS1402-E-06
(default)
2013/02
- 100 -
[AK4679]
■ Digital Output Volume (DATT-A)
The AK4679 has a digital output volume (DATT-A: 128 levels, 0.5dB step, Mute). The volume can be set by the OVL6-0
and OVR6-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +6 to –57dB
or MUTE. When the OVOLC bit = “1”, the OVL6-0 bits control both Lch and Rch attenuation levels. When the OVOLC
bit = “0”, the OVL6-0 bits control Lch level and OVR6-0 bits control Rch level. This volume has a soft transition
function. The OVTM bit sets the transition time between set values of OVL/R6-0 bits as either 128/fs or 256/fs (Table
69). When OVTM bit = “1”, a soft transition between the set values occurs (256 levels). It takes 256/fs
([email protected]=44.1kHz) from 00H (+6dB) to 7FH (MUTE).
OVL/R6-0 bits
Gain
Step
00H
+6.0dB
01H
+5.5dB
02H
+5.0dB
:
:
0.5dB
0CH
0dB
:
:
7DH
−56.5dB
7EH
−57.0dB
7FH
MUTE (−∞)
Table 68. Digital Volume A Code Table
OVTM bit
0
1
(default)
Transition time between OVL/R6-0 bits = 00H and 7FH
Setting
fs=8kHz
fs=44.1kHz
128/fs
16ms
2.9ms
256/fs
32ms
5.8ms
Table 69. Transition Time Setting of Digital Output Volume A
MS1402-E-06
(default)
2013/02
- 101 -
[AK4679]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit is changed to “1”, the output signal is
attenuated to −∞ (“0”) during the cycle set by the OVTM bit. When the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the value set by the OVL/R6-0 bits during the cycle set of the
OVTM bit. If the soft mute is cancelled within the cycle set by the OVTM bit after starting the operation, the attenuation
is discontinued and returned to the value set by the OVL/R6-0 bits. The soft mute is effective for changing the signal
source without stopping the signal transmission (Figure 76).
S MU TE bit
O VT M bit
O V L/R6 -0 bits
O VT M bit
(1 )
(3 )
A tte nu a tion
-∞
GD
(2 )
GD
A na lo g O u tpu t
Figure 76. Soft Mute Function
(1) The output signal is attenuated until −∞ (“0”) in the cycle set by the OVTM bit.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle set by the OVTM bit, the attenuation is discounted and returned to the
value set by the OVL/R6-0 bits.
MS1402-E-06
2013/02
- 102 -
[AK4679]
■ Digital Volume for Recording of Received Voice (DATT-B)
The AK4679 has a digital output volume control (DATT-B: 128 levels, 0.5dB step, Mute) for recording of received voice.
The volume can be set by the BVL6-0 bits. This volume is included in SRCAI blocks. The output data of SRCAI is
changed from +6 to –57dB or MUTE. This volume control is in common for left and right channels. This volume has a
soft transit function. The OVTMB bit sets the transition time between set values of BVL6-0 bits as either 128/fs or 256/fs
(Table 71). When OVTMB bit = “1”, a soft transition between the set values occurs (256 levels). It takes 256/fs (=5.8ms
@ fs=44.1kHz, PMMIX bit = “1”) from 00H (+6dB) to 7FH (MUTE).
BVL6-0 bits
00H
01H
02H
:
0CH
:
7DH
7EH
7FH
Gain
Step
+6.0dB
+5.5dB
+5.0dB
:
0.5dB
0dB
:
−56.5dB
−57.0dB
MUTE (−∞)
Table 70. Digital Volume B Table
(default)
Transition time between BVL6-0 bits = 00H and 7FH
Setting
fs=8kHz
fs=44.1kHz
0
128/fs
16ms
2.9ms
1
256/fs
32ms
5.8ms
(default)
(PMMIX bit = “0”: fs = SYNCB Frequency, PMMIX bit = “1”: fs = LRCK Frequency)
Table 71. Transition Time Setting of Digital Output Volume B
OVTMB bit
■ Digital Volume for Received Voice (DATT-C)
The AK4679 has a digital output volume control (DATT-C: 128 levels, 0.5dB step, Mute) for recording of received voice.
The volume can be set by the CVL6-0 bits. The volume range is from +6 to –57dB or MUTE. This volume control is in
common for left and right channels. This volume has a soft transit function. The OVTMB bit sets the transition time
between set values of CVL6-0 bits as either 128/fs or 256/fs (Table 73). When OVTMB bit = “1”, a soft transition
between the set values occurs (256 levels). It takes 256/fs (=5.8ms @ fs =44.1kHz, PMMIX bit = “1”) from 00H (+6dB)
to 7FH (MUTE).
CVL6-0 bits
00H
01H
02H
:
0CH
:
7DH
7EH
7FH
Gain
Step
+6.0dB
+5.5dB
+5.0dB
:
0.5dB
0dB
:
−56.5dB
−57.0dB
MUTE (−∞)
Table 72. Digital Volume C Table
(default)
Transition time between CVL6-0 bits = 00H and 7FH
Setting
fs=8kHz
fs=44.1kHz
0
128/fs
16ms
2.9ms
1
256/fs
32ms
5.8ms
(default)
(PMMIX bit = “0”: fs = SYNCB Frequency, PMMIX bit = “1”: fs = LRCK Frequency)
Table 73. Transition Time Setting of Digital Output Volume C
OVTMB bit
MS1402-E-06
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■ Side Tone Volume for B/T Phone Call (SVOLB)
The AK4679 has the side tone volume control (5 levels, 6dB step) for B/T phone call. The volume can be set by the
SVB2-0 bits. The volume range is from 0dB to -24dB.
SVB2-0 bits
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 74. Side Tone Volume B Table (N/A: Not available)
■ Digital Volume for B/T MIC Input (BIVOL)
The AK4679 has the digital volume control (5 levels, 6dB step) for B/T mic input. The volume can be set by the BIV2-0
bits .The volume rage is from 0 to –24dB.
BIV2-0 bits
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 75. SDTIB Volume Table (N/A: Not available)
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■ Path & Mixing Setting of Digital Block (Figure 61)
PMADL, PMADR, PMDML and PMDMR bits set both ADC power management and output data selection. In case of
mono operation, the same data is output to both channel slots.
PMADL bit PMADR bit
ADC Lch data
ADC Rch data
0
0
All “0”
All “0”
(default)
0
1
Rch Input Signal
Rch Input Signal
1
0
Lch Input Signal
Lch Input Signal
1
1
Lch Input Signal
Rch Input Signal
Table 76. ADC Mono/Stereo Select (Analog MIC: DMIC bit = “0”)
PMDML bit PMDMR bit
ADC Lch data
ADC Rch data
0
0
All “0”
All “0”
(default)
0
1
Rch Input Signal
Rch Input Signal
1
0
Lch Input Signal
Lch Input Signal
1
1
Lch Input Signal
Rch Input Signal
Table 77. ADC Mono/Stereo Select (Digital MIC: DMIC bit = “1)
PFSEL bit select the input data of programmable filter.
PFSEL
Programmable Filter Input
0
ADC Output (selected by Table 76)
(default)
1
SDTI Input (selected by Table 84)
Table 78. Programmable Filter Input Signal Select
When ADM bit is “1”, ALC output data is output to both channels of SDTO and SVOLA as (L+R)/2, respectively.
ADM bit
Lch
Rch
0
L
R
(default)
1
(L+R)/2
(L+R)/2
Table 79. ALC Output Mono Mixing
PFSDO bit select the input data both SDTO and SVOLA.
PFSDO bit
0
1
SDTO and SVOLA Input
ADC Output (selected by Table 76)
Programmable Filter Output (selected by Table 79)
Table 80. SDTO, SVOLA Input Signal Select
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[AK4679]
SDOL1-0 and SDOR1-0 bits set the data mixing for each channel of SDTO from the data selected by Table 80 and
MIX1L/R output data.
SDOL1 bit
0
0
1
1
SDOL0 bit
0
1
0
1
SDTO Lch
Lch Signal selected by Table 80
MIX1L
(Lch Signal selected by Table 80) + (MIX1L)
(Lch Signal selected by Table 80)/2 + (MIX1L)/2
Table 81. SDTO Lch Output Mixing
SDOR1 bit
0
0
1
1
SDOR0 bit
0
1
0
1
SDTO Rch
Rch Signal selected by Table 80
MIX1R
(Rch Signal selected by Table 80) + (MIX1R)
(Rch Signal selected by Table 80)/2 + (MIX1R)/2
Table 82. SDTO Rch Output Mixing
(default)
(default)
When SDOD bit is “1”, SDTO output data can be disabled (fixed to “L”). Input data of SVOLA is not disabled.
SDOD bit
0
1
SDTO
Enable (Output)
Disable (“L” Output)
Table 83. SDTO Disable
(default)
SDIM1-0 bits select stereo or mono of SDTI input data. In case of mono mode, the same data is input to both channels.
SDIM1 bit SDIM0 bit
Lch
Rch
0
0
L
R
(default)
0
1
L
L
1
0
R
R
1
1
N/A
Table 84. SDTI Stereo/Mono Select (N/A: Not available)
PFMXL1-0 and PFMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table 84
and SVOLA output data.
PFMXL1 bit
0
0
1
1
PFMXL0 bit
5-band EQ Lch Input
0
Lch Signal selected by Table 84
1
SVOLA Lch
0
(Lch Signal selected by Table 84) + (SVOLA Lch)
1
N/A
Table 85. 5-band EQ Lch Input Mixing 1 (N/A: Not available)
PFMXR1 bit
0
0
1
1
PFMXR0 bit
5-band EQ Rch Input
0
Rch Signal selected by Table 84
1
SVOLA Rch
0
(Rch Signal selected by Table 84) + (SVOLA Rch)
1
N/A
Table 86. 5-band EQ Rch Input Mixing 1 (N/A: Not available)
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(default)
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SRMXL1-0 and SRMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table 85
/Table 86 and MIX1L/R output data.
SRMXL1 bit
SRMXL0 bit
5-band EQ Lch Input
0
0
Signal selected by Table 85
0
1
MIX1L
1
0
(Signal selected by Table 85) + (MIX1L)
1
1
N/A
Table 87. 5-band EQ Lch Input Mixing 2 (N/A: Not available)
SRMXR1 bit
SRMXR0 bit
5-band EQ Rch Input
0
0
Signal selected by Table 86
0
1
MIX1R
1
0
(Signal selected by Table 86) + (MIX1R)
1
1
N/A
Table 88. 5-band EQ Rch Input Mixing 2 (N/A: Not available)
(default)
(default)
DASEL1-0 bits select the input data of DAC.
DASEL1 bit
0
0
1
1
DASEL0 bit
DAC Lch
DAC Rch
0
DATT-A Lch
DATT-A Rch
1
DRC Lch
DRC Rch
0
SDTI Lch
SDTI Rch
1
N/A
Table 89. DAC Input Signal Select (N/A: Not available)
(default)
MX1L2-0 bits set the data mixing for Audio I/F Lch input.
MX1L2 bit
0
0
0
0
1
1
1
1
MX1L1 bit MX1L0 bit
Audio I/F Lch Input
0
0
DATT-B
(default)
0
1
BIVOL Lch
1
0
BIVOL Rch
1
1
((BIVOL Lch) + (BIVOL Rch))/2
0
0
(DATT-B) + (BIVOL Lch)
0
1
(DATT-B) + (BIVOL Rch)
1
0
((BIVOL Lch) + (BIVOL Rch))/2 + (DATT-B))/2
1
1
N/A
Table 90. Audio I/F Lch Input Mixing (N/A: Not available)
MX1R2-0 bits set the data mixing for Audio I/F Rch input.
MX1R2 bit
0
0
0
0
1
1
1
1
MX1R1 bit MX1R0 bit
Audio I/F Rch Input
0
0
DATT-B
(default)
0
1
BIVOL Lch
1
0
BIVOL Rch
1
1
((BIVOL Lch) + (BIVOL Rch))/2
0
0
(DATT-B) + (BIVOL Lch)
0
1
(DATT-B) + (BIVOL Rch)
1
0
((BIVOL Lch) + (BIVOL Rch))/2 + (DATT-B))/2
1
1
N/A
Table 91. Audio I/F Rch Input Mixing (N/A: Not available)
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MX2A1-0 bits set the data mixing for MIX2C input.
MX2A1 bit
0
0
1
1
MX2A0 bit
MIX2C Input
0
BIVOL Lch
1
BIVOL Rch
0
(BIVOL Lch ) + (BIVOL Rch)
1
((BIVOL Lch ) + (BIVOL Rch))/2
Table 92. MIX2C Input Mixing 1
(default)
MX2B1-0 bits set the data mixing for MIX2C input.
MX2B1 bit
0
0
1
1
MX2B0 bit
MIX2C Input
0
DATT-A Lch
1
DATT-A Rch
0
(DATT-A Lch ) + (DATT-A Rch)
1
((DATT-A Lch ) + (DATT-A Rch))/2
Table 93. MIX2C Input Mixing 2
(default)
MX2C1-0 bits set the data mixing for SRCAO and SVOLB input.
MX2C1 bit
0
0
1
1
MX2C0 bit
SRCAO/SVOLB Input
0
MIX2A
1
MIX2B
0
(MIX2A) + (MIX2B)
1
((MIX2A) + (MIX2B))/2
Table 94. SRCAO/SVOLB Input Mixing
(default)
MXSB2-0 bits set the data mixing for SRCBO input.
MXSB2
bit
MXSB1
bit
MXSB0
bit
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
0
1
SRCBO Lch
SRCBO Rch
DATT-A Lch
DATT-A Rch
(default)
DATT-A Lch
←
DATT-A Rch
←
(DATT-A Lch) + (DATT-A Rch)
←
((DATT-A Lch) + (DATT-A Rch))/2
←
((DATT-A Lch) + (DATT-A Rch))/2
←
+ (DATT-C)
Lch Signal selected by Table 80
Rch Signal selected by Table 80
DATT-C
←
Table 95. SRCBO Input Mixing
When SDOAD bit is “1”, SDTOA output data can be disabled (fixed to “L”). Input data of SVOLB is not disabled.
SDOAD bit
SDTOA
0
Enable (Output)
1
Disable (“L” Output)
Table 96. SDTOA Disable
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[AK4679]
SBMX1-0 bits set the data mixing from SDTIA input and SVOLB output. The mixed data is input to DATT-C.
SBMX1 bit
0
0
1
1
SBMX0 bit
DATT-C Input
0
SRCAI
1
SVOLB
0
(SRCAI) + (SVOLB)
1
N/A
Table 97. SDTOB Mixing (N/A: Not available)
(default)
When SDOBD bit is “1”, SDTOB output data can be disabled (fixed to “L”).
SDOBD bit
SDTOB
0
Enable (Output)
1
Disable (“L” Output)
Table 98. SDTOB Disable
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(default)
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[AK4679]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins in single-ended.
When DACL and DACR bits are “0” in normal operation (PMDAC=PML/RO bits = “1”, LOPS bit = “0”), output signal
is muted and LOUT/ROUT pins output common voltage (typ. 0.8 x AVDD). The load impedance is 10kΩ (min.). When
the PMLO=PMRO=LOPS bits = “0”, LOUT/ROUT enters power-down mode and the output is pulled-down to VSS1 by
100kΩ (typ). When the LOPS bit is “1”, LOUT/ROUT enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO and PMRO bits at LOPS bit = “1”. In this case, output signal line should be pulled-down to
VSS1 by 20kΩ after AC coupled as Figure 78. Rise/Fall time is 300ms (max) at C=1μF and AVDD=1.8V. When
PMLO=PMRO bits = “1” and LOPS bit = “0”, LOUT/ROUT is in normal operation. LVL2-0 bits control the volume of
LOUT/ROUT. When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R) mono signal.
LVL2-0 bits
DACL bit
DAC Lch
DACR bit x LOM bit
M
I
X
LOUT pin
M
I
X
ROUT pin
DACL bit x LOM bit
DACR bit
DAC Rch
Figure 77. Stereo Line Output
LOPS bit
0
1
LOPS bit
0
1
PMLO bit
Mode
LOUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 99. Stereo Line Output Mode Select (LOUT)
PMRO bit
Mode
ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 100. Stereo Line Output Mode Select (ROUT)
(default)
(default)
LVL2-0 bits
Attenuation
7H
N/A
6H
N/A
5H
+6dB
4H
+3dB
3H
0dB
(default)
2H
−3dB
1H
−6dB
0H
−9dB
Table 101. Stereo Line Output Volume Setting (N/A: Not available)
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LOUT
ROUT
1μF
220Ω
20kΩ
Figure 78. External Circuit for Stereo Line Output (in case of using Pop Noise Reduction Circuit)
<Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2 )
(5 )
P M L O b it
P M R O b it
(1)
(3 )
(4 )
(6 )
L O P S bi t
L O U T p in
R O U T p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 79. Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(2) Set PMLO=PMRO bits = “1”. Stereo line output exits power-down mode.
LOUT and ROUT pins rise up to common voltage (typ. 0.8 x AVDD). Rise time is 200ms (max 300ms) at
C=1μF and AVDD=1.8V.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO=PMRO bits = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=1.8V.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits power-save mode.
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■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins in full-differential as (L+R) signal.
The load impedance is 10kΩ (min) for each LOP pin and LON pin. When the PMLO = PMRO bits = “0”, the mono line
output enters power-down mode and the output is pulled-down to VSS1. When the PMLO = PMRO bits = “1” and LOPS
bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO and
PMRO bits when LOPS bit = “1”. When PMLO = PMRO bits = “1” and LOPS bit = “0”, mono line output enters in
normal operation. LVL2-0 bits set the volume of mono line output.
LVL2-0 bits
DACL bit
DAC Lch
LOP pin
DACR bit
M
I
X
LON pin
DAC Rch
Figure 80. Full-differential Mono Line Output
LVL2-0 bits
Attenuation
7H
N/A
6H
N/A
5H
+12dB
4H
+9dB
3H
+6dB
(default)
2H
+3dB
1H
0dB
0H
−3dB
Table 102. Mono Line Output Gain Setting (N/A: Not available)
LOPS bit
0
1
PMLO/RO bits
Mode
LON/LOP pins
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 103. Mono Line Output Mode Setting
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(default)
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[AK4679]
<Full-differential Mono Line Output Control Sequence (in case of using Pop Noise Reduction
Circuit)>
(2 )
(5 )
P M L O b it
P M R O b it
(1)
(3 )
(4 )
(6 )
L O P S bi t
L O P , L O N p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 81. Mono Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. Mono line output enters power-save mode.
(2) Set PMLO = PMRO bits = “1”. Mono line output exits power-down mode.
LOP and LON pins rise up to common voltage (typ. 0.8 x AVDD). Rise time is 200ms (max 300ms) at
C=1μF and AVDD=1.8V.
(3) Set LOPS3 bit = “0” after LOP and LON pins rise up. Mono line output exits power-save mode.
Mono line output is enabled.
(4) Set LOPS bit = “1”. Mono line output enters power-save mode.
(5) Set PMLO = PMRO bits = “0”. Mono line output enters power-down mode.
LOP and LON pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=1.8V.
(6) Set LOPS bit = “0” after LOP and LON pins fall down. Mono line output exits power-save mode.
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■ Receiver-Amp (RCP/RCN pins)
Lch/Rch signal of DAC is output from the RCP/RCN pins which is BTL as (L+R) signal. The load impedance is 32Ω
(min). When the PMRCV bit = “0”, the mono receiver output enters power-down mode and the output is Hi-Z. When the
PMRCV bit = “1” and RCVPS bit = “1”, mono receiver output enters power-save mode. Pop noise at power-up/down can
be reduced by changing PMRCV bit when RCVPS bit = “1”. When PMRCV bit = “1” and RCVPS bit = “0”, mono
receiver output enters in normal operation. RCVG3-0 bits control the volume of mono receiver output.
RCVG3-0 bits
DACRL bit
RCP pin
DAC Lch
DACRR bit
M
I
X
DAC Rch
RCN pin
Figure 82. Mono Receiver Output
RCVG3-0 bits
Attenuation
FH
+12dB
EH
+9dB
DH
+6dB
CH
+3dB
BH
0dB
(default)
AH
−3dB
9H
−6dB
8H
−9dB
7H
−12dB
6H
−15dB
5H
−18dB
4H
−21dB
3H
−24dB
2H
−27dB
1H
−30dB
0H
MUTE
Table 104. Mono Receiver Output Volume Setting
PMRCV bit
0
1
RCVPS bit
x
Mode
Power-down
RCP pin
Hi-Z
RCN pin
Hi-Z
(default)
Common Voltage
1
Power-save
Hi-Z
(typ. 0.8 x AVDD)
0
Normal Operation
Normal Operation Normal Operation
Table 105. Receiver-Amp Mode Setting (x: Don’t care)
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[AK4679]
PMRCV bit
RCVPS bit
RCP pin
RCN pin
Hi-Z
Hi-Z
Common
Voltage
Common
Voltage
Hi-Z
Hi-Z
>1ms
>0
Figure 83. Power-up/Power-down Timing for Receiver-Amp
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[AK4679]
■ Headphone Output (HPL/HPR pins)
The headphone amplifiers are operated by positive and negative power supplied from charge pump circuit. The VEE pin
outputs the negative voltage generated by the internal charge pump circuit from PVDD. This charge pump circuit is
switched between VDD mode and 1/2VDD mode by the output level of the headphone amplifiers.
The headphone amplifier output is single-ended and centered on 0V (VSS1). Therefore, the capacitor for AC-coupling
can be removed. The minimum load resistance is 16Ω. The output power is 20mW (@ 0dBFS, RL = 16Ω, AVDD=1.8V,
HPG = -4dB) and 25mW (@ 0dBFS, RL =32Ω, AVDD=1.8V, HPG=0dB).
The output level of headphone-amp can be controlled by HPG5-0 bits. This volume setting is in common for L/R channels
and can attenuate/gain the mixer output from +6dB to –62dB in 2dB steps (Table 106). The HPG value is changed
independently on L/R channels by zero crossing or timeout. Zero crossing timeout period is set by HPTM1-0 bits. When
LOHM bit = “1”, the headphone-amp output to HPL and HPR pins as (L+R) mono signal.
HPG5-0 bits
DAC Lch
LOMH bit
M
I
X
HPL pin
M
I
X
HPR pin
LOMH bit
DAC Rch
Figure 84. Stereo Headphone Output
HPG5-0 bits
GAIN (dB)
HPG5-0 bits
GAIN (dB)
29H
N/A
14H
−30
28H
N/A
13H
−32
27H
N/A
12H
−34
26H
+6
11H
−36
25H
+4
10H
−38
24H
+2
0FH
−40
0EH
23H
0
−42
22H
0DH
−2
−44
21H
0CH
−4
−46
20H
0BH
−6
−48
1FH
0AH
−8
−50
1EH
09H
−10
−52
1DH
08H
−12
−54
1CH
07H
−14
−56
1BH
06H
−16
−58
1AH
05H
−18
−60
19H
04H
−20
−62
18H
03H
MUTE
−22
17H
02H
MUTE
−24
16H
01H
MUTE
−26
15H
00H
MUTE
−28
Table 106. Headphone-Amp Volume Setting (Default: 0dB, N/A: Not available)
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Zero Crossing Timeout Period
HPTM0
bit
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
Table 107. Headphone-Amp Volume Zero Crossing Timeout Period
HPTM1
bit
0
0
1
1
CPMODE1 bit
0
0
1
1
VDDTM2
bit
0
0
0
0
1
1
1
1
(default)
CPMODE0 bit
Mode
Operation Voltage
0
Class-G Operation Mode
Automatic Switching
1
± VDD Operation Mode
± VDD
0
±1/2 VDD Operation Mode
±1/2 VDD
1
N/A
Table 108. Charge Pump Mode Setting (N/A: Not available)
VDD Mode Holding Period
VDDTM1 VDDTM0
bit
bit
8kHz
16kHz
44.1kHz
0
0
1024/fs
128ms
64ms
23.2ms
0
1
2048/fs
256ms
128ms
46.4ms
1
0
4096/fs
512ms
256ms
92.9ms
1
1
8192/fs
1024ms
512ms
186ms
0
0
16384/fs
2048ms
1024ms
372ms
0
1
32768/fs
4096ms
2048ms
743ms
1
0
65536/fs
8192ms
4096ms
1486ms
1
1
N/A
Table 109. VDD Mode Waiting Period (N/A: Not available)
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(default)
(default)
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[AK4679]
<HP-Amp External Circuit>
It is necessary to put an oscillation prevention circuit (0.22μF±20% capacitor and 15Ω±20% resistor) because it has the
possibility that Headphone-Amp oscillates.
HP-Amp
AK4679
Headphone
0.22μF
16Ω
15Ω
Figure 85. HP-Amp oscillation prevention circuit example
When PMHPL or PMHPR bit = “1”, headphone outputs are in normal operation after the charge pump circuit is powered
up. When PMHPL and PMHPR bits = “0”, the headphone-amps and the charge pump circuit are powered-down
completely. At that time, the HPL and HPR pins go to VSS1 voltage via the internal pulled-down resistor. The
pulled-down resistor is 120Ω (typ).
The power-up time of HP-Amp block is 28ms and then HPL and HPR pins output 0V (VSS1). The power-down is
executed immediately.
PMVCM
bit
x
1
PMHPL/R
Mode
HPL/R pins
bits
0
Power-down & Mute
Pull-down by 120Ω (typ)
1
Normal Operation
Normal Operation
Table 110. Headphone-Amp Mode Setting (x: Don’t’ care)
MS1402-E-06
(default)
2013/02
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[AK4679]
■ Speaker Output (SPP/SPN pins)
Lch/Rch signal of DAC is converted by PWM and is output from SPP/SPN pins by BTL. When Lch/Rch signal of DAC
is 0dBFS, the speaker amplifier outputs 0.89W ( @ 8Ω, AVDD=1.8V, SVDD=4.2V, SPKG=-6dB). The load impedance
is 8Ω (min). A 2.2nF capacitor should be connected between SPFIL pin and VSS1 pin to reduce out-of-band noise from
DAC. SPKG3-0 bits control the volume of SPP/SPN.
SPKG3-0 bits
DACSL bit
DAC Lch
SPP pin
DACSR bit
M
I
X
SPN pin
DAC Rch
Figure 86. Mono Speaker Output
SPKG3-0 bits
Attenuation
FH
+12dB
EH
+9dB
DH
+6dB
CH
+3dB
BH
0dB
(default)
AH
−3dB
9H
−6dB
8H
−9dB
7H
−12dB
6H
−15dB
5H
−18dB
4H
−21dB
3H
−24dB
2H
−27dB
1H
−30dB
0H
MUTE
Table 111. Speaker Output Volume Setting
PMSPK bit
Speaker-Amp
0
Power-down & Hi-Z
1
Power-up & Output
Table 112. Speaker-Amp output state
(default)
When PMSPK bit is “1”, the speaker-amp is powered-up. The power-up time of SPK-Amp block is 32ms and then SPP
and SPN pins output 0V (VSS3). When PMSPK bit is “0”, the SPK-Amp block can be powered-down. The clock
supplied to SPK-Amp block must not be stopped for more than 0.5ms. Once SPK-Amp block is powered-down, the
SPK-Amp block should be powered-up again with an interval of 0.5ms or more.
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[AK4679]
■ Thermal Shutdown Function
When PMVCM bit is “1” and the internal device temperature rises up irregularly (E.g. Output pins of speaker amplifier
are shortened.), all amplifier blocks are automatically powered-down (PMLO, PMRO, PMRCV, PMHPL, PMHPR and
PMSPK bits = “0”) and then THDET bit becomes “1”. The other control registers are not initialized. When the internal
device temperature falls down, THDET bit becomes “0”, but the amplifier blocks do not return to normal operation unless
the amplifier blocks are powered-up (PMLO, PMRO, PMRCV, PMHPL, PMHPR or PMSPK bits = “1”). The device
status can be monitored by THDET bit.
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[AK4679]
■ System Clock (PCM I/F)
The AK4679 has two PCM I/F ports. PCM I/F A is for baseband module and PCM I/F B is for Bluetooth mode. PCM I/F
A, PCM I/F B and Audio I/F can be operated by asynchronous clock because the AK4679 has four SRCs. PCM I/F A and
PCM I/F B support slave mode only. The required clock PCM I/F is BICKA (BICKB) and SYNCA (SYNCB).When
PMPCMA bit is “1”, PCM I/F A port is powered-up. When PMPCMB bit is “1”, PCM I/F B port is powered-up.
CODEC
DSP
1fs2
Baseband
SYNC2
SYNC1
SYNC
BCLK2
BCLK1
BICK
SDTOA
SDIN2
SDOUT1
SDTI
SDTIA
SDOUT2
SDOUT2
SDTO
SYNCA
BICKA
≥ 16fs2
Bluetooth Module
SYNCB
BICKB
1fs3
SYNC
16fs3 or ≥ 32fs3
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 87. PCM I/F A and B
■ SRC (Sample Rate Converter)
The AK4679 has four asynchronous SRCs. The SRCs are operated by internal oscillator. When PMSRAI, PMSRAO,
PMSRBI or PMSRBO bit is “1” and PMOSC bit is “1”, SRC starts operation. Initial time of SRC is 164/fs2(164/fs3) for
SDTOA(SDTOB) output enable after power-down state is released by a clock input(SYNC clock). Until then, SDTOA
and SDTOB output data as shown in Table 113. Ratio of Input / Output is decided by PMMIX bit.
PMSRx bit = “1”
After PMSRx bit = “0” → “1”
During initial time
& Before SYNCA/SYNCB Input
16bit Linear
L
L
0000H
8bit A-Law
L
H
11010101b
L
H
11111111b
8bit μ-Law
Table 113. SDTOA and SDTOB pins Output Data (PMSRx: PMSRAI, PMSRAO, PMSRBI, PMSRBO)
Mode
PMSRx bit = “0”
PMMIX
bit
0
1
Input Sampling Rate
Output Sampling Rate
(FSI)
(FSO)
SRCAI
SYNCA
SYNCB
SRCAO
SYNCB
SYNCA
SRCAI
SYNCA
LRCK
SRCAO
LRCK
SYNCA
SRCBI
SYNCB
LRCK
SRCBO
LRCK
SYNCB
Table 114. PCM I/F Input Output rate
SRC
MS1402-E-06
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[AK4679]
■ PCM I/F A & B Format
AK4679 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and 8bit
μ-Law) independently (Table 115 and Table 116).
LAWA1
LAWA0
Format
bit
bit
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 115. PCM I/F A Mode (N/A: Not available)
Mode
0
1
2
3
Mode
0
1
2
3
LAWB1 bit LAWB0 bit
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 116. PCM I/F B Mode (N/A: Not available)
(default)
(default)
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (Table
117 and Table 118). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and μ-Law
Mode, the serial data is MSB first. PCM I/F formats support slave mode only. SYNCA/B and BICKA/B are input to the
AK4679.
Mode
0
1
2
3
Mode
0
1
2
3
FMTA1 bit
0
0
1
1
FMTB1 bit
0
0
1
1
FMTA0 bit
Format
BICKA
0
Short Frame Sync
≥ 16fs2
1
Long Frame Sync
≥ 16fs2
0
MSB justified
≥ 32fs2
1
I2S
≥ 32fs2
Table 117. PCM I/F A Format
FMTB0 bit
0
1
0
1
Format
BICKB
Short Frame Sync
16fs3 or ≥ 32fs3
Long Frame Sync
16fs3 or ≥ 32fs3
MSB justified
≥ 32fs3
I2S
≥ 32fs3
Table 118. PCM I/F B Format
Figure
Table 119
Table 121
Figure 104
Figure 106
(default)
Figure
Table 120
Table 122
Figure 105
Figure 107
(default)
In modes 2 and 3, the SDTOA/B is clocked out on the falling edge (“↓”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“↑”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits, and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“↑”) of BICKA and the SDTIA is latched on the
falling edge (“↓”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“↓”) of BICKA and the
SDTIA is latched on the rising edge (“↑”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“↑”) of BICKB and the SDTIB is latched on the
falling edge (“↓”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“↓”) of BICKB and the
SDTIB is latched on the rising edge (“↑”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
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[AK4679]
MSBSA bit
BCKPA bit
0
0
0
1
1
0
1
1
MSBSB
bit
BCKPB
bit
0
0
0
1
1
0
1
1
MSBSA
bit
BCKPA
bit
0
0
0
1
1
0
1
1
Data Interface Format
MSB of SDTOA is output by next rising edge (“↑”) of the falling edge (“↓”) of
BICKA after the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by the
falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by next falling edge (“↓”) of the rising edge (“↑”) of
BICKA after the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by the
rising edge (“↑”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the 2nd rising edge (“↑”) of BICKA after the rising
edge (“↑”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the
BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the 2nd falling edge (“↓”) of BICKA after the rising
edge (“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the
BICKA just after the output timing of SDTOA’s MSB.
Table 119. PCM I/F A Format in Mode 0
Data Interface Format
MSB of SDTOB is output by next rising edge (“↑”) of the falling edge (“↓”) of BICKB
after the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”)
of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by next falling edge (“↓”) of the rising edge (“↑”) of BICKB
after the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”)
of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the 2nd rising edge (“↑”) of BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB just
after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the 2nd falling edge (“↓”) of BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB just
after the output timing of SDTOB’s MSB.
Table 120. PCM I/F B Format in Mode 0
Data Interface Format
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by
the falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by
the rising edge (“↑”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of the first BICKA after the rising edge
(“↑”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA just
after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the falling edge (“↓”) of the first BICKA after the rising edge
(“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the BICKA just
after the output timing of SDTOA’s MSB.
Table 121. PCM I/F A Format in Mode 1
MS1402-E-06
Figure
Figure 88
Figure 89
Figure 90
Figure 91
Figure
Figure 96
Figure 97
Figure 98
Figure 99
Figure
Figure 92
Figure 93
Figure 94
Figure 95
2013/02
- 123 -
[AK4679]
MSBSB
bit
BCKPB
bit
0
0
0
1
1
0
1
1
Data Interface Format
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched
by the falling edge (“↓”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched
by the rising edge (“↑”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of the first BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB just
after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the falling edge (“↓”) of the first BICKB after the rising
edge (“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB
just after the output timing of SDTOB’s MSB.
Table 122. PCM I/F B Format in Mode 1
MS1402-E-06
Figure
Figure 100
Figure 101
Figure 102
Figure 103
2013/02
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[AK4679]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D7
D6
Don’t Care D7
D6
Figure 88. Timing of Short Frame Sync (PCM I/F A: MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 89. Timing of Short Frame Sync (PCM I/F A: MSBSA bit = “0”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 90. Timing of Short Frame Sync (PCM I/F A: MSBSA bit = “1”, BCKPA bit = “0”)
MS1402-E-06
2013/02
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[AK4679]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
Don’t Care
D7
D6
D7
D6
Figure 91. Timing of Short Frame Sync (PCM I/F A: MSBSA bit = “1”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 92. Timing of Long Frame Sync (PCM I/F A: MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 93. Timing of Long Frame Sync (PCM I/F A: MSBSA bit = “0”, BCKPA bit = “1”)
MS1402-E-06
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[AK4679]
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 94. Timing of Long Frame Sync (PCM I/F A: MSBSA bit = “1”, BCKPA bit = “0”)
1/fs2
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 95. Timing of Long Frame Sync (PCM I/F A: MSBSA bit = “1”, BCKPA bit = “1”)
MS1402-E-06
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[AK4679]
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L2
SDTIB
L1
L0 L15 L14 L13 L12 L11 L10
L9 L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14
R1
R0
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L15 L14 L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
D on’t Care
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L7
L6 L6
L0
R7
L7
L6 D5
L0
R7 D2
L15 L14
Don’t Care
L15 L14
Don’t Care
L7
L6
L7
L6
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 96. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L2
SDTIB
L1
L0 L15 L14 L13 L12 L11 L10
L9 L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14
R1
R0
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L15 L14 L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
D on’t Care
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L7
L6 L6
L0
R7
L7
L6 D5
L0
R7 D2
Don’t Care
L15 L14
Don’t Care
L15 L14
L7
L6
L7
L6
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 97. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “1”)
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1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
SDTIB
L2
L1
L0 L15 L14 L13 L12 L11 L10
L9 L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14
R1
R0
R7
R6
R5
R4
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2
L7
L6
L5
L4
L3
L2
L1
L0
L15 L14
L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L15 L14
L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L7
L6
L6
L0
R7
L7
L6
D5
L0
R7 D2
L15 L14
Don’t Care
L15 L14
Don’t Care
L7
L6
L7
L6
<16bit Linear>
Lch D ata: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 98. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “1”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
SDTIB
L2
L1
L0 L15 L14 L13 L12 L11 L10
L9 L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14
R1
R0
R7
R6
R5
R4
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R2
L7
L6
L5
L4
L3
L2
L1
L0
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L15 L14
L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L7
L6
L6
L0
R7
L7
L6
D5
L0
R7 D2
Don’t Care
L15 L14
Don’t Care
L15 L14
L7
L6
L7
L6
<16bit Linear>
Lch D ata: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 99. Timing of Short Frame Sync (PCM I/F B: MSBSB bit = “1”, BCKPB bit = “1”)
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1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L1
SDTIB
L0 L15 L14 L13 L12 L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14 L13
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
L5
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care L15 L14
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L13
L7
L6 L6
L0
R7
L7
L6 D5
L0
R7 D2
L15 L14 L13
Don’t Care
L15 L14 L13
D on’t Care
L7
L6
L5
L7
L6
L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 100. Timing of Long Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L1
SDTIB
L0 L15 L14 L13 L12 L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14 L13
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L8
L7
L1
L1
L0 R15 D6
R1
R0
R1
R1
R0
R1
R0
L7
L6
L5
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care L15 L14
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L13
L7
L6 L6
L0
R7
L7
L6 D5
L0
R7 D2
D on’t Care
L15 L14 L13
Don’t Care
L15 L14 L13
L7
L6
L5
L7
L6
L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 101. Timing of Long Frame Sync (PCM I/F B: MSBSB bit = “0”, BCKPB bit = “1”)
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1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L1
SDTIB
L0 L15 L14 L13 L12 L11 L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14 L13
R0
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R1
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L14 L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
L7
L6 L6
L0
R7
R1
R1
R0
L7
L6 D5
L0
R7 D2
R1
R0
L7
L6
L5
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care L15
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
L15 L14 L13
Don’t Care
L15 L14 L13
D on’t Care
L7
L6
L5
L7
L6
L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 102. Timing of Long Frame Sync (PCM I/F B MSBSB bit = “1”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16fs3)
(16bit Linear)
SDTOB
L1
SDTIB
L0 L15 L14 L13 L12 L11 L10
L9 L8
L7
L6
L5
L4
L3
L2
L1
D0
L0 L15 L14 L13
L0
R7
R3
R2
R1
D0
R0
(8bit A-Law/μ-Law)
SDTOB
SDTIB
R1
L7
L6
L5
L4
L3
L2
L1
L0
R6
R5
R4
L15 L14 L13
L8
L7
L1
L1
L0 R15 R13
R1
R0
L14 L13
L8
L7
L1
L1
L0 R15 D6
R1
R0
L7
L6 L6
L0
R7
R1
R1
R0
L7
L6 D5
L0
R7 D2
R1
R0
L7
L6
L5
BICKB
(64fs3)
(16bit Linear)
SDTOB
SDTIB
Don’t Care L15
(8bit A-Law/μ-Law)
SDTOB
SDTIB
Don’t Care
D on’t Care
L15 L14 L13
Don’t Care
L15 L14 L13
L7
L6
L5
L7
L6
L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 103. Timing of Long Frame Sync (PCM I/F B: MSBSB bit = “1”, BCKPB bit = “1”)
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SYNCA
BICKA
(32fs2)
SDTOA(o)
SDTIA(i)
BICKA
(64fs2)
0 1
2 3
9 10 11 12 13 14 15 0
15 14 13
7 6
5 4 3 2
1 0
15 14 13
7 6
5 4 3 2
1 0
0 1
2 3
15 16 17 18
SDTOA(o)
15 14 13
1 0
SDTIA(i)
15 14 13
1 0
1 2 3
9 10 11 12 13 14 15 0 1
15
Don't Care
31 0
1 2 3
15
Don't Care
15 16 17 18
31 0 1
15
Don't Care
Don't Care
15
15:MSB, 0:LSB
Figure 104. Timing of MSB justified (PCM I/F A)
SYNCB
BICKB
(32fs3)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
SDTOB(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTIB(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
BICKB
(64fs3)
0 1 2 3
15 16 17 18
SDTOB(o)
15 14 13
1 0
SDTIB(i)
15 14 13
1 0
31 0 1 2 3
Don't Care
15 16 17 18
15 14 13
1 0
15 14 13
1 0
31 0 1
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 105. Timing of MSB justified (PCM I/F B)
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SYNCA
BICKA
(32fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
SDTOA(o)
15 14
8 7 6 5 4 3 2 1 0
SDTIA(i)
15 14
8 7 6 5 4 3 2 1 0
BICKA
(64fs2)
0 1 2 3
15 16 17 18
SDTOA(o)
15 14
2 1 0
SDTIA(i)
15 14
2 1 0
9 10 11 12 13 14 15 0 1
Don't Care
31 0 1 2 3
15 16 17 18
Don't Care
31 0 1
Don't Care
15:MSB, 0:LSB
Figure 106. Timing of I2S (PCM I/F A)
SYNCB
BICKB
(32fs3)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
SDTOB(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTIB(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
BICKB
(64fs3)
0 1 2 3
15 16 17 18
SDTOB(o)
15 14
2 1 0
SDTIB(i)
15 14
2 1 0
31 0 1 2 3
Don't Care
15 16 17 18
15 14
2 1 0
15 14
2 1 0
31 0 1
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 107. Timing of I2S (PCM I/F B)
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[AK4679]
■ DSP Block Sampling Frequency Setting
Select sampling frequency (FSD[3:0] bits) on the sleep mode. In FSD mode 6, the Up-Down sampling converter is
powered-up and the AK4679 enters double sampling mode (fs1 =8kHz, fs2 =16kHz). In the other modes (using unity
sampling rate), fs2 is output at the same timing of fs1 input.
FSD
Mode
0
6
1
2
3
5
7
10
11
15
Sampling Frequency
fs1 Port1
fs2 Port2
fs3 Port3
0
0
0
8kHz
8kHz
8kHz
1
1
0
8kHz
16kHz
8kHz
0
0
1
12kHz
12kHz
12kHz
0
1
0
16kHz
16kHz
16kHz
0
1
1
24kHz
24kHz
24kHz
1
0
1
11.025kHz
11.025kHz
11.025kHz
1
1
1
22.05kHz
22.05kHz
22.05kHz
0
1
0
32kHz
32kHz
32kHz
0
1
1
48kHz
48kHz
48kHz
1
1
1
44.1kHz
44.1kHz
44.1kHz
N/A
N/A
Table 123. Setting of Sampling Frequency (N/A: Not available)
FSD3 bit FSD2 bit FSD1 bit FSD0 bit
0
0
0
0
0
0
0
1
1
1
Others
(default)
Double FS mode
■ Selection of Input Port
The selection of the signal path of the input clock for Port#1 and #3 is set by the SELPT bit. SYNC2 clock is selected by
FSD bits and processed on the clock generator (CGU) block. The frequency of SYNC2 is double as that of SYNC1 on the
FSD mode 6 while the BCLK2 bit clock rate is same as BCLK1. When PT2N bit = “1”, BCLK2 and SYNC2 pin outputs
are low level. When BCLK1 and SYNC1 pins are selected as input pins, BCLK3/JX0 and SYNC3/JX1 pins could act as
JX0 and JX1 pins function respectively.
Port#1,#3
Port#2
BCLK1 pin
BCLK2 pin
BCLK3/JX0 pin
SELPT bit
SYNC1 pin
SYNC3/JX1 pin
FSD[3:0] bit
PT2N bit
SYNC2 pin
CGU
CGU: Clock Generator Unit
Figure 108. Port#1/2/3 Signal Setting (PT2N bit = “0”)
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[AK4679]
■ Output Selector of Port#1, Port#2 and Port#3
The AK4679 has output selectors. After releasing hardware suspend, LPDO1/2 bits control signal path of SDOUT1/2
respectively. On both hardware reset and suspend states, Port#1 input/output are bypassed to Port#2 output/input
respectively. The output pin selection of the Por#3 is done by LPDO3 and 4 bits. Each output pin has an output enable
switch. (OUTxN bit x = 1, 2, 3, 4)
FS[3:0] bits
PCM I/F Port #2
SDIN2
LPDO2 bit
1
0
SDOUT2
SYNC2
0
1
SYNC1
SYNC3
AKM
DSP
Core
PT2N bit SELPT bit
BCLK2
0
1
Up-down DIN2
Sample
converter
(8k←→16k DOUT2
BCLK1
BCLK3
PCM I/F Port #1
SYNC1
BCLK1
DIN1
SDIN1
LPDO1 bit
SDOUT1
0
1
DOUT1
PCM I/F Port #3
DIN3
SDIN3
LPDO3 bit
SDOUT3
1
0
DOUT3
DIN4
SDIN4
LPDO4 bit
SDOUT4
0
1
DOUT4
SYNC3
BCLK3
Figure 109. Output Selector of Port#1, Port#2 and Port#3 (Red: hardware reset)
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[AK4679]
■ PCM Audio Interface Format
LAW [1:0] and DIFD [1:0] bits select interface format of Port#1, Port#2 and Port#3. The interface format is in common
for all ports. BCLK1/2 frequency ranges from 16fsl to 256fsl. In all modes, the data format is MSB first, 2’s complement
and supporting 2channel data only. The data length supports 16/24bit Linear, 8bit μ-Law, and 8bit A-Law (Table 125).
On the PCM short/long frame, the AK4679 only accepts 1channel data when BICK1/2 is 16fs and in/output data length is
16bit Linear. The AK4679 can support 16bit PCM (short frame, long frame), Left justified and I2S mode (Table 126).
When the data format of Port#1 and Port#2 is 8bit A-Law or 8bitμ-Law, the data format of Port#3 will be 16bit Linear.
BCLK1 and BCLK3 input frequency to the Port#1, 3 are dependent on DIFD mode as shown below.
fBCLK1, fBCLK3 frequency range
Remark
4 x DataLength(8,16,24) x fs ~ 256 x fs
FSD mode 6
Others
2 x DataLength (8,16,24) x fs ~ 256 x fs
(Except FSD mode 6)
Table 124. BCLK Setting
Digital I/F Format
Port#1, Port#2
Port#3
16-bit Linear
16-bit Linear
24-bit Linear
24-bit Linear
8-bit A-Law
16-bit Linear
8-bit μ-Law
16-bit Linear
Table 125. PCM Data Format Setting
Mode
LAW [1:0]bits
0
1
2
3
00
01
10
11
(default)
DIFD Mode
0
1
2
3
DIFD[1:0]bits
Digital I/F Format
BCLK1
00
PCM Short Frame
≥ 16fs1
01
PCM Long Frame
≥ 16fs1
10
Left justified
≥ 32fs1
11
I2S
≥ 32fs1
Table 126. PCM Interface Format Setting
In format mode 1/2, PCM data format is selected by BCKPD bi
(default)
When PCM short/long frame interface format is selected, the data format is determined by the BCKPD bit (Table 127).
SDOUT output data and SDIN input data are latched and output on the falling or rising edge of BCLK. Rising/Falling
edge select is valid on any digital interface format. Set BCKP1 bit = “0” (falling edge) for Left justified and I2S formats.
Refer to: Figure 110-Figure 113 for selectable format of BCLK against SYNC1/2 edge.
BCKPD bit
BCLK edge referenced
to SYNC edge
Figure 110 (default)
Figure 112
Figure 111
1
Rising (RE)
Figure 113
Table 127. PCM Interface format in (DIFD[1:0] = “00”, “01”)
0
Falling (FE)
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[AK4679]
SYNC1, 2, 3
BCLK1, 2, 3
1st channel
(16bit Linear)
SDOUTx
D15 D14 D13 D12 D11
D2 D1
2nd channel
D0
D15 D14 D13 D4
D3
1st channel
SDINx
Don’t Care D15 D14 D13
(8bit A-Law/μ-Law)
D2 D1
1st channel
SDOUTx
D0
D7
D0
D15 D14
D0
D15 D14 D13 D4
D3
D2
D1
D0
Don’t Care D15 D14
D0
D7
D0
1st channel
Don’t Care D7
D1
2nd channel
2nd channel
D7
SDINx
D2
D6
D5
D2
D1
2nd channel
D0
Don’t Care
D7
D6
D7
D6
(x =1~4)
Figure 110. PCM Short Frame Falling-edge (LAW bits = “00”, DIFD bits = “00”, BCKPD bit = “0”)
SYNC1, 2, 3
BCLK1, 2, 3
1st channel
(16bit Linear)
SDOUTx
2nd channel
D15 D14 D13 D12
D3
D2 D1
D0
1st channel
SDINx
Don’t Care
(8bit A-Law/μ-Law)
D7
D6
Don’t Care
D7
D6
D2
D1
D0
D15 D14
D3
D2 D1
D0
D15 D14 D13 D4
D3
D2
D1
D0
Don’t Care D15 D14
2nd channel
D5
D0
D5
D0
1st channel
SDINx
D3
2nd channel
D15 D14 D13 D12
1st channel
SDOUTx
D15 D14 D13 D4
D7
D2
D1
D0
D7
D6
D7
D6
2nd channel
D7
D2
D1
D0
Don’t Care
(x =1~4)
Figure 111. PCM Short Frame Rising-edge (LAW bit = “00”, DIFD bits = “00”, BCKPD bit = “1”)
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[AK4679]
ts
tSYNCH(tBICK ≤ tSYNCH ≤ ts-tBICK)
SYNC1, 2, 3
BCK1, 2, 3
(16bit Linear)
1st channel
SDOUTx
D15 D14 D13 D12 D11 D2
SDINx
2nd channel
Don’t Care D15 D14 D13
D0
D15 D14 D13 D12 D11 D2
D1
D0
D15 D14 D13
D1
D0
D15 D14 D13
D1
D0
Don’t Care D15 D14 D13
D2
2nd channel
D7
D6
D5
D0
D7
D6
D5
D0
Don’t Care D7
D6
D5
D0
D7
D6
D5
D0
SDOUTx
SDINx
D2
1st channel
(8bit A-Law/μ-Law)
D1
Don’t Care
D7
D6
D5
D7
D6
D5
(x =1~4)
Figure 112. PCM Long Frame Falling-edge (LAW bit = “00”, DIFD bits = “01”, BCKPD bit = “0”)
ts
tSYNCH(tBICK ≤ tSYNCH ≤ ts-tBICK)
SYNC1, 2, 3
BCLK1, 2, 3
(16bit Linear)
1st channel
SDOUTx
D15 D14 D13 D12 D11 D2
D1
D0
D15 D14 D13 D12 D11 D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D2
D1
D0
D15 D14 D13 D12 D11 D2
D1
D0
Don’t Care D15 D14 D13
SDINx
(8bit A-Law/μ-Law)
1st channel
2nd channel
D7
D6
D5
D0
D7
D6
D5
D0
Don’t Care D7
D6
D5
D0
D7
D6
D5
D0
SDOUTx
SDINx
2nd channel
Don’t Care
D7
D6
D5
D7
D6
D5
(x =1~4)
Figure 113. PCM Long Frame Rising-edge (LAW bit = “00”, DIFD bits = “01”, BCKPD bit = “1”)
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SYNC1, 2, 3
0
1
2
10
11
12
13
14
15
n-1 n
0
1
2
11
10
12
13
14
15
n-1 n
0
1
BCLK1, 2, 3
SDOUTx
15 14
5
4
3
2
1
0
15 14
5
4
3
2
1
0
SDINx
15 14
5
4
3
2
1
0
Don’t Care 15 14
5
4
3
2
1
0 Don’t Care 15
15: MSB, 0: LSB
(x = 1 to 4)
Lch Data
15
Rch Data
Figure 114. Left Justified format (LAW bits = “00”, DIFD bits = “10”)
SYNC1, 2, 3
0
1
2
18
19
20
21
22
23
n-1
n
0
1
2
18
19
20
21
22
23
n-1
n
0
1
BCLK1, 2, 3
SDOUTx
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDINx
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care 23
23:MSB, 0:LSB
(x = 1 to 4)
Lch Data
23
Rch Data
Figure 115. Left Justified format (LAW bits = “01”, DIFD bits = “10”)
SYNC1, 2, 3
0
1
2
3
11
12
13
14
15
16
n
0
1
2
3
11
12
13
14
15
16
n
0
1
BCLK1, 2, 3
SDOUTx
15 14
5
4
3
2
1
0
15 14
5
4
3
2
1
0
SDINx
15 14
5
4
3
2
1
0
Don’t Care 15 14
5
4
3
2
1
0 Don’t Care
15:MSB, 0:LSB
Lch Data
(x=1 to 4)
Rch Data
Figure 116. I2S Format (LAW bits = “00”, DIFD bits = “11”)
SYNC1, 2, 3
0
1
2
3
19
20
21
22
23
24
n
0
1
2
3
19
20
21
22
23
24
n
0
1
BCLK1, 2, 3
SDOUTx
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDINx
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
(x=1 to 5)
Lch Data
Rch Data
Figure 117. I2S Format (LAW bits = “01”, DIFD bits = “11”)
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■ DSP STATE TRANSITION
The DSP blcok has follwing operating modes which are controlled by power supply, registors setting, program setting
and external clocks.
♦ Power Down (PDNE pin= “L”)
When the PDNE pin = “L” the DSP block is in powered-down state. Power supplies must be applied when the
PDNE pin = “L”. Set the PDNE pin to “H” to release the power-down after all power supplies are fed. More than
tPDNE cycle of “L” period is needed before releasing the power-down. The state moves the Hardware Reset
state by bringing the PDNE pin = “H”.
♦ Hardware Reset
The DSP is also in reset state in this mode. The clcocks and digital signals are bypassed to the output pins as
shown in Figure 109. The frame sync SYNC1 goes through SYNC2, and BCLK1 through BCLK2. The dital
signal path is shown in Figure 109. Do not apply a clock over 3.072MHz to the BCLK pin. In hardware reset
state, control registers (CONT0~8) cannot be accessed. The DSP block enters hardware suspended state when
the internal digital block is powered-up by setting the system power supply register (PCONT0: PWSW bit) to
“1”.
3
♦ Hardware Suspended
The power supply control block is initialized when the system power supply register (PCONT1: MRSTN bit) is
set to “1”. Control registers are reset and the DSP block goes into sleep state.
♦ Sleep (Standby)
In this state, all internal registers are in their default values. Register settings and DSP program downloading to
the RAM are available. TESTA, B, C bit, Digital I/F format and DSP related register settings should be made in
DSP reset state (DSPRSTN bit = “0”). CONT8 TESTC bit must be set to “1”. After these settings, set DLRDY
bit for the access pamission of internal memories to download DSP programs. The DLRDY bit must be cleared
after downloading DSP programs. Then, release the DSP reset (DSPRSTN bit = “1”). Clock inputs (BCLK1 or
3, SYNC1 or 3) are not necessary when writing to PRAM or CRAM.
♦ Wait Sync
After releasing DSP reset, DRAM and DLRAM data are cleared by “0” and the DSP block enters wait sync state.
In this state, the clock generator (CGU) is powered-up if an external clock is input to Port#1 or Port#3. Then the
DSP block enters normal operation mode after the output clock of CGU is stabilized. For a proper operation of
the system, a burst clock or a clock with two different frequencies locally are prohibited to use as BCLK or
SYNC. Uniform clocks must be input without a frequency deviation. In sleep mode, the CGU block does not
power up since an external clock cannot be received.
♦ DSP Operational (Run state)
The CGU block is powered-up when BCLK and SYNC clocks are detected in Wait Sync mode. The DSP block
becomes RUN state and CGU block starts to control clocks and DSP core.
The CGU block is unlocked when no input clocks are present during an operation and the DSP block enters
either Wait Sync state or Hardware Reset.
1. Wait Sync State
When the input clock at Port#1 or Port#3 is stopped for a certaion period (Figure 120), the DSP block
enters wait sync state. Registers, PRAM, CRAM and OFREG data are maintained. The CGU block is
in powere-down state until the clock is input again.
2. Hardware Reset State
When MRSTN bit = “0” and PWSW bit= “0”, the CGU block is powered-down and the internal
registers are initialized.The system power supply switch is turned off and PRAM, CRAM and
DLRAM are cleared. Regster values are also cleared to the default values. This mode is suitable for
standby in low power consumption. To resume the device operation, register settings and program
downloadings are necessary.
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Mode
Power Down
Hardware Reset
Hardware Suspended
Sleep/Standby
Wait Sync
CG Ctrl
Device Operating
State
PDNE
pin
L
H
H
H
H
H
PWSW
bit
0
0
1
1
1
1
MRSTN
bit
0
0
0
1
1
1
Setting
DLRDY
bit
0
0
0
0
0
0
DSPRSTN
bit
0
0
0
0
1
1
BCLKx,
SYNCx
None
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Input
CGU
State
DSP
RAM
PD
PD
PD
PD
PD
PU
PD
PD
PD
PD
PU
PU
H
1
1
0
1
Input
PU
PU
(PD: Power Down, PU: Power Up)
Table 128. Modes Definitions
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DSP Operational Transition Diagram
Apply Power
Power
off
Power
Down
Remove Power
PDNE pin
L
H
Hardware
Reset
PWSW bit
0
1
Hardware
Suspended
0
MRSTN bit
1
DLRDY bit
MRSTN bit ="0"
0
Sleep
(Standby)
Register
Setting
DSPRSTN bit = “1”
1
Download
Program
0
1
Wait Sync
Sync
SYDET bit
Detect
(Read only)
?
DSPRSTN bit = “0”
N
Y
CG
Ctrl
CGLK bit
(Read only)
Stop Sync
CG
Locked
?
N
Y
DSP
Operational
"Run state"
Figure 118. DSP Block State Diagram
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■ Power-up Sequence and Device Setting
• Power-up, register setting, program download and RUN state sequence
The DSP must be in sleep state when downloading the program. Set DLRDY bit to “1” to power-up the internal
oscillation circuit, and after 100μs downloading becomes available. DLRDY bit must always be cleared when complete a
download. Then DSPTRSTN bit is cleared, the DSP block enters wait sync mode. In this state, CGU block is locked when
serial data clock input is detected and the DSP block becomes operating state.
Power supply
0.6μs (min)
PDNE(pin)
1μs (min)
PWSW bit
MRSTN bit
μP I/F
Setting Register
Download DSP program
100 μs(min)
DLRDY bit
100 μs(min)
Glock Gen(int.)
DSPRSTN bit
BCLKx,SYNCx pin
Don’t care
(x= 1 or 3)
Device state Power OFF
Power Down
Sleep State
Input
Wait Sync
Device Operational State
Hardware Reset→Suspend
Figure 119. DSP Block Status
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■ DSP State Transition (operational state ↔ wait sync)
Standby Sequence by SYNC1 and SYNC3
When SYNC input is stopped, fixed to “L” or “H” for more than 0.8ms during RUN state, CGU block is powered-down
and the DSP block enters the wait sync mode.
>0.8ms
SYNC1 or SYNC3
“H” or “L”
CGU CTRL
Device state
Device Operational
CGU unlocked
Wait Sync
Figure 120. Standby Sequence Example by SYNC1/3
Resume Sequence by SYNC1 and SYNC3
In wait sync mode, CGU block will be powered up in 5ms after SYNC1/3 input. The DSP block resumes operation when
DSP reset is released internally and the RAM data is cleared.
< 5ms
SYNC1 or SYNC3
“H” or “L”
CLKGEN & Ctrl
Device state
Wait Sync
CGU locked
Device Operational
Figure 121. Resume Sequence by SYNC1/3
Refer to Figure 118 for the sequence when resuming the operation from hardware default state.
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■ RAM Clear
The DSP block has a RAM clear function. After the DSP reset release (during RUN), data RAM, delay RAM, coefficient
RAM and accelerator are cleared by “0” (RAM clear). The required time to clear RAM is about 400µs.
In the RAM clear sequence, it is possible to order command to DSP. (DSP is stopped during RAM clear sequence. The
ordered command is accepted automatically after this sequence is completed.)
SYNC1/3 pin
BCLK1/3 pin
Input
Wait Sync
Device state
CGU unlocked
RAM clear
CGU locked
Device Operational
RAM clear
DSP start
DSP Operational
Start working
Figure 122. RAM Clear Sequence
■ Status Output Pin
STRDY bit selects the output of the STO/RDY pin. When STRDY bit = “0”, the STO/RDY pin outputs STO. The
STO/RDY pin outputs “L” after the DSP block is powered-up during the PDN pin = “L”. When the DSP block exits
power-down mode, WDT (watch dog timer) error, CRC error and lock error of CGU block can be output by control
register settings. Each error OR’ed status is output by active-low output when these errors occur. WDT error detection
result output is enabled by DSP instruction setting.
PWSW
bit
0
MRSTN
bit
0
1
1
CRCE
bit
--
WDTN
bit
--
LOCKE
bit
--
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
1
0
1
1
STO pin
L
L
WDTERRN
Note
Needs DSP Instruction Setting
H
CRCERRN
WDTERRN
Needs DSP Instruction Setting
0
CRCERRN
1
WDTERRN
Needs DSP Instruction Setting
LOCKERRN
1
LOCKERRN
1
CRCERRN
WDTERRN
Needs DSP Instruction Setting
LOCKERRN
1
CRCERRN
LOCKERRN
Table 129. STO pin Configuration
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■ DSP Programmable Output
The DSP block has two General Purpose Output (GP0 and GP1) pins for external device controlling. The outputs can be
controlled by DSP programs. SELDO3 and SELDO4 bits control SDOUT3/GP0 and SDOUT4/GP1 pins respectively.
OUT3N and OUT4N bits switch output enable/disable of these. When controlling the GPCby the GP0 and GP1 pins, the
initial state of the GP0 and GP1 pins are “L”.
OUT3N bit
0
1
OUT4N bit
0
1
SELDO3 bit
Output Data Select
0
DSP DOUT3
1
DSP GP output 0
0
Low
1
Table 130. SDOUT3/GP0 pin Select
SELDO4 bit
Output Data Select
0
DSP DOUT4
1
DSP GP output 1
0
Low
1
Table 131. SDOUT4/GP1 pin Select
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Serial Control Interface (SPI, I2C-bus)
■ General
Audio Block is controlled by I2C bus only while DSP Block is controlled by the SPI or I2C bus which is set by I2CE pin
state.
■ Serial Control Interface (I2C-bus)
The AK4679 supports the fast-mode I2C-bus (max: 400 kHz). Pull-up resistors at SDAA and SCLA pins must be
connected to (TVDDA+0.3)V or less voltage. Pull-up resistors at SDAE and SCLE pins must be connected to
(TVDDE+0.3)V or less voltage.
SCLA and SCLE are denoted by SCL. SDAA and SDAE are denoted by SDA in this document.
(2)-1. WRITE Operations
Figure 123 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 131). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are shown in Figure 124 and Figure 125. If the slave address
matches that of the AK4679, the AK4679 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 133). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write
operation is to be executed.
The second byte consists of the control register address of the AK4679. When accesing the PRAM, CRAM and OFFREG
the second byte consists command code at this time. This address is 8bits and the format is MSB first (Figure 126). The
data after the second byte contains control data. The format is MSB first, 8bits (Figure 127). The AK4679 generates an
acknowledge after each byte is received. A data transfer is always terminated by a STOP condition generated by the
master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 131).
The AK4679 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4679
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 8-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address for CODEC registers
exceeds AFH prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 134) except for the START and STOP
conditions.
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SDAA
(SDAE)
S
T
A
R
T
S
T
O
P
R/W="0"
Slave
S Address
Sub *
Address(n)
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
0
0
1
0
0
1
A
C
K
A
C
K
Figure 123. Data Transfer Sequence at the I2C-Bus Mode
P
(*: Command code)
0
R/W
CAD0
R/W
Figure 124. The First Byte for Audio Block
0
0
1
1
0
CAD1
Figure 125. The First Byte for DSP Block
CAD1, CAD0 bits defined by the related pins.
A7
A6
A5
A4
A3
A2
A1
A0
D1
D0
Figure 126. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 127. Byte Structure after the second byte
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(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4679. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 8-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds AFH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out. The AK4679 supports two basic read operations:
CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4679 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4679 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4679
ceases transmission.
S
T
A
R
T
SDAA
SDAE
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
S K
T
E
R
MA
AC
S K
T
E
R
P
MN
AA
SC
T
EK
R
Figure 128. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4679 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4679 ceases transmission.
S
T
A
R
T
SDAA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub *
Address(n)
A
C
K
S
T
O
P
R/W="1"
A
C
K
Data(n)
Data(n+1)
MA
AC
S
T K
E
R
MA
AC
SK
T
E
R
A
C
K
Data(n+x)
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
(*: Command code)
Figure 129. RANDOM ADDRESS READ (Audio Block)
S
T
A
R
T
SDAE
R
E
S
T
A
R
T
R/W ="0"
Slave
S Address
Command
code
A
C
K
Slave
S Address
Data(n)
A
C
K
S
T
O
P
R/W ="1"
Data(n)
A
C
K
A
C
K
Data(n+1)
MA
A C
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
M
A
S
T
E
R
N
A
C
K
Figure 130. RANDOM ADDRESS READ (DSP Block)
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SDAA
SDAE
SCLA
SCLE
S
P
start condition
stop condition
Figure 131. START and STOP Conditions
When Start condition is received again instead of Stop condition, the bus changes to Repeated Start condition. Repeated
Start condition is functionally the same as Start condition.
SCLA
SCLE
SDAA
SDAE
START CONDITION
Repeated Start CONDITION
Figure 132. Repeated Start Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 133. Acknowledge on the I2C-Bus
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SDAA
SDAE
SCLA
SCLE
data line
stable;
data valid
change
of data
allowed
Figure 134. Bit Transfer on the I2C-Bus
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■ SPI Serial Control Interface (DSP block)
DSP block can be controlled by SPI.
1. Configuration
The access format is: Command code (8bit) + Address + Data (MSB First)
Bit Length
Rgister address 8
MSB bit is R/W flag. The following 7bits indicate access area such as PRAM/
or
CRAM/Registers.
Command code
Address to be
16 or 0
Valid only for those cases where accessed areas have addresses such as PRAM
accessed
/CRAM/OFREG. When no address is assigned, there is no data.
Data
later section
Write or Read data
Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
CSN
SCLK
don’tcare
(L /H)
SI
RegAddr,ComCode(8bit)
Address (16bit or 0bit)
SO Hi-Z
Low
Data (write)
X (L/H)
Data (read)
Hi-Z
Low
The output level of SO pin is set by SOCFG bit on CSN pin = “H”.
□ Echo back
The input data of the SI pin is echoed back to the SO pin by shifting 8bit to the right.
1-1. Write Sequence 1
CSN
SI
SO
COMMAND
HiZ
Low
ADDRESS1
COMMAND
ADDRESS2
ADDRESS1
DATA1
ADDRESS2
DATA2
don’tcare
(L/H)
DATA1
Hi-Z or Low
COMMAND
ADDRESS1
COMMAND
Figure 135. Echo-Back Writing 1
1-2 Write Sequence 2
CSN
SI
n= ~5
0xB4
SO HiZ
Low
0x00
COMMAND
0x00
ADDRESS1
DATA1
ADDRESS2
DATAn
DATA1
Extra 8bit data
DATAn
don’t care
(L/H)
Hi-Z or Low
It is possible to verify the written data by inputting extra 8bit clock. If the dummy data is more than the data length, this
dummy data is written on the next address. (24bit for CRAM writing and 16bit for OFREG writing)
Figure 136. Echo-Back Writing 2
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[AK4679]
2. Read Sequence
CSN
SI
COMMAND
SO HiZ
Low
ADDRESS1
COMMAND
ADDRESS2
ADDRESS1
don’t care
(L/H)
don’t care
(L/H)
don’t care
(L/H)
READ DATA
READ DATA
Hi-Z or Low
COMMAND
ADDRESS1
COMMAND
Data of the address2 field is not echoed back in read operation. The read data on the SO pin is output after writing to the
address2 field.
Figure 137. Echo-Back Mode Reading
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■ Register Map (Audio block)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
Register Name
Power Management 0
Power Management 1
Power Management 2
PLL Mode Select 0
PLL Mode Select 1
Audio I/F Format Select
MIC Signal Select
MIC Amp Gain
Digital MIC
DAC Signal Pass Select
LINEOUT Power Management
HP Power Management
Charge Pump Control
SPK&RCV Power Management
LINEOUT Volume Control
HP Volume Control
SPK & RCV Volume Control
Lch Input Volume Control
Rch Input Volume Control
ALC Reference Select
Digital Mixing Control
ALC Timer Select
ALC Mode Control
Mode Control 0
Mode Control 1
Digital Filter Select 0
Digital Filter Select 1
Digital Filter Select 2
Side Tone Volume A Control
Lch Output Volume Control
Rch Output Volume Control
PCM I/F Power Management
PCM I/F Control 0
PCM I/F Control 1
Side Tone Volume B Control
Digital Volume B Control
Digital Volume C Control
Digital Mixing Control 0
Digital Mixing Control 1
Digital Mixing Control 2
Digital Mixing Control 3
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
D7
0
0
ADRST
FS3
CM1
0
0
MGNR3
0
DACSR
0
HPTM1
D6
0
0
0
FS2
CM0
0
MDIF3
MGNR2
0
DACSL
0
HPTM0
D5
PMADR
0
0
FS1
BCKO
0
MDIF2
MGNR1
PMDMR
DACRR
0
0
D4
PMADL
0
0
FS0
0
SDOD
MDIF1
MGNR0
PMDML
DACRL
LODIF
0
0
VDDTM2
VDDTM1
VDDTM0
THDET
0
0
RCVG3
IVL7
IVR7
REF7
0
0
0
RCVG2
IVL6
IVR6
REF6
TEST
0
HPG5
RCVG1
IVL5
IVR5
REF5
PMSPK
0
HPG4
RCVG0
IVL4
IVR4
REF4
D3
0
PMDAR
MICL2
PLL3
0
MSBS
INR1
MGNL3
DCLKE
0
LOM
LOMH
0
0
0
HPG3
SPKG3
IVL3
IVR3
REF3
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
FR
LFST
0
0
0
GN1
0
0
0
0
PMMIX
SDOAD
SDOBD
0
0
0
0
0
0
SDOR1
F1A7
0
F1B7
0
F2A7
0
F2B7
0
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
RFST1
ZELMN
0
OVTMB
HPFC1
GN0
0
SVAR2
OVL6
OVR6
RFST0
LMAT1
SDIM1
BIV2
HPFC0
LPF
0
SVAR1
OVL5
OVR5
PMSRBI
MSBSA
MSBSB
0
BVL5
CVL5
MX1R2
MX2C1
0
SDOL1
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
WTM2
LMAT0
SDIM0
BIV1
HPFAD
HPF
EQ5
SVAR0
OVL4
OVR4
WTM1
RGAIN1
5EQ
BIV0
DASEL1
EQ0
EQ4
0
OVL3
OVR3
PMOSC
LAWA1
LAWB1
0
BVL3
CVL3
MX1R0
MX2B1
0
0
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
PMSRBO
0
0
0
BVL6
CVL6
0
0
0
SDOR0
F1A6
0
F1B6
0
F2A6
0
F2B6
0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
MS1402-E-06
PMPCMB
BCKPA
BCKPB
0
BVL4
CVL4
MX1R1
MX2C0
0
SDOL0
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
D2
0
PMDAL
PMMP2
PLL2
0
BCKP
INR0
MGNL2
0
0
LOPS
0
0
0
LVL2
HPG2
SPKG2
IVL2
IVR2
REF2
D1
PMPFIL
PMDRC
MICL1
PLL1
M/S
DIF1
INL1
MGNL1
DCLKP
DACR
PMRO
PMHPR
D0
PMVCM
PMEQ
PMMP1
PLL0
PMPLL
DIF0
INL0
MGNL0
DMIC
DACL
PMLO
PMHPL
CPMODE1 CPMODE0
RCVPS
LVL1
HPG1
SPKG1
IVL1
IVR1
REF1
PMRCV
LVL0
HPG0
SPKG0
IVL0
IVR0
REF0
PFMXR0
PFMXL1
PFMXL0
WTM0
RGAIN0
ADM
SMUTE
DASEL0
FIL3
EQ3
SVAL2
OVL2
OVR2
ZTM1
LMTH1
IVOLC
OVTM
PFSDO
0
EQ2
SVAL1
OVL1
OVR1
PMSRAI
FMTA1
FMTB1
SVB1
BVL1
CVL1
MX1L1
MX2A1
MXSB1
SBMX1
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
ZTM0
LMTH0
ALC
OVOLC
PFSEL
0
EQ1
SVAL0
OVL0
OVR0
PMSRAO
LAWA0
LAWB0
SVB2
BVL2
CVL2
MX1L2
MX2B0
MXSB2
0
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
PMPCMA
FMTA0
FMTB0
SVB0
BVL0
CVL0
MX1L0
MX2A0
MXSB0
SBMX0
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
2013/02
- 154 -
[AK4679]
Addr
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
Reserved
Reserved
Reserved
5band E1 Co-efficient 0
5band E1 Co-efficient 1
5band E1 Co-efficient 2
5band E1 Co-efficient 3
5band E2 Co-efficient 0
5band E2 Co-efficient 1
5band E2 Co-efficient 2
5band E2 Co-efficient 3
5band E2 Co-efficient 4
5band E2 Co-efficient 5
5band E3 Co-efficient 0
5band E3 Co-efficient 1
5band E3 Co-efficient 2
5band E3 Co-efficient 3
5band E3 Co-efficient 4
5band E3 Co-efficient 5
5band E4 Co-efficient 0
5band E4 Co-efficient 1
5band E4 Co-efficient 2
5band E4 Co-efficient 3
5band E4 Co-efficient 4
5band E4 Co-efficient 5
5band E5 Co-efficient 0
5band E5 Co-efficient 1
5band E5 Co-efficient 2
5band E5 Co-efficient 3
5band EQ1 Gain
5band EQ2 Gain
5band EQ3 Gain
5band EQ4 Gain
5band EQ5 Gain
Reserved
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
0
0
0
5E1A7
0
5E1B7
0
5E2A7
5E2A15
5E2B7
5E2B15
5E2C7
5E2C15
5E3A7
5E3A15
5E3B7
5E3B15
5E3C7
5E3C15
5E4A7
5E4A15
5E4B7
5E4B15
5E4C7
5E4C15
5E5A7
0
5E5B7
0
0
0
0
0
0
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
0
0
0
5E1A6
0
5E1B6
0
5E2A6
5E2A14
5E2B6
5E2B14
5E2C6
5E2C14
5E3A6
5E3A14
5E3B6
5E3B14
5E3C6
5E3C14
5E4A6
5E4A14
5E4B6
5E4B14
5E4C6
5E4C14
5E5A6
0
5E5B6
0
0
0
0
0
0
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
0
0
0
5E1A5
5E1A13
5E1B5
5E1B13
5E2A5
5E2A13
5E2B5
5E2B13
5E2C5
5E2C13
5E3A5
5E3A13
5E3B5
5E3B13
5E3C5
5E3C13
5E4A5
5E4A13
5E4B5
5E4B13
5E4C5
5E4C13
5E5A5
5E5A13
5E5B5
5E5B13
EQ1G5
EQ2G5
EQ3G5
EQ4G5
EQ5G5
0
MS1402-E-06
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
0
0
0
5E1A4
5E1A12
5E1B4
5E1B12
5E2A4
5E2A12
5E2B4
5E2B12
5E2C4
5E2C12
5E3A4
5E3A12
5E3B4
5E3B12
5E3C4
5E3C12
5E4A4
5E4A12
5E4B4
5E4B12
5E4C4
5E4C12
5E5A4
5E5A12
5E5B4
5E5B12
EQ1G4
EQ2G4
EQ3G4
EQ4G4
EQ5G4
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
0
0
0
5E1A3
5E1A11
5E1B3
5E1B11
5E2A3
5E2A11
5E2B3
5E2B11
5E2C3
5E2C11
5E3A3
5E3A11
5E3B3
5E3B11
5E3C3
5E3C11
5E4A3
5E4A11
5E4B3
5E4B11
5E4C3
5E4C11
5E5A3
5E5A11
5E5B3
5E5B11
EQ1G3
EQ2G3
EQ3G3
EQ4G3
EQ5G3
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
0
0
0
5E1A2
5E1A10
5E1B2
5E1B10
5E2A2
5E2A10
5E2B2
5E2B10
5E2C2
5E2C10
5E3A2
5E3A10
5E3B2
5E3B10
5E3C2
5E3C10
5E4A2
5E4A10
5E4B2
5E4B10
5E4C2
5E4C10
5E5A2
5E5A10
5E5B2
5E5B10
EQ1G2
EQ2G2
EQ3G2
EQ4G2
EQ5G2
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
0
0
0
5E1A1
5E1A9
5E1B1
5E1B9
5E2A1
5E2A9
5E2B1
5E2B9
5E2C1
5E2C9
5E3A1
5E3A9
5E3B1
5E3B9
5E3C1
5E3C9
5E4A1
5E4A9
5E4B1
5E4B9
5E4C1
5E4C9
5E5A1
5E5A9
5E5B1
5E5B9
EQ1G1
EQ2G1
EQ3G1
EQ4G1
EQ5G1
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
0
0
0
5E1A0
5E1A8
5E1B0
5E1B8
5E2A0
5E2A8
5E2B0
5E2B8
5E2C0
5E2C8
5E3A0
5E3A8
5E3B0
5E3B8
5E3C0
5E3C8
5E4A0
5E4A8
5E4B0
5E4B8
5E4C0
5E4C8
5E5A0
5E5A8
5E5B0
5E5B8
EQ1G0
EQ2G0
EQ3G0
EQ4G0
EQ5G0
0
2013/02
- 155 -
[AK4679]
Addr
70H
71H
72H
73H
Register Name
DRC Mode Control
NS Control
NS Gain & ATT Control
NS On Level
D7
0
0
0
NSIAF1
74H
NS Off Level
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
NS Reference Select
NS LPF Co-efficient 0
NS LPF Co-efficient 1
NS LPF Co-efficient 2
NS LPF Co-efficient 3
NS HPF Co-efficient 0
NS HPF Co-efficient 1
NS HPF Co-efficient 2
NS HPF Co-efficient 3
Reserved
Reserved
DVLC Filter Select
DVLC Mode Control
DVLCL Curve X1
DVLCL Curve Y1
DVLCL Curve X2
DVLCL Curve Y2
DVLCL Curve X3
DVLCL Curve Y3
DVLCL Slope 1
DVLCL Slope 2
DVLCL Slope 3
DVLCL Slope 4
DVLCM Curve X1
DVLCM Curve Y1
DVLCM Curve X2
DVLCM Curve Y2
DVLCM Curve X3
DVLCM Curve Y3
DVLCM Slope 1
DVLCM Slope 2
DVLCM Slope 3
DVLCM Slope 4
DVLCH Curve X1
DVLCH Curve Y1
DVLCH Curve X2
DVLCH Curve Y2
DVLCH Curve X3
DVLCH Curve Y3
DVLCH Slope 1
DVLCH Slope 2
DVLCH Slope 3
DVLCH Slope 4
D6
D5
DLMAT2
DLMAT1
0
DRCM1
NSGAIN2
NSGAIN1
NSIAF0
0
NSOAF1
NSOAF0
0
0
NSLA7
0
NSLB7
0
NSHA7
0
NSHB7
0
0
0
DLLPF1
0
NSLA6
0
NSLB6
0
NSHA6
0
NSHB6
0
0
0
DLLPF0
0
NSLA5
NSLA13
NSLB5
NSLB13
NSHA5
NSHA13
NSHB5
NSHB13
0
0
DMHPF1
DVRGAIN2 DVRGAIN1 DVRGAIN0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L1G6
L2G6
L3G6
L4G6
0
0
0
0
0
0
M1G6
M2G6
M3G6
M4G6
0
0
0
0
0
0
H1G6
H2G6
H3G6
H4G6
VL1X5
VL1Y5
VL2X5
VL2Y5
0
0
L1G5
L2G5
L3G5
L4G5
VM1X5
VM1Y5
VM2X5
VM2Y5
0
0
M1G5
M2G5
M3G5
M4G5
VH1X5
VH1Y5
VH2X5
VH2Y5
0
0
H1G5
H2G5
H3G5
H4G5
MS1402-E-06
D4
D3
D2
DLMAT0
DRGAIN1
DRGAIN0
D1
DRCC1
DRCM0
0
NSLPF
NSHPF
NSGAIN0
0
NSATT2 NSATT1
NSTHL4 NSTHL3 NSTHL2 NSTHL1
NSTHH
NSTHH
NSTHH
NSTHH3
2
1
4
0
NSREF3 NSREF2 NSREF1
NSLA4
NSLA3
NSLA2
NSLA1
NSLA12 NSLA11 NSLA10
NSLA9
NSLB4
NSLB3
NSLB2
NSLB1
NSLB12 NSLB11 NSLB10
NSLB9
NSHA4
NSHA3
NSHA2
NSHA1
NSHA12 NSHA11 NSHA10 NSHA9
NSHB4
NSHB3
NSHB2
NSHB1
NSHB12 NSHB11 NSHB10
NSHB9
0
0
0
0
0
0
0
0
DMHPF0 DMLPF1 DMLPF0 DHHPF1
DVLMAT2 DVLMAT1 DVLMAT0
DAF1
VL1X4
VL1X3
VL1X2
VL1X1
VL1Y4
VL1Y3
VL1Y2
VL1Y1
VL2X4
VL2X3
VL2X2
VL2X1
VL2Y4
VL2Y3
VL2Y2
VL2Y1
VL3X4
VL3X3
VL3X2
VL3X1
VL3Y4
VL3Y3
VL3Y2
VL3Y1
L1G4
L1G3
L1G2
L1G1
L2G4
L2G3
L2G2
L2G1
L3G4
L3G3
L3G2
L3G1
L4G4
L4G3
L4G2
L4G1
VM1X4
VM1X3
VM1X2
VM1X1
VM1Y4
VM1Y3
VM1Y2
VM1Y1
VM2X4
VM2X3
VM2X2
VM2X1
VM2Y4
VM2Y3
VM2Y2
VM2Y1
VM3X4
VM3X3
VM3X2
VM3X1
VM3Y4
VM3Y3
VM3Y2
VM3Y1
M1G4
M1G3
M1G2
M1G1
M2G4
M2G3
M2G2
M2G1
M3G4
M3G3
M3G2
M3G1
M4G4
M4G3
M4G2
M4G1
VH1X4
VH1X3
VH1X2
VH1X1
VH1Y4
VH1Y3
VH1Y2
VH1Y1
VH2X4
VH2X3
VH2X2
VH2X1
VH2Y4
VH2Y3
VH2Y2
VH2Y1
VH3X4
VH3X3
VH3X2
VH3X1
VH3Y4
VH3Y3
VH3Y2
VH3Y1
H1G4
H1G3
H1G2
H1G1
H2G4
H2G3
H2G2
H2G1
H3G4
H3G3
H3G2
H3G1
H4G4
H4G3
H4G2
H4G1
D0
DRCC0
NSCE
NSATT0
NSTHL0
NSTHH
0
NSREF0
NSLA0
NSLA8
NSLB0
NSLB8
NSHA0
NSHA8
NSHB0
NSHB8
0
0
DHHPF0
DAF0
VL1X0
VL1Y0
VL2X0
VL2Y0
VL3X0
VL3Y0
L1G0
L2G0
L3G0
L4G0
VM1X0
VM1Y0
VM2X0
VM2Y0
VM3X0
VM3Y0
M1G0
M2G0
M3G0
M4G0
VH1X0
VH1Y0
VH2X0
VH2Y0
VH3X0
VH3Y0
H1G0
H2G0
H3G0
H4G0
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Addr
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
Register Name
DVLCL LPF Co-efficient 0
DVLCL LPF Co-efficient 1
DVLCL LPF Co-efficient 2
DVLCL LPF Co-efficient 3
DVLCM HPF Co-efficient 0
DVLCM HPF Co-efficient 1
DVLCM HPF Co-efficient 2
DVLCM HPF Co-efficient 3
DVLCM LPF Co-efficient 0
DVLCM LPF Co-efficient 1
DVLCM LPF Co-efficient 2
DVLCM LPF Co-efficient 3
DVLCH HPF Co-efficient 0
DVLCH HPF Co-efficient 1
DVLCH HPF Co-efficient 2
DVLCH HPF Co-efficient 3
D7
DLLA7
0
DLLB7
0
DMHA7
0
DMHB7
0
DMLA7
0
DMLB7
0
DHHA7
0
DHHB7
0
D6
DLLA6
0
DLLB6
0
DMHA6
0
DMHB6
0
DMLA6
0
DMLB6
0
DHHA6
0
DHHB6
0
D5
DLLA5
DLLA13
DLLB5
DLLB13
DMHA5
DMHA13
DMHB5
DMHB13
DMLA5
DMLA13
DMLB5
DMLB13
DHHA5
DHHA13
DHHB5
DHHB13
D4
D3
D2
DLLA4
DLLA3
DLLA2
DLLA12 DLLA11 DLLA10
DLLB4
DLLB3
DLLB2
DLLB12 DLLB11 DLLB10
DMHA4 DMHA3 DMHA2
DMHA12 DMHA11 DMHA10
DMHB4
DMHB3
DMHB2
DMHB12 DMHB11 DMHB10
DMLA4
DMLA3
DMLA2
DMLA12 DMLA11 DMLA10
DMLB4
DMLB3
DMLB2
DMLB12 DMLB11 DMLB10
DHHA4
DHHA3
DHHA2
DHHA12 DHHA11 DHHA10
DHHB4
DHHB3
DHHB2
DHHB12 DHHB11 DHHB10
D1
DLLA1
DLLA9
DLLB1
DLLB9
DMHA1
DMHA9
DMHB1
DMHB9
DMLA1
DMLA9
DMLB1
DMLB9
DHHA1
DHHA9
DHHB1
DHHB9
D0
DLLA0
DLLA8
DLLB0
DLLB8
DMHA0
DMHA8
DMHB0
DMHB8
DMLA0
DMLA8
DMLB0
DMLB8
DHHA0
DHHA8
DHHB0
DHHB8
Note 80. PDNA pin = “L” resets the registers to their default values.
Note 81. The bits defined as 0 must contain a “0” value.
Note 82. For Addresses B0H to FFH, data must not be written.
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■ Register Definition
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
0
R
0
D6
0
R
0
D5
PMADR
R/W
0
D4
PMADL
R/W
0
D3
0
R
0
D2
0
R
0
D1
PMPFIL
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
PMPFIL: Programmable Filter Block Power Management
0: Power down (default)
1: Power up
PMADL: MIC-Amp Lch & ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL(PMDML) or PMADR(PMDMR) bit is changed from “0” to “1”, the digital initialization
cycle (1059/fs=24ms @ 44.1kHz, ADRST bit = “0”) starts. After initializing, digital data of the ADC is
output.
PMADR: MIC-Amp Rch & ADC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDNA pin is “L”,
Audio blocks are powered-down regardless of setting of this address. In this case, CODEC register is initialized to the
default value.
When all power management bits are “0”, Audio blocks are powered-down. The register values remain unchanged.
Power supply current is 50μA(typ) in this case. For fully shut down (typ. 1μA), PDNA pin should be “L”.
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Addr
01H
Register Name
Power Management 1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
PMDAR
R/W
0
D2
PMDAL
R/W
0
D1
PMDRC
R/W
0
D0
PMEQ
R/W
0
PMEQ: 5-band Parametric Equalizer Block Power Management
0: Power down (default)
1: Power up
PMDRC: Dynamic Range Control Block Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDNA pin is “L”,
all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value.
Addr
02H
Register Name
Power Management 1
R/W
Default
D7
ADRST
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
MICL2
R/W
0
D2
PMMP2
R/W
0
D1
MICL1
R/W
0
D0
PMMP1
R/W
0
PMMP1: MPWR1 pin Power Management
0: Power down: Hi-Z (default)
1: Power up
MICL1: MIC Power (MPWR1 pin) Output Level select
Default “0”, typ. 2.5V (Table 22)
PMMP2: MPWR2 pin Power Management
0: Power down: Hi-Z (default)
1: Power up
MICL2: MIC Power (MPWR2 pin) Output Level Select
Default “0”, typ. 2.5V (Table 22)
ADRST: ADC Initialization Cycle Setting
0: 1059/fs (default)
1: 267/fs
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Addr
03H
Register Name
PLL Mode Select 0
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
1
D5
FS1
R/W
1
D4
FS0
R/W
1
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
D3
0
R
0
D2
0
R
0
D1
M/S
R/W
0
D0
PMPLL
R/W
0
D3
MSBS
R/W
0
D2
BCKP
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0110” (MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (Table 6, Table 11 and Table 14)
Default: “1111” (fs=44.1kHz)
Addr
04H
Register Name
PLL Mode Select 1
R/W
Default
D7
CM1
R/W
0
D6
CM0
R/W
0
D5
BCKO
R/W
0
D4
0
R
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
BCKO: BICK Output Frequency Select at Master Mode (Table 9)
CM1-0: MCKI Frequency Select at EXT Mode (Table 10 and Table 13)
Default: “00” (256fs)
Addr
05H
Register Name
Audio I/F Format Select
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
SDOD
R/W
0
DIF1-0: Audio Interface Format (Table 18)
Default: “10” (24bit Left justified)
BCKP: BICK Polarity at DSP Mode (Table 19)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Phase at DSP Mode (Table 19)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
SDOD: SDTO Disable (Table 83)
“0”: Enable (default)
“1”: Disable (“L”)
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Addr
06H
Register Name
MIC Signal Select
R/W
Default
D7
0
R
0
D6
MDIF3
R/W
0
D5
MDIF2
R/W
0
D4
MDIF1
R/W
0
D3
INR1
R/W
0
D2
INR0
R/W
0
D1
INL1
R/W
0
D0
INL0
R/W
0
D5
MGNR1
R/W
0
D4
MGNR0
R/W
1
D3
MGNL3
R/W
0
D2
MGNL2
R/W
1
D1
MGNL1
R/W
0
D0
MGNL0
R/W
1
D3
DCLKE
R/W
0
D2
0
R
0
D1
DCLKP
R/W
0
D0
DMIC
R/W
0
INL1-0: MIC-Amp Lch Input Source Select (Table 20)
Default: “00” (LIN1)
INR1-0: MIC-Amp Rch Input Source Select (Table 20)
Default: “00” (RIN1)
MDIF1: Line1 Input Type Select
0: Single-ended input (LIN1/RIN1 pins: default)
1: Full-differential input (IN1+/IN1− pins)
MDIF2: Line2 Input Type Select
0: Single-ended input (LIN2/RIN2 pins: default)
1: Full-differential input (IN2−/IN2+ pins)
MDIF3: Line3 Input Type Select
0: Single-ended input (LIN3/RIN3 pins: default)
1: Full-differential input (IN3+/IN3− pins)
Addr
07H
Register Name
MIC Amp Gain
R/W
Default
D7
MGNR3
R/W
0
D6
MGNR2
R/W
1
MGNL3-0: MIC-Amp Lch Gain Control (Table 21)
Default: “0101” (0dB)
MGNR3-0: MIC-Amp Rch Gain Control (Table 21)
Default: “0101” (0dB)
Addr
08H
Register Name
Digital MIC
R/W
Default
D7
0
R
0
D6
0
R
0
D5
D4
PMDMR
PMDML
R/W
0
R/W
0
DMIC: Digital Microphone Connection Select
0: Analog Microphone (default)
1: Digital Microphone
DCLKP: Data Latching Edge Select
0: Lch data is latched on the DMCLK rising edge (“↑”). (default)
1: Lch data is latched on the DMCLK falling edge (“↓”).
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDML/R: Input Signal Select with Digital Microphone (Table 77)
Default: “0”
When DMIC bit is “1”, these registers are enabled. ADC digital block is powered-down by PMDML = PMDMR
bits = “0” when selecting a digital microphone input (DMIC bit = “1”).
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Addr
09H
Register Name
DAC Signal Pass Select
R/W
Default
D7
DACSR
R/W
0
D6
DACSL
R/W
0
D5
DACRR
R/W
0
D4
DACRL
R/W
0
D3
0
R
0
D2
0
R
0
D1
DACR
R/W
0
D0
DACL
R/W
0
DACL: Switch Control from DAC Lch to LOUT
0: OFF (default)
1: ON
DACR: Switch Control from DAC Rch to ROUT
0: OFF (default)
1: ON
DACRL: Switch Control from DAC Lch to RCV-Amp
0: OFF (default)
1: ON
DACRR: Switch Control from DAC Rch to RCV-Amp
0: OFF (default)
1: ON
DACSL: Switch Control from DAC Lch to SPK-Amp
0: OFF (default)
1: ON
DACSR: Switch Control from DAC Rch to SPK-Amp
0: OFF (default)
1: ON
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Addr
0AH
Register Name
D7
0
R
0
LINEOUT Power Management
R/W
Default
D6
0
R
0
D5
0
R
0
D4
LODIF
R/W
0
D3
LOM
R/W
0
D2
LOPS
R/W
0
D1
PMRO
R/W
0
D0
PMLO
R/W
0
D3
LOMH
R/W
0
D2
0
R
0
D1
PMHPR
R/W
0
D0
PMHPL
R/W
0
PMLO: LOUT Power Management
0: Power down (default)
1: Power up
PMRO: ROUT Power Management
0: Power down (default)
1: Power up
LOPS: LOUT/ROUT Power Management
0: Normal Operation (default)
1: Power Save Mode
LOM: Mono Mixing from DAC to LOUT/ROUT
0: Stereo Mixing (default)
1: Mono Mixing
LODIF: Lineout Mode Select
0: Stereo Single-ended Line Output (LOUT/ROUT pins) (default)
1: Mono Full-differential Output (LOP/LON pins)
Addr
0BH
Register Name
HP Power Management
R/W
Default
D7
HPTM1
R/W
0
D6
HPTM0
R/W
0
D5
0
R
0
D4
0
R
0
PMHPL: HPL Power Management
0: Power down (default)
1: Power up
PMHPR: HPR Power Management
0: Power down (default)
1: Power up
LOMH: Mono Mixing from DAC to HPL/HPR
0: Stereo Mixing (default)
1: Mono Mixing
HPTM1-0: Headphone-Amp Volume Zero Crossing Timeout Period (Table 107)
Default: “00” (128/fs)
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Addr
0CH
Register Name
Charge Pump Control
R/W
Default
D7
0
R
0
D6
D5
D4
VDDTM2
VDDTM1
VDDTM0
R/W
1
R/W
0
R/W
1
D3
0
R
0
D2
0
R
0
D1
D0
CPMODE1 CPMODE0
R/W
0
R/W
0
D1
RCVPS
R/W
0
D0
PMRCV
R/W
0
D1
LVL1
R/W
1
D0
LVL0
R/W
1
CPMODE1-0: Charge-pump Mode Setting (Table 108)
Default: “00” (Automatic Switching)
VDDTM2-0: VDD Mode Waiting Period (Table 109)
Default: “101” (32768/fs)
Addr
0DH
Register Name
SPK & RCV Power Management
R/W
Default
D7
THDET
R
0
D6
0
R
0
D5
TEST
R/W
0
D6
0
R
0
D5
0
R
0
D4
PMSPK
R/W
0
D3
0
R
0
D2
0
R
0
PMRCV: Receiver-Amp Power Management
0: Power down (default)
1: Power up
RCVPS: Receiver-Amp Power Save Mode
0: Normal Operation (default)
1: Power Save Mode
PMSPK: Speaker-Amp Power Management
0: Power down (default)
1: Power up
TEST: Device TEST mode Enable.
0: Normal operation (default)
1: TEST mode
TEST bit must be always “0”.
THDET: Thermal Shutdown Detection
0: Normal Operation (default)
1: Thermal Shutdown status
Addr
0EH
Register Name
LINEOUT Volume Control
R/W
Default
D7
0
R
0
D4
0
R
0
D3
0
R
0
D2
LVL2
R/W
0
LVL2-0: LINEOUT Volume Control (Table 101)
Default: “3H” (0dB)
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Addr
0FH
Register Name
HP Volume Control
R/W
Default
D7
0
R
0
D6
0
R
0
D5
HPG5
R/W
1
D4
HPG4
R/W
0
D3
HPG3
R/W
0
D2
HPG2
R/W
0
D1
HPG1
R/W
1
D0
HPG0
R/W
1
D5
RCVG1
R/W
1
D4
RCVG0
R/W
1
D3
SPKG3
R/W
1
D2
SPKG2
R/W
0
D1
SPKG1
R/W
1
D0
SPKG0
R/W
1
D5
IVL5
IVR5
R/W
0
D4
IVL4
IVR4
R/W
1
D3
IVL3
IVR3
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D3
REF3
R/W
0
D2
REF2
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
HPG5-0: Headphone Volume Control (Table 106)
Default: “23H” (0dB)
Addr
10H
Register Name
SPK & RCV Volume Control
R/W
Default
D7
RCVG3
R/W
1
D6
RCVG2
R/W
0
SPKG3-0: Speaker Volume Control (Table 111)
Default: “BH” (0dB)
RCVG3-0: Receiver Volume Control (Table 104)
Default: “BH” (0dB)
Addr
11H
12H
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
0
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 37)
Default: “91H” (0dB)
Addr
13H
Register Name
ALC Reference Select
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
D5
REF5
R/W
1
D4
REF4
R/W
0
REF7-0: Reference Value at ALC Recovery Operation (Recording); 0.375dB step, 242 Level (Table 33)
Default: “E1H” (+30.0dB)
Addr
14H
Register Name
Digital Mixing Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PFMXL1-0: 5-band EQ Lch Input Mixing 1 (Table 85)
Default: “00” (SDTI)
PFMXR1-0: 5-band EQ Rch Input Mixing 1 (Table 86)
Default: “00” (SDTI)
SRMXL1-0: 5-band EQ Lch Input Mixing 2 (Table 87)
Default: “00” (SDTI)
SRMXR1-0: 5-band EQ Rch Input Mixing 2 (Table 88)
Default: “00” (SDTI)
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Addr
15H
Register Name
ALC Timer Select
R/W
Default
D7
FR
R/W
0
D6
RFST1
R/W
0
D5
RFST0
R/W
0
D4
WTM2
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
ZTM1
R/W
0
D0
ZTM0
R/W
0
D2
RGAIN0
R/W
0
D1
LMTH1
R/W
0
D0
LMTH0
R/W
0
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 30)
Default: “00” (128/fs)
WTM2-0: ALC Recovery Waiting Period (Table 31)
Default: “000” (128/fs)
RFST1-0: ALC Fast recovery Speed (Table 34)
Default: “00” (4times)
FR: Fast recovery Enable
0: Enable (default)
1: Disable
Addr
16H
Register Name
ALC Mode Control
R/W
Default
D7
LFST
R/W
0
D6
ZELMN
R/W
0
D5
LMAT1
R/W
0
D4
LMAT0
R/W
0
D3
RGAIN1
R/W
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 28)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (Table 32)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 29)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
LFST: ALC Limiter operation when the output level exceeds FS(full-scale) level.
0: The volume is changed at zero crossing or zero crossing time out (default)
1: When output of ALC is larger than FS, IVL/IVR values are changed immediately (1/fs).
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Addr
17H
Register Name
Mode Control 0
R/W
Default
D7
0
R
0
D6
0
R
0
D5
SDIM1
R/W
0
D4
SDIM0
R/W
0
D3
5EQ
R/W
0
D2
ADM
R/W
0
D1
IVOLC
R/W
1
D0
ALC
R/W
0
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
ADM: Mono Recording (Table 79)
0: Stereo (default)
1: Mono: (L+R)/2
5EQ: Select 5-Band Equalizer
0: OFF (default)
1: ON
SDIM1-0: SDTI Input Signal Select (Table 84)
Default: “00” (L=Lch, R=Rch)
Addr
18H
Register Name
Mode Control 0
R/W
Default
D7
0
R
0
D6
OVTMB
R/W
1
D5
BIV2
R/W
0
D4
BIV1
R/W
0
D3
BIV0
R/W
0
D2
SMUTE
R/W
0
D1
OVTM
R/W
1
D0
OVOLC
R/W
1
OVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When OVOLC bit = “1”, OVL6-0 bits control both Lch and Rch volume level, while register values of
OVL6-0 bits are not written to OVR6-0 bits. When OVOLC bit = “0”, OVL6-0 bits control Lch level and
OVR6-0 bits control Rch level, respectively.
OVTM: Digital Volume Transition Time Setting
0: 128/fs
1: 256/fs (default)
This is the transition time between OVL/R6-0 bits = 00H and 7FH.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
BIV2-0: SDTIB Input Volume Control (Table 75)
Default: “0H” (0dB)
OVTMB: Digital Volume Control (DATT-B and DATT-C) Transition Time Setting
0: 128/fs
1: 256/fs (default)
This is the transition time between BVL6-0 bits or CVL6-0 bits = 00H and 7FH.
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Addr
19H
Register Name
Digital Filter Select 0
R/W
Default
D7
0
R
0
D6
HPFC1
R/W
0
D5
HPFC0
R/W
0
D4
HPFAD
R/W
1
D3
D2
DASEL1 DASEL0
R/W
R/W
0
0
D1
PFSDO
R/W
1
D0
PFSEL
R/W
0
PFSEL: Signal Select of Programmable Filter Block (Table 78)
0: ADC Output Data (default)
1: SDTI Input Data
PFSDO: SDTO Output and SVOLA Input Signal Select (Table 80)
0: ADC (+1st HPF) Output
1: Programmable Filter Output (default)
DASEL1-0: DAC Input Signal Select (Table 89)
Default: “00” (L= DATT-A Lch, R= DATT-A Rch)
HPFAD: HPF1 Control of ADC
0: OFF
1: ON (default)
When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, HPFAD block is
through (0dB).
When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”.
HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) (Table 38)
Default: “00” (3.4Hz @ fs = 44.1kHz)
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Addr
1AH
Register Name
Digital Filter Select 1
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
EQ0
R/W
0
D2
FIL3
R/W
0
D1
0
R
0
D0
0
R
0
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block
is OFF (MUTE).
EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E0C15-0 bits are enabled. When EQ0 bit is “0”,
EQ0 block is through (0dB).
HPF: HPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block
is through (0dB).
LPF: LPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block
is through (0dB).
GN1-0: Gain Select at GAIN block (Table 27)
Default: “00” (0dB)
Addr
1BH
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
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Addr
1CH
Register Name
Side Tone A Control
R/W
Default
D7
0
R
0
D6
SVAR2
R/W
0
D5
SVAR1
R/W
0
D4
SVAR0
R/W
0
D3
0
R
0
D2
SVAL2
R/W
0
D1
SVAL1
R/W
0
D0
SVAL0
R/W
0
D4
OVL4
OVR4
R/W
0
D3
OVL3
OVR3
R/W
1
D2
OVL2
OVR2
R/W
1
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
0
SVAL2-0, SVAR2-0: Side Tone Volume A (SVOLA) (Table 39)
Default: “000” (0dB)
Addr
1DH
1EH
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
D7
0
0
R
0
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
OVL6-0, OVR6-0: Output Digital Volume (Table 68)
Default: “0CH” (0dB)
Addr
1FH
Register Name
PCM I/F Power Management
R/W
Default
D7
PMMIX
R/W
0
D6
D5
D4
D3
D2
D1
D0
PMSRBO
PMSRBI
PMPCMB
PMOSC
PMSRAO
PMSRAI
PMPCMA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMPCMA: PCM I/F A Power Management
0: Power down (default)
1: Power up
PMSRAI: SRCAI Power Management
0: Power down (default)
1: Power up
PMSRAO: SRCAO Power Management
0: Power down (default)
1: Power up
PMOSC: Internal Oscillator Power Management
0: Power down (default)
1: Power up
PMPCMB: PCM I/F B Power Management
0: Power down (default)
1: Power up
PMSRBI: SRCBI Power Management
0: Power down (default)
1: Power up
PMSRBO: SRCBO Power Management
0: Power down (default)
1: Power up
PMMIX: MIX1 Block Power Management
0: Power down (default)
1: Power up
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Addr
20H
Register Name
PCM I/F Control 0
R/W
Default
D7
SDOAD
R/W
0
D6
0
R
0
D5
MSBSA
R/W
0
D4
BCKPA
R/W
0
D3
LAWA1
R/W
0
D2
LAWA0
R/W
0
D1
FMTA1
R/W
0
D0
FMTA0
R/W
0
FMTA1-0: PCM I/F A Format (Table 117)
Default: “00” (Mode 0)
LAWA1-0: PCM I/F A Mode (Table 115)
Default: “00” (Mode 0)
BCKPA: P BICKA Polarity of PCM I/F A (Table 119)
“0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”). (default)
“1”: SDTOA is output by the falling edge (“↓”) of BICKA and SDTIA is latched by the rising edge (“↑”).
MSBSA: SYNCA Phase of PCM I/F A (Table 119)
“0”: The rising edge (“↑”) of SYNCA is half clock of BICKA before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCA is one clock of BICKA before the channel change.
SDOAD: SDTOA Disable (Table 96)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
21H
Register Name
PCM I/F Control 1
R/W
Default
D7
SDOBD
R/W
0
D6
0
R
0
D5
MSBSB
R/W
0
D4
BCKPB
R/W
0
D3
LAWB1
R/W
0
D2
LAWB0
R/W
0
D1
FMTB1
R/W
0
D0
FMTB0
R/W
0
FMTB1-0: PCM I/F B Format (Table 118)
Default: “00” (Mode 0)
LAWB1-0: PCM I/F B Mode (Table 116)
Default: “00” (Mode 0)
BCKPB: BICKB Polarity of PCM I/F B (Table 120)
“0”: SDTOB is output by the rising edge (“↑”) of BICKB and SDTIB is latched by the falling edge (“↓”). (default)
“1”: SDTOB is output by the falling edge (“↓”) of BICKB and SDTIB is latched by the rising edge (“↑”).
MSBSB: SYNCB Phase of PCM I/F B (Table 120)
“0”: The rising edge (“↑”) of SYNCB is half clock of BICKB before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCB is one clock of BICKB before the channel change.
SDOBD: SDTOB Disable (Table 98)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
22H
Register Name
Side Tone Volume B Control
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
SVB2
R/W
0
D1
SVB1
R/W
0
D0
SVB0
R/W
0
SVB2-0: Side Tone Volume B (Table 74)
Default: “0H” (0dB)
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Addr
23H
Register Name
Digital Volume B Control
R/W
Default
D7
0
R
0
D6
BVL6
R/W
0
D5
BVL5
R/W
0
D4
BVL4
R/W
0
D3
BVL3
R/W
1
D2
BVL2
R/W
1
D1
BVL1
R/W
0
D0
BVL0
R/W
0
D6
CVL6
R/W
0
D5
CVL5
R/W
0
D4
CVL4
R/W
0
D3
CVL3
R/W
1
D2
CVL2
R/W
1
D1
CVL1
R/W
0
D0
CVL0
R/W
0
D6
0
R
0
D5
MX1R2
R/W
0
D4
MX1R1
R/W
0
D3
MX1R0
R/W
0
D2
MX1L2
R/W
0
D1
MX1L1
R/W
0
D0
MX1L0
R/W
0
D5
MX2C1
R/W
0
D4
MX2C0
R/W
0
D3
MX2B1
R/W
0
D2
MX2B0
R/W
0
D1
MX2A1
R/W
0
D0
MX2A0
R/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
MXSB2
R/W
0
D1
MXSB1
R/W
0
D0
MXSB0
R/W
0
BVL6-0: Digital Volume B (Table 70)
Default: “0CH” (0dB)
Addr
24H
Register Name
Digital Volume C Control
R/W
Default
D7
0
R
0
CVL6-0: Digital Volume C (Table 72)
Default: “0CH” (0dB)
Addr
25H
Register Name
Digital Mixing Control 0
R/W
Default
D7
0
R
0
MX1L2-0: MIX1 Lch Output Signal Select (Table 90)
Default: “000” (DATT-B)
MX1R2-0: MIX1 Rch Output Signal Select (Table 91)
Default: “000” (DATT-B)
Addr
26H
Register Name
Digital Mixing Control 1
R/W
Default
D7
0
R
0
D6
0
R
0
MX2A1-0: MIX2A Output Signal Select (Table 92)
Default: “00” (BIVOL Lch)
MX2B1-0: MIX2B Output Signal Select (Table 93)
Default: “00” (DATT-A Lch)
MX2C1-0: MIX2C Output Signal Select (Table 94)
Default: “00” (MIX2A)
Addr
27H
Register Name
Digital Mixing Control 2
R/W
Default
D7
0
R
0
D6
0
R
0
MXSB2-0: MIX3 Output Signal Select (Table 95)
Default: “000” (DATT-A Lch, DATT-A Rch)
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Addr
28H
Register Name
Digital Mixing Control 3
R/W
Default
D7
SDOR1
R/W
0
D6
SDOR0
R/W
0
D5
SDOL1
R/W
0
D4
SDOL0
R/W
0
D3
0
R
0
D2
0
R
0
D1
SBMX1
R/W
0
D0
SBMX0
R/W
0
SBXM1-0: DATT-C Input Signal Selec (Table 97)
Default: “00” (SRCAI)
SDOL1-0: SDTO Lch Output Mixing (Table 81)
Default: “00” (Lch Signal Selected by Table 80)
SDOR1-0: SDTO Rch Output Mixing (Table 82)
Default: “00” (Rch Signal Selected by Table 80)
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Addr
29H
2AH
2BH
2CH
Register Name
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
R/W
D6
F1A6
0
F1B6
0
R/W
D5
F1A5
F1A13
F1B5
F1B13
R/W
D4
F1A4
F1A12
F1B4
F1B12
R/W
D3
F1A3
F1A11
F1B3
F1B11
R/W
D2
F1A2
F1A10
F1B2
F1B10
R/W
D1
F1A1
F1A9
F1B1
F1B9
R/W
D0
F1A0
F1A8
F1B0
F1B8
R/W
F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH”
F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” ([email protected]=44.1kHz)
Addr
2DH
2EH
2FH
30H
Register Name
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
R/W
0
D6
F2A6
0
F2B6
0
R/W
0
D5
F2A5
F2A13
F2B5
F2B13
R/W
0
D4
F2A4
F2A12
F2B4
F2B12
R/W
0
D3
F2A3
F2A11
F2B3
F2B11
R/W
0
D2
F2A2
F2A10
F2B2
F2B10
R/W
0
D1
F2A1
F2A9
F2B1
F2B9
R/W
0
D0
F2A0
F2A8
F2B0
F2B8
R/W
0
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
R/W
0
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
R/W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
R/W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
R/W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
R/W
0
F2A13-0, F2B13-B0: FIL2 (LPF) Coefficient (14bit x 2)
Default: “0000H”
Addr
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
R/W
0
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
R/W
0
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
R/W
0
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3(Stereo Separation Emphasis Filter) Select
0: HPF (default)
1: LPF
E0A15-0, E0B13-0, E0C15-C0: EQ0 (Gain Compensation Filter) Coefficient (14bit x 1 + 16bit x 2)
Default: “0000H”
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Addr
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
R/W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
R/W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
R/W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
R/W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
R/W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
R/W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
R/W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
R/W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
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[AK4679]
Addr
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
Register Name
5band E1 Co-efficient 0
5band E1 Co-efficient 1
5band E1 Co-efficient 2
5band E1 Co-efficient 3
5band E2 Co-efficient 0
5band E2 Co-efficient 1
5band E2 Co-efficient 2
5band E2 Co-efficient 3
5band E2 Co-efficient 4
5band E2 Co-efficient 5
5band E3 Co-efficient 0
5band E3 Co-efficient 1
5band E3 Co-efficient 2
5band E3 Co-efficient 3
5band E3 Co-efficient 4
5band E3 Co-efficient 5
5band E4 Co-efficient 0
5band E4 Co-efficient 1
5band E4 Co-efficient 2
5band E4 Co-efficient 3
5band E4 Co-efficient 4
5band E4 Co-efficient 5
5band E5 Co-efficient 0
5band E5 Co-efficient 1
5band E5 Co-efficient 2
5band E5 Co-efficient 3
R/W
D7
5E1A7
0
5E1B7
0
5E2A7
5E2A15
5E2B7
5E2B15
5E2C7
5E2C15
5E3A7
5E3A15
5E3B7
5E3B15
5E3C7
5E3C15
5E4A7
5E4A15
5E4B7
5E4B15
5E4C7
5E4C15
5E5A7
0
5E5B7
0
R/W
D6
5E1A6
0
5E1B6
0
5E2A6
5E2A14
5E2B6
5E2B14
5E2C6
5E2C14
5E3A6
5E3A14
5E3B6
5E3B14
5E3C6
5E3C14
5E4A6
5E4A14
5E4B6
5E4B14
5E4C6
5E4C14
5E5A6
0
5E5B6
0
R/W
D5
5E1A5
5E1A13
5E1B5
5E1B13
5E2A5
5E2A13
5E2B5
5E2B13
5E2C5
5E2C13
5E3A5
5E3A13
5E3B5
5E3B13
5E3C5
5E3C13
5E4A5
5E4A13
5E4B5
5E4B13
5E4C5
5E4C13
5E5A5
5E5A13
5E5B5
5E5B13
R/W
D4
5E1A4
5E1A12
5E1B4
5E1B12
5E2A4
5E2A12
5E2B4
5E2B12
5E2C4
5E2C12
5E3A4
5E3A12
5E3B4
5E3B12
5E3C4
5E3C12
5E4A4
5E4A12
5E4B4
5E4B12
5E4C4
5E4C12
5E5A4
5E5A12
5E5B4
5E5B12
R/W
D3
5E1A3
5E1A11
5E1B3
5E1B11
5E2A3
5E2A11
5E2B3
5E2B11
5E2C3
5E2C11
5E3A3
5E3A11
5E3B3
5E3B11
5E3C3
5E3C11
5E4A3
5E4A11
5E4B3
5E4B11
5E4C3
5E4C11
5E5A3
5E5A11
5E5B3
5E5B11
R/W
D2
5E1A2
5E1A10
5E1B2
5E1B10
5E2A2
5E2A10
5E2B2
5E2B10
5E2C2
5E2C10
5E3A2
5E3A10
5E3B2
5E3B10
5E3C2
5E3C10
5E4A2
5E4A10
5E4B2
5E4B10
5E4C2
5E4C10
5E5A2
5E5A10
5E5B2
5E5B10
R/W
D1
5E1A1
5E1A9
5E1B1
5E1B9
5E2A1
5E2A9
5E2B1
5E2B9
5E2C1
5E2C9
5E3A1
5E3A9
5E3B1
5E3B9
5E3C1
5E3C9
5E4A1
5E4A9
5E4B1
5E4B9
5E4C1
5E4C9
5E5A1
5E5A9
5E5B1
5E5B9
R/W
D0
5E1A0
5E1A8
5E1B0
5E1B8
5E2A0
5E2A8
5E2B0
5E2B8
5E2C0
5E2C8
5E3A0
5E3A8
5E3B0
5E3B8
5E3C0
5E3C8
5E4A0
5E4A8
5E4B0
5E4B8
5E4C0
5E4C8
5E5A0
5E5A8
5E5B0
5E5B8
R/W
5E1A13-0, 5E1B13-B0: 5-band Equalizer 1 Coefficient (14bit x 2)
Default: 5E1A13-0 bits = “003AH”, 5E1B13-0 bits = “2074H” ([email protected]=44.1kHz)
5E2A15-0, 5E2B15-0, 5E2C15-0: 5-band Equalizer 2 Coefficient (16bit x3)
Default: 5E2A15-0 bits = “001DH”, 5E2B15-0 bits = “ 3FBB H”, 5E2C15-0 bits = “E03AH”
(fo2=250Hz, [email protected]=44.1kHz)
5E3A15-0, 5E3B15-0, 5E3C15-0: 5-band Equalizer 3 Coefficient (16bit x3)
Default: 5E3A15-0 bits = “0073H”, 5E3B15-0 bits = “3E76H”, 5E3C15-0 bits = “E0E6H”
(fo3=1kHz, [email protected]=44.1kHz)
5E4A15-0, 5E4B15-0, 5E4C15-0: 5-band Equalizer 4 Coefficient (16bit x3)
Default: 5E4A15-0 bits = “0185H”, 5E4B15-0 bits = “3589H”, 5E4C15-0 bits = “E30BH”
(fo4=3.5kHz, [email protected]=44.1kHz)
5E5A13-0, 5E5B13-B0: 5-band Equalizer 5 Coefficient (14bit x 2)
Default: 5E5A13-0 bits = “112CH”, 5E5B13-0 bits = “3DA9H” ([email protected]=44.1kHz)
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Addr
6AH
6BH
6CH
6DH
6EH
Register Name
5band EQ1 Gain
5band EQ2 Gain
5band EQ3 Gain
5band EQ4 Gain
5band EQ5 Gain
R/W
Default
D7
0
0
0
0
0
R
0
D6
0
0
0
0
0
R
0
D5
5EQ1G5
5EQ2G5
5EQ3G5
5EQ4G5
5EQ5G5
R/W
0
D4
5EQ1G4
5EQ2G4
5EQ3G4
5EQ4G4
5EQ5G4
R/W
1
D3
5EQ1G3
5EQ2G3
5EQ3G3
5EQ4G3
5EQ5G3
R/W
1
D2
5EQ1G2
5EQ2G2
5EQ3G2
5EQ4G2
5EQ5G2
R/W
0
D1
5EQ1G1
5EQ2G1
5EQ3G1
5EQ4G1
5EQ5G1
R/W
0
D0
5EQ1G0
5EQ2G0
5EQ3G0
5EQ4G0
5EQ5G0
R/W
0
5EQ1G5-0: 5-band Equalizer 1 Gain Setting
Default: 18H (0dB)
5EQ2G5-0: 5-band Equalizer 2 Gain Setting
Default: 18H (0dB)
5EQ3G5-0: 5-band Equalizer 3 Gain Setting
Default: 18H (0dB)
5EQ4G5-0: 5-band Equalizer 4 Gain Setting
Default: 18H (0dB)
5EQ5G5-0: 5-band Equalizer 5 Gain Setting
Default: 18H (0dB)
EQ gain: +12dB(00H) ~ -12dB(30H), 0.5dB step
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Addr Register Name
70H DRC Mode Control
R/W
Default
D7
0
R
0
D6
DLMAT2
R/W
0
D5
DLMAT1
R/W
0
D4
DLMAT0
R/W
0
D3
D2
DRGAIN1
DRGAIN0
R/W
0
D1
DRCC1
R/W
0
D0
DRCC0
R/W
0
R/W
0
D3
0
R
0
D2
NSLPF
R/W
0
D1
NSHPF
R/W
0
D0
NSCE
R/W
0
DRCC1-0: DRC Enable (Table 65)
00: Disable (default)
01: Low
10: Middle
11: High
When DRCC1-0 bits are “00”, DRC is through (0dB).
DRGAIN1-0: DRC Recovery Speed Setting (Table 67)
Default: “00”
DLMAT2-0: DRC ATT Speed Setting (Table 66)
Default: “000”
Addr Register Name
71H NS Control
R/W
Default
D7
0
R
0
D6
0
R
0
D5
DRCM1
R/W
0
D4
DRCM0
R/W
0
NSCE: Noise Suppression Enable
0: Disable (default)
1: Enable
When NSCE bit is “0”, Noise Suppression is through (0dB).
NSHPF: HPF for Noise Suppression Coefficient Setting Enable
0: Disable (default)
1: Enable
When NSHPF bit is “1”, the settings of NSHA13-0 and NSHB13-0 bits are enabled. When NSHPF bit is “0”,
HPF block is through (0dB).
NSLPF: LPF for Noise Suppression Coefficient Setting Enable
0: Disable (default)
1: Enable
When NSLPF bit is “1”, the settings of NSLA13-0 and NSLB13-0 bits are enabled. When NSLPF bit is “0”,
LPF block is through (0dB).
DRCM1-0: DRC Input Signal Setting (Table 41)
Default: “00” (L = Lch, R = Rch)
Addr Register Name
72H NS Gain & ATT Control
R/W
Default
D7
0
R
0
D6
D5
D4
NSGAIN2
NSGAIN1
NSGAIN0
R/W
0
R/W
0
R/W
1
D3
0
R
0
D2
NSATT2
R/W
0
D1
D0
NSATT1 NSATT0
R/W
R/W
0
1
NSATT2-0: Noise Suppression ATT Speed Setting (Table 45)
Default: “001”
NSGAIN2-0: Noise Suppression Recovery Speed Setting (Table 48)
Default: “001”
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Addr Register Name
73H NS On Level
R/W
Default
D7
NSIAF1
R/W
1
D6
NSIAF0
R/W
0
D5
0
R
0
D4
NSTHL4
R/W
0
D3
D2
D1
NSTHL3 NSTHL2 NSTHL1
R/W
R/W
R/W
0
0
0
D0
NSTHL0
R/W
0
NSTHL4-0: Noise Suppression Threshold Low Level Setting (Table 43)
Default: “00H” (-36dB)
NSIAF1-0: Moving Average Parameter Setting at Noise Suppression Off (Table 42)
Default: “10” (1024/fs)
Addr Register Name
74H NS Off Level
R/W
Default
D7
NSOAF1
R/W
1
D6
NSOAF0
R/W
0
D5
0
R
0
D4
NSTHH4
R/W
0
D3
D2
D1
NSTHH3 NSTHH2 NSTHH1
R/W
R/W
R/W
0
0
0
D0
NSTHH0
R/W
0
NSTHH4-0: Noise Suppression Threshold High Level Setting (Table 47)
Default: “00H” (-36dB)
NSOAF1-0: Moving Average Parameter Setting at Noise Suppression On (Table 46)
Default: “10” (16/fs)
Addr Register Name
75H NS Reference Select
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
NSREF3
R/W
0
D2
NSREF2
R/W
0
D1
NSREF1
R/W
0
D0
NSREF0
R/W
0
D3
D2
NSLA3
NSLA2
NSLA11 NSLA10
NSLB3
NSLB2
NSLB11 NSLB10
NSHA3 NSHA2
NSHA11 NSHA10
NSHB3
NSHB2
NSHB11 NSHB10
R/W
R/W
D1
NSLA1
NSLA9
NSLB1
NSLB9
NSHA1
NSHA9
NSHB1
NSHB9
R/W
D0
NSLA0
NSLA8
NSLB0
NSLB8
NSHA0
NSHA8
NSHB0
NSHB8
R/W
NSREF3-0: Reference Value at Noise Suppression (Table 44)
Default: “0H” (-9dB)
Addr
76H
77H
78H
79H
7AH
7BH
7CH
7DH
Register Name
NS LPF Co-efficient 0
NS LPF Co-efficient 1
NS LPF Co-efficient 2
NS LPF Co-efficient 3
NS HPF Co-efficient 0
NS HPF Co-efficient 1
NS HPF Co-efficient 2
NS HPF Co-efficient 3
R/W
D7
NSLA7
0
NSLB7
0
NSHA7
0
NSHB7
0
R/W
D6
NSLA6
0
NSLB6
0
NSHA6
0
NSHB6
0
R/W
D5
NSLA5
NSLA13
NSLB5
NSLB13
NSHA5
NSHA13
NSHB5
NSHB13
R/W
D4
NSLA4
NSLA12
NSLB4
NSLB12
NSHA4
NSHA12
NSHB4
NSHB12
R/W
NSLA13-0, NSLB13-0: Noise Suppression LPF Coefficient (14bit x 2)
Default: “0000H”
NSHA13-0, NSHB13-0: Noise Suppression HPF Coefficient (14bit x 2)
Default: “0000H”
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Addr
80H
Register Name
DVLC Filter Select
R/W
Default
D7
DLLPF1
R/W
0
D6
DLLPF0
R/W
0
D5
DMHPF1
R/W
0
D4
DMHPF0
R/W
0
D3
DMLPF1
R/W
0
D2
D1
D0
DMLPF0 DHHPF1 DHHPF0
R/W
R/W
R/W
0
0
0
DHHPF1-0: DVLC High Frequency Range HPF Coefficient Setting Enable (Table 58)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DHHPF1-0 bits are “01” or “10”, the settings of DHHA13-0 and DHHB13-0 bits are enabled. When
DHHPF1-0 bits are “00”, HPF block outputs “0” data.
DMLPF1-0: DVLC Middle Frequency Range LPF Coefficient Setting Enable (Table 54)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DMLPF1-0 bits are “01” or “10”, the settings of DMLA13-0 and DMLB13-0 bits are enabled. When
DMLPF1-0 bits are “00”, LPF block of DVLC middle frequency range is through (0dB).
DMHPF1-0: DVLC Middle Frequency Range HPF Coefficient Setting Enable (Table 53)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DMHPF1-0 bits are “01” or “10”, the settings of DMHA13-0 and DMHB13-0 bits are enabled. When
DMHPF1-0 bits are “00”, HPF block of DVLC middle frequency range is through (0dB).
DLLPF1-0: DVLC Low Frequency Range LPF Coefficient Setting Enable (Table 49)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DLLPF1-0 bits are “01” or “10”, the settings of DLLA13-0 and DLLB13-0 bits are enabled. When
DLLPF1-0 bits are “00”, LPF block outputs “0” data.
Addr
81H
Register Name
DVLC Mode Control
R/W
Default
D7
D6
D5
DVRGAIN2
DVRGAIN1
DVRGAIN0
R/W
0
R/W
1
R/W
1
D4
D3
D2
DVLMAT2 DVLMAT1 DVLMAT0
R/W
0
R/W
1
R/W
1
D1
DAF1
R/W
1
D0
DAF0
R/W
1
DAF1-0: Moving Average Parameter Setting for DVLC (Table 62)
Default: “11” (Default: 2048/fs)
DVLMAT2-0: DVLC ATT Speed Setting (Table 63)
Default: “011”
DVRGAIN2-0: DVLC Recovery Speed Setting (Table 64)
Default: “011”
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[AK4679]
Addr
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
Register Name
DVLCL Curve X1
DVLCL Curve Y1
DVLCL Curve X2
DVLCL Curve Y2
DVLCL Curve X3
DVLCL Curve Y3
DVLCL Slope 1
DVLCL Slope 2
DVLCL Slope 3
DVLCL Slope 4
DVLCM Curve X1
DVLCM Curve Y1
DVLCM Curve X2
DVLCM Curve Y2
DVLCM Curve X3
DVLCM Curve Y3
DVLCM Slope 1
DVLCM Slope 2
DVLCM Slope 3
DVLCM Slope 4
DVLCH Curve X1
DVLCH Curve Y1
DVLCH Curve X2
DVLCH Curve Y2
DVLCH Curve X3
DVLCH Curve Y3
DVLCH Slope 1
DVLCH Slope 2
DVLCH Slope 3
DVLCH Slope 4
R/W
Default
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
D6
0
0
0
0
0
0
L1G6
L2G6
L3G6
L4G6
0
0
0
0
0
0
M1G6
M2G6
M3G6
M4G6
0
0
0
0
0
0
H1G6
H2G6
H3G6
H4G6
R/W
0
D5
VL1X5
VL1Y5
VL2X5
VL2Y5
0
0
L1G5
L2G5
L3G5
L4G5
VM1X5
VM1Y5
VM2X5
VM2Y5
0
0
M1G5
M2G5
M3G5
M4G5
VH1X5
VH1Y5
VH2X5
VH2Y5
0
0
H1G5
H2G5
H3G5
H4G5
R/W
0
D4
VL1X4
VL1Y4
VL2X4
VL2Y4
VL3X4
VL3Y4
L1G4
L2G4
L3G4
L4G4
VM1X4
VM1Y4
VM2X4
VM2Y4
VM3X4
VM3Y4
M1G4
M2G4
M3G4
M4G4
VH1X4
VH1Y4
VH2X4
VH2Y4
VH3X4
VH3Y4
H1G4
H2G4
H3G4
H4G4
R/W
0
D3
VL1X3
VL1Y3
VL2X3
VL2Y3
VL3X3
VL3Y3
L1G3
L2G3
L3G3
L4G3
VM1X3
VM1Y3
VM2X3
VM2Y3
VM3X3
VM3Y3
M1G3
M2G3
M3G3
M4G3
VH1X3
VH1Y3
VH2X3
VH2Y3
VH3X3
VH3Y3
H1G3
H2G3
H3G3
H4G3
R/W
0
D2
VL1X2
VL1Y2
VL2X2
VL2Y2
VL3X2
VL3Y2
L1G2
L2G2
L3G2
L4G2
VM1X2
VM1Y2
VM2X2
VM2Y2
VM3X2
VM3Y2
M1G2
M2G2
M3G2
M4G2
VH1X2
VH1Y2
VH2X2
VH2Y2
VH3X2
VH3Y2
H1G2
H2G2
H3G2
H4G2
R/W
0
D1
VL1X1
VL1Y1
VL2X1
VL2Y1
VL3X1
VL3Y1
L1G1
L2G1
L3G1
L4G1
VM1X1
VM1Y1
VM2X1
VM2Y1
VM3X1
VM3Y1
M1G1
M2G1
M3G1
M4G1
VH1X1
VH1Y1
VH2X1
VH2Y1
VH3X1
VH3Y1
H1G1
H2G1
H3G1
H4G1
R/W
0
D0
VL1X0
VL1Y0
VL2X0
VL2Y0
VL3X0
VL3Y0
L1G0
L2G0
L3G0
L4G0
VM1X0
VM1Y0
VM2X0
VM2Y0
VM3X0
VM3Y0
M1G0
M2G0
M3G0
M4G0
VH1X0
VH1Y0
VH2X0
VH2Y0
VH3X0
VH3Y0
H1G0
H2G0
H3G0
H4G0
R/W
0
VL1X5-0, VL2X5-0, VL3X4-0: Input Gain Setting for Low Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
VL1Y5-0, VL2Y5-0, VL3Y4-0: Output Gain Setting for Low Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
L1G6-0, L2G6-0, L3G6-0, L4G6-0: DVLC Slope Setting for Low Range (Table 52)
Default: “00H”
VM1X5-0, VM2X5-0, VM3X4-0: Input Gain Setting for Middle Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
VM1Y5-0, VM2Y5-0, VM3Y4-0: Output Gain Setting for Middle Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
M1G6-0, M2G6-0, M3G6-0, M4G6-0: DVLC Slope Setting for Middle Range (Table 52)
Default: “00H”
VH1X5-0, VH2X5-0, VH3X4-0: Input Gain Setting for High Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
VH1Y5-0, VH2Y5-0, VH3Y4-0: Output Gain Setting for High Range DVLC Point (Table 50, Table 51)
Default: “00H” (0dB)
H1G6-0, H2G6-0, H3G6-0, H4G6-0: DVLC Slope Setting for High Range (Table 52)
Default: “00H”
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Addr
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
Register Name
DVLCL LPF Co-efficient 0
DVLCL LPF Co-efficient 1
DVLCL LPF Co-efficient 2
DVLCL LPF Co-efficient 3
DVLCM HPF Co-efficient 0
DVLCM HPF Co-efficient 1
DVLCM HPF Co-efficient 2
DVLCM HPF Co-efficient 3
DVLCM LPF Co-efficient 0
DVLCM LPF Co-efficient 1
DVLCM LPF Co-efficient 2
DVLCM LPF Co-efficient 3
DVLCH HPF Co-efficient 0
DVLCH HPF Co-efficient 1
DVLCH HPF Co-efficient 2
DVLCH HPF Co-efficient 3
R/W
D7
DLLA7
0
DLLB7
0
DMHA7
0
DMHB7
0
DMLA7
0
DMLB7
0
DHHA7
0
DHHB7
0
R/W
D6
DLLA6
0
DLLB6
0
DMHA6
0
DMHB6
0
DMLA6
0
DMLB6
0
DHHA6
0
DHHB6
0
R/W
D5
DLLA5
DLLA13
DLLB5
DLLB13
DMHA5
DMHA13
DMHB5
DMHB13
DMLA5
DMLA13
DMLB5
DMLB13
DHHA5
DHHA13
DHHB5
DHHB13
R/W
D4
D3
D2
DLLA4
DLLA3
DLLA2
DLLA12 DLLA11 DLLA10
DLLB4
DLLB3
DLLB2
DLLB12 DLLB11 DLLB10
DMHA4 DMHA3 DMHA2
DMHA12 DMHA11 DMHA10
DMHB4
DMHB3
DMHB2
DMHB12 DMHB11 DMHB10
DMLA4
DMLA3
DMLA2
DMLA12 DMLA11 DMLA10
DMLB4
DMLB3
DMLB2
DMLB12 DMLB11 DMLB10
DHHA4
DHHA3
DHHA2
DHHA12 DHHA11 DHHA10
DHHB4
DHHB3
DHHB2
DHHB12 DHHB11 DHHB10
R/W
R/W
R/W
D1
DLLA1
DLLA9
DLLB1
DLLB9
DMHA1
DMHA9
DMHB1
DMHB9
DMLA1
DMLA9
DMLB1
DMLB9
DHHA1
DHHA9
DHHB1
DHHB9
R/W
D0
DLLA0
DLLA8
DLLB0
DLLB8
DMHA0
DMHA8
DMHB0
DMHB8
DMLA0
DMLA8
DMLB0
DMLB8
DHHA0
DHHA8
DHHB0
DHHB8
R/W
DLLA13-0, DLLB13-0: DVLC Low Frequency Range LPF Coefficient (14bit x 2)
Default: “0000H”
DMHA13-0, DMHB13-0: DVLC Middle Frequency Range HPF Coefficient (14bit x 2)
Default: “0000H”
DMLA13-0, DMLB13-0: DVLC Middle Frequency Range LPF Coefficient (14bit x 2)
Default: “0000H”
DHHA13-0, DHHB13-0: DVLC High Frequency Range HPF Coefficient (14bit x 2)
Default: “0000H”
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■ Register Map (DSP block)
The DSP block control register settings are executed through a microcontroller interface. All registers below are
initialized by the power down (PDNE pin = “L”). To ensure control register settings, this power-down (PDNE pin= “L”)
must always be made when power up the AK4679.
Control register settings should be made during DSP reset (DSPRSTN bit = “0”).
Name
D7
D6
D5
D4
D3
D2
D1
D0
PCONT0
0
0
0
SOCFG
0
0
0
PWSW
PCONT1
0
0
0
0
0
0
0
MRSTN
Name
D7
D6
D5
D4
D3
D2
D1
D0
CONT0
FSD[3]
FSD[2]
FSD[1]
FSD[0]
0
0
0
0
CONT1
LAW[1]
LAW[0]
DIFD[1]
BCKPD
0
TESTB
TESTA
CONT2
BANK[3]
BANK[2]
BANK[1]
LOCKE
CRCE
WDTN
EFEN
DRMS[1]
DRMS[0]
DRAD[0]
0
WAVP1[1]
LPDO3
LPDO2
DIFD[0]
BANK[0
]
DRAD[1
]
LPDO1
SELDO4
SELDO3
PT2N
WAVP1[0
]
SELPT
0
STRDY
0
0
0
0
0
0
CONT4
POMOD
E
LPDO4
CONT5
OUT4N
OUT3N
OUT2N
OUT1N
0
CONT6
0
0
DLRDY
0
0
CONT7
SYDET
CGLK
0
0
0
0
DSPRST
N
0
CONT8
TESTC
0
0
0
0
0
CONT3
Note 83. The bits defined as 0 must set a “0” value.
Note 84. Default value is the value after power-down release.
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Power Control: Internal Power Supply Control
PCONT0: Internal power supply control
Register
Address
W
D0h
R
50h
Register Name
PCONT0
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
SOCFG
R/W
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
PWSW
R/W
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
MRSTN
R/W
0
PWSW bit: Internal power supply switch control
0: power control SW off (default)
1: power control SW on
SOCFG: SO pin configuration (this bit is valid for I2C pin = “L”)
0: CMOSL (default)
1: Wired ‘OR’ (Hi-impedance)
Register
Address
W
D1h
R
51h
Register Name
PCONT1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
MRSTN: Internal power supply reset control
0: Reset state (Default)
1: Reset Released
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Device Control Register
CONT0: Initial Setting1
Register
Address
W
C0h
R
40h
Register Name
CONT0
R/W
Default
D7
R/W
0
D6
D5
FSD[3:0]
R/W
R/W
0
0
D4
R/W
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
0
R
0
D3
BCKPD
R/W
0
D2
0
R
0
D1
TESTB
R
0
D0
TESTA
R
0
FSD3-0: Sampling Frequency Select (Table 6)
00: fs1=fs2=8kHz (default)
Write “0” into the “0” registers.
CONT1: Initial Setting 2
Register
Address
W
C1h
R
41h
Register Name
CONT1
R/W
Default
D7
D6
LAW[1:0]
R/W
R/W
0
0
D5
D4
DIFD[1:0]
R/W
R/W
0
0
LAW[1:0]: PCM I/F Port#1 Data Format (Table 125)
00:16 bit Linear (default)
DIFD[1:0]: PCM I/F Port#1 SYNC Format Setting (Table 126)
00: PCM Short Frame (default)
BCKPD: PCM Format BCLK Edge Select (Table 124)
0: Falling Edge (default)
1: Rising Edge
TESTB, TESTA: Must write “0” into these bits.
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CONT2: Initial Setting 3
Register
Address
W
C2h
R
42h
Register Name
CONT2
R/W
Default
D7
R/W
0
D6
D5
BANK[3:0]
R/W
R/W
0
0
D4
R/W
0
D3
LOCKE
R/W
0
D2
CRCE
R/W
0
D1
WDTN
R/W
0
D0
EFEN
R/W
0
BANK[3:0]: DSP DLRAM Mode Setting
DLRAM
Partition
Mode
0
1
2
3
4
5
6
7
8
Bank0
BANK [3:0]
Bit
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
9
10
11
12
13
14
15
1001b
1010b
1011b
1100b
1101b
1110b
1111b
DSP Delay RAM
Bank1
Ring 20.4f
Linear 20.4f
16384 words
14336 words
12288 words
10240 words
8192 words
6144 words
4096 words
2048 words
0
0
2048 words
4096 words
6144 words
8192 words
10240 words
12288 words
14336 words
16384 words
10240 words
8192 words
6144 words
4096 words
2048 words
0
0
2048 words
4096 words
6144 words
8192 words
10240 words
N/A
Bank2
Linear 8bit
μ-law codec
0
0
0
0
0
0
0
0
0
(default)
18432words
18432words
18432words
18432words
18432words
18432words
(N/A: Not available)
LOCKE: Clock Generator Unit Lock Error status selects (Table 129)
0: lock status monitor invalid (default)
1: lock status monitor Enable
CRCE: DSP CRC status selects (Table 129)
0: CRC status monitor invalid (default)
1: CRC status monitor enable
WDTN: WDT Disable Switch of DSP (Table 129)
0: WDT Enable (default)
1: WDT Disable
EFEN: Extended Instruction Enable of DSP
0: Valid (default)
1: Invalid
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CONT3: DSP Setting 1
Register
Address
W
C3h
R
43h
Register Name
CONT3
R/W
Default
D7
POMODE
R/W
0
D6
D5
DRMS[1:0]
R/W
R/W
0
0
D4
D3
DRAD[1:0]
R/W
R/W
0
0
D2
0
R
0
D1
D0
WAVP[1:0]
R/W
R/W
0
0
POMODE1: DLYRAM Pointer 0 Select
0: OFREG (default)
1: DBUS Immediate Data
DRAM: DATA RAM Size Setting
DSP Data RAM
DRAM
Mode
0
1
2
others
DRMS[1:0]
Bit
00
01
10
others
Bank1
Memory size
[words]
512
1024
1536
Bank0
Memory size
[words]
1536
1024
512
(default)
N/A
(N/A: Not available)
Addressing Mode Setting bit [1:0]
DSP Data RAM
Addressing
mode
DRAD
Pointer
0
1
2
3
00
01
10
11
Bank1
DP1
Ring
Ring
Linear
Linear
Bank0
DP0
Ring
Linear
Ring
Linear
WAVP[1:0]: CRAM Memory Assignment of DSP
WAVP Mode WAVP[1] WAVP[0]
0
0
0
33word
1
0
1
65word
2
1
0
129word
3
1
1
257word
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FFT point
128
256
512
1024
(default)
(default)
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CONT4: DSP Setting 2
Register
Address
W
C4h
R
44h
Register Name
CONT4
R/W
Default
D7
LPDO4
R/W
0
D6
LPDO3
R/W
0
D5
LPDO2
R/W
0
D4
LPDO1
R/W
0
D3
SELDO4
R/W
0
D2
SELDO3
R/W
0
D1
PT2N
R/W
0
D0
SELPT
R/W
0
LPDO4: SDOUT4 Signal Select (Figure 109) Valid when OUT4N bit = “0”
0: SDIN3 to SDOUT4 (default)
1: DSP DOUT4 to SDOUT4 pin
LPDO3: SDOUT3 Signal Select (Figure 109) Valid when OUT3N bit = “0”
0: SDIN4 to SDOUT3 (default)
1: DSP DOUT3 to SDOUT3 pin
LPDO2: SDOUT2 Signal Select (Figure 109) Valid when OUT2N bit = “0”
0: SDIN1 to SDOUT2 (default)
1: DSP DOUT2 to SDOUT2 pin
LPDO1: SDOUT1 Signal Select (Figure 109) Valid when OUT1N bit = “0”
0: SDIN2 pin to SDOUT1 pin (default)
1: DSP DOUT1 to SDOUT1 pin
SELDO4: SDOUT4/GP1 pin Signal Select (Table 131)
0: DSP DOUT4 Output (default)
1: DSP GP Output 1
SELDO3: SDOUT3/GP0 Signal Select (Table 130)
0: DSP DOUT3 Output (default)
1: DSP GP Output 1
PT2N: Port#2 Output Enable (Figure 108)
0: Enable (default)
1: Disable (BCLK2 and SYNC2 pin output Low level)
SELPT: Port Select of Port #2 Output (Figure 108)
0: Port#1 (SYNC1, BCLK1) (default)
SYNC3/JX1 and BCLK3/JX0 pins can be used as JX1 and JX0 pins respectively.
1: Port#3 (SYNC3, BCLK3)
437H
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CONT5: Signal Setting 1
Register
Address
W
C5h
R
45h
Register Name
CONT5
R/W
Default
D7
OUT4N
R/W
0
D6
D5
D4
OUT3N
OUT2N
OUT1N
R/W
0
R/W
0
R/W
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
STRDY
R/W
0
OUT4N: SDOUT4 pin output enable (active low)
0: SDOUT4 Output Enable (default)
1: SDOUT4 pin = “L”
OUT3N: SDOUT3 pin output enable (active low)
0: SDOUT3 Output Enable (default)
1: SDOUT3 pin = “L”
OUT2N: SDOUT2 pin output enable (active low)
0: SDOUT2 Output Enable (default)
1: SDOUT2 pin = “L”
OUT1N: SDOUT1 pin output enable (active low)
0: SDOUT1 Output Enable (default)
1: SDOUT1 pin = “L”
STRDY: STO/RDY pin select
0: STO Output (default)
1: RDY Output
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CONT6: Signal Setting 2
Register
Address
W
C6h
R
46h
Register Name
CONT6
R/W
Default
D7
0
R
0
D6
0
R
0
D5
DLRDY
R/W
0
D4
0
R
0
D3
0
R
0
D2
DSPRSTN
R/W
0
D1
0
R
0
D0
0
R
0
DLRDY: DSP Download Preparation
0: download inhibit (default)
1: download ready
This bit is used when start to download the DSP programs. The bit must be cleared after downloading
programs are completed.
DSPRSTN: DSP Reset
0: DSP Reset (default)
1: DSP Reset Release
CONT7: State Signal (Read only)
Register
Address
W
C7h
R
47h
Register Name
CONT7
R/W
Default
D7
SYDET
R
0
D6
CGLK
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
0
R
0
D1
0
R
0
D0
0
R
0
DSP status output from the wait sync state to operational state (Run State)
SYDET: SYNC Signal Detection flag
0: No SYNC1 pin Signal (Low or High fixed) (default)
1: SYNC1 pin Signal Detect
This bit outputs DSP status in Wait Sync State until DSP Operational state (RUN).
CGLK: Clock Generator Unit Lock Status
0: Clock Generator Unlocked State (default)
1: Clock Generator Locked State
CONT8: Initial Setting 4
Register
Address
W
C8h
R
48h
Register Name
CONT8
R/W
Default
D7
TESTC
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
TESTC bit must be set “1”. (i.e. set the 80h value in this register)
The TESTC bit is set after writing the power control register with the power suplly on.
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■ Command Code map for the DSP
1. Command Code
BIT7
R/W flag
BIT6
BIT5
BIT4
Area to be accessed
BIT3
BIT2
BIT1
BIT0
Accompanying data to the access area
R/W Flag
Write at “1”, Read at “0”.
Access data and accompanying data
BIT6
BIT5
BIT4 BIT3~0
0
0
0
Number of Write
0
0
1
Number of Write
0
1
0
0100
0010
1000
0
1
1
0100
0010
1
0
0
Register Address
1
0
1
Register Address
1
1
0
0000
1
1
1
0000
0010
0100
0110
1000
1010
1100
Write preparation to CRAM during RUN
Write preparation to OFREG during RUN
Write operation to CRAM during RUN
Write operation to OFREG during RUN
Write operation to PRAM during DSP reset
Write operation to CRAM during DSP reset
Write operation to OFREG during DSP reset
Internal control registers 00h~08h
System power registers 00h~01h
Device Identification (Read only)
Error Status Read
CRC Write/Read
Write operation of JX code
Read operation from MIR1
Read operation from MIR2
Read operation from MIR3
Read operation from MIR4
2. Address
Address description is always LSB justified. Accessing command code BIT[6:4]= “000” to “011” requires 16bit address.
Accessing command code BIT[6:4]= “100” to “111” requires no address.
3. Data
Length of write data is depending on the writing area size. When accessing RAM, data may be written to sequential
address locations by writing data continuously.
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■ Write
Command
Code
0x80~0x8F
Address
Data Length
16bit
24bit×n
0x90~0x9F
16bit
24bit×n
0xA2
0xA4
0xB2
0xB4
0xB8
0xC0~0xC8
0xD0~0xD
1
0xF2
0xF4
16bit
16bit
16bit
16bit
16bit
None
None
None
None
24bit×n
24bit×n
40bit×n
8bit
8bit
None
None
16bit
8bit
Description
Write preparation to CRAM during RUN.
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
Write preparation to OFREG during RUN
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
Write operation to OFREG during RUN. 0 address should be written.
Write operation to CRAM during RUN. 0 address should be written.
Write operation to OFREG during DSP reset
Write operation to CRAM during DSP reset
Write operation to PRAM during DSP reset
Write operation to Register 0h~8h (except 7h)
System Power Supply Registers 0h~1h Write
CRC Write
Write operation of DSP JX code
Data length is defined by the command code which specifies the area to be accessed. When accessing RAM, data may be
read from sequential address locations by reading data continuously. Writing other than the above-mentioned command
code is prohibited.
Table 132. List of Usable Command Codes in Write Sequence
■ Read
Command
Code
0x24
0x32
0x34
0x38
0x40~0x48
0x50~0x 51
0x60
0x70
0x72
0x76
Address
16bit
16bit
16bit
16bit
None
None
None
None
None
None
Data
Length
24bit×n
24bit×n
24bit×n
40bit×n
8bit
8bit
8bit
8bit
16bit
32bit
Description
CRAM/OFREG Write preparation data Read during RUN
Read operation form OFREG during DSP reset
Read operation from CRAM during DSP reset
Read operation from PRAM during DSP reset
Read operation from Register 0h~8h
Read operation from System Power Supply Register 0h~1h
Device Identification
DSP Error Status Read
CRC result Read
Read operation from MIR1
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x78
None
32bit
Read operation from MIR2
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x7A
None
32bit
Read operation from MIR3
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x7C
None
32bit
Read operation from MIR4
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Reading other than the above-mentioned command code is prohibited.
Table 133. List of Usable Command Codes in Read Sequence
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■ Command Format
DLRDY bit must be set “1” when the PRAM, CRAM, OFFREG will access on the sleep state.
1. Write Operation during DSP Reset
1-1. Program RAM (PRAM) Write (during DSP Reset)
Field
Write data
(1) COMMAND Code 0xB8
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
426H38
1-2. Coefficient RAM (CRAM) Write (during DSP Reset)
Field
Write data
(1) COMMAND Code 0xB4
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Two bytes of data may be written continuously for each address.
1-3. Offset REG (OFREG) Write (during DSP Rest)
Field
Write data
(1) COMMAND Code 0xB2
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 0 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 D14 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
2. Write Operation during DSP Reset (DLRDY bit = “1”) and RUN
2-1. Control Register Write (during DSP reset and RUN)
Field
Write data
(1) COMMAND Code 0xC0~0xC8
(2) DATA
D7~D0
Note 85. Write operation may be limited depending on register settings. (C7: read only register)
2-2. System Power Supply Register Write (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0xD0~0xD1
(2) DATA
D7~D0
Note 86. Write operation may be limited depending on register settings.
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2-3. External Conditional Jump Code Write (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0xF4
(2) DATA
D7~D0
2-4. CRC Code Write (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0xF2
(2) DATA
D15~D8
(3) DATA
D7~D0
3. Write Operation during RUN
3-1. Coefficient RAM (CRAM) Write Preparation (during Run)
Preparation
Write data
(1) COMMAND Code 0x80~0x8F (one data at 80h, sixteen data at 8Fh)
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Three bytes of data may be written continuously for each address.
3-2. Coefficient RAM (CRAM) Write Operation (during RUN)
Execute
Write data
(1) COMMAND Code 0xA4
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 87. The COMMAND determines the length of the data. If the written data exceeds the allotted amount, the
excess data is ignored.
3-3. Offset REG (OFREG) Write Preparation (during RUN)
Preparation
Write data
(1) COMMAND Code 0x90~0x9F (one data at 0x90, sixteen data at 0x9F)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 0 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 D14 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
3-4. Offset REG (OFREG) Write Operation (during RUN)
Execute
Write data
(1) COMMAND Code 0xA2
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 88. The COMMAND determines the length of the data. If the written data exceeds the allotted amount, the
excess data is ignored.
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4. Read Operation (DLRDY bit = “1”)
4-1. Program RAM (PRAM) Read (during DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x38
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
4-2. Coefficient RAM (CRAM) Read (during DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x34
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Three bytes of data may be written continuously for each address.
4-3. Offset REG (OFREG) Read (DSP Reset)
Field
Write data
Readout data
(1) COMMAND Code 0x32
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 0 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 D14 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
5. Read Operation (DLRDY bit = “1” and RUN state)
5-1. Control Register Read (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0x40~0x47h
(2) DATA
D7~D0
Readout data
5-2. System Power Supply Register Read (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0x50~0x51
(2) DATA
D7~D0
5-3. Device Identification (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0x60
(2) DATA
MS1402-E-06
Readout data
Readout data
D7
0
D6
0
D5
0
1
D4
1
D3
1
D2
0
9
D1
0
D0
1
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5-4. CRC Code Reading (during DSP Reset and RUN)
Field
Write data
(1) COMMAND Code 0x72
(2) DATA1
D15~D8
(3) DATA2
D7~D0
Readout data
5-5. Error and GPO statuses Reading (DSP Reset and RUN)
Field
Write data
Output
(1) COMMAND Code 0x70
(2) DATA
Active low output
D7: CRCERRN
0: CRC error
D6: WDTERRN
0: Watch Dog Timer error
D5: CGERRN
0: Clock Generator unit lock error
D4: GP0
0: clear
1: set
D3: GP1
0: clear
1: set
6. Read Operation during RUN
6-1. CRAM Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
Readout data
A15~A8
A8~A0
D19~D12
D11~D4
D3~D0 0 0 0 0
6-2. OFREG Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A8~A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12~D8
(6) DATA3
D7~D0
6-3. MIR1/2/3/4 Read (during RUN)
Field
Write data
(1) COMMAND Code 0x76(MIR1)
0x78(MIR2)
0x7A(MIR3)
0x7C(MIR4)
(2) DATA1
(3) DATA2
(4) DATA3
(5) DATA4
Note 89. Data is valid only when all flags are zero.
Readout data
Readout data
D27~D20
D19~D12
D11~D4
D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)
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7. Timing
7-1. RAM Writing Timing during DSP Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in the order
of command code, address and data. The PRAM start address is fixed to 0h. When writing the data to consecutive
address locations, continue to input data only. PRAM address is incremented by 1 automatically.
DSPRSTN bit = “0”
CSN
DLRDY bit = “1”
SCLK
don’t care
(L/H)
SI
Command
Address
DATA
DATA
Address[n]
DATA
DATA
DATA
don’t care
(L/H)
Address[n+1]
RDY = “H”
Figure 138. Writing to RAM at Consecutive Address Locations
When writing data at specified address locations, set the CSN pin to “L” from “H” and then input command code, address
and data in this order.
DSPRSTN bit = “0”
CSN
DLRDY bit
SCLK
SI
don’tcare
(L/H)
Command
Address DATA
don’tcare
(L/H)
Command
Address DATA
don’tcare
(L/H)
RDY = “H”
Figure 139. Writing to RAM at specified Address Locations
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7-2. RAM Writing Timing during RUN
These operations are to rewrite Coefficient RAM (CRAM) and Offset REG (OFREG) during RUN. Data writing is
executed in 2step; write preparation and write execution. The writing data can be confirmed by reading write preparation
data.
1. Write Preparation
After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the starting
address of write (16-bit all 0) and the number of data assigned by command code in this order.
2. Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this order by write
preparation data confirmation command “24h”. The data will be “0x000001” when reading more than write
preparation data. Execute write preparation again when the address and data are garbled by external noise.
3. Write Execution
Upon completion of this operation, execute RAM write during RUN by inputting the corresponding command code
and address (16-bit all “0”) in this order.
Note 90. Execute Write preparation before a write execution. When writing to RAM without write preparation
sequence, a malfunction occurs. Access operation by microcontroller is prohibited until RDY changes to
“H”.
Write modification of RAM contents is executed whenever the RAM address for modification is assigned. For
example, when 5 Data are written, from RAM address “10”, it is executed as shown below.
RAM execution address
7
8
9
Write execution position
10
↓
○
11
↓
○
13
16
11
↑
12
↓
○
13
↓
○
14
↓
○
15
Note: Address “13” is not executed until rewriting address “12”.
DSPRSTN bit= “1”
CSN
(Ex.) When # of DATA is 4
CRAM Command Code0x83
OFREG Command Code 0x93
SCLK
SI
don ’tcare
(L/H )
Command
Code
Address DATA0
CRAM
DATA1
DATAn-1 DATAn
do n’tcare
(L/H)
0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG 0x90(# of DATA: 1)~0x9F(# DATA: 16)
Figure 140. CRAM/OFREG Write Preparation
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DSPRSTN bit= “1”
CSN
SCLK
don’t car e
(L/H)
SI
0x24
Hi-Z or Low
SO
don’ t care
(L/H )
Address
DATA
DATA
DATA
DATA
DATA
Figure 141. CRAM/OFREG Write Preparation Confirm
DSPRSTN bit= “1”
CSN
SCLK
SI
don’t care
(L/H)
Command Code
00000000
00000000
CRAM0xA4, OFREG0xA2
Figure 142. CRAM/OFREG Write
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7-3. External Conditional Jump
External Conditional Jump Code Writing (during DSP Reset and RUN)
(1) COMMAND
0xF4
(2) DATA
D7~D0
External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the designated
register on the rising edge of SYNC. The RDY pin changes to “L” when the command code is transferred, and it
changes to “H” when write operations are completed. When any single bit of “1” data in 8-bit External Jump code
matches an “1” bit data in the IFCON field, a Jump instruction is executed. Then, the RDY pin changes to “H” when
the rise of SYNC is captured. Access operation by microcontroller is prohibited until the RDY pin changes to “H”.
IFCON field is the area where the external conditions are written. This Jump code is reset to 00h by setting the IRSTN
pin to “L”, but it is not reset by DSP Reset.
4 3
2 1
0
■ ■
■ ■
■
↑
Check if “1” of IFCON field corresponds with External Condition Jump Code including Jump pins by at least
one at the same location.
7
↓
0
IFCON Field
♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦
External Conditional Jump Code
7
■
6
■
5
■
DSPRSTN bit
SCLK
SI
don’tcare
(L/H)
F4h
D7…D0
don’tcare
(L/H)
CSN
DLRDY bit
SYNC
RDY
Next command write is available
Figure 143. External Conditional Timing (in DSP Reset)
DSPRSTN bit= “1”
SCLK
SI
don’tcare
(L/H)
F4h
D7 … D0
don’tcare
(L/H)
CSN
DLRDY bit= “0”
SYNC
max 2 x tSYNC
RDY
max0.25 x tSYNC
tSYNC= 1/fs
Figure 144. External Conditional Jump Timing (during RUN)
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7-4. RAM Reading Timing during DSP Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP Reset in the order
of input Command code and Address. PRAM address is fixed to 0h. After writing the Command, the data comes out
from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data
at consecutive address locations, continue to input SCLK as is.
DSPRSTN bit= “0”
CSN
DLRDY bit
SCLK
SI
don’t care
(L/H)
Command
don’t care
(L/H)
Address
Hi-Z or Low
SO
Echo back Output
DATA
DATA
DATA
DATA
DATA
Figure 145. RAM Reading at Consecutive Address
7-5. RAM Reading Timing during DSP RUN
Input control register, device identification code, CRC result and error status during both RUN time and DSP Reset
state. These codes are input in the order of Command and Address.
After completing Command code write, the data comes out from the SO pin synchronous with falling edge of
SCLK. (The SI pin input data is “Don’t care”)
DSPRSTN bit=”1”
CSN
DLRDY bit=”0”
SCLK
SI
SO
don’tcare
(L/H)
Hi-Z or Low
Command
Address
don’tcare
(L/H)
DATA
Echo Back Output
Figure 146. RAM Reading during DSP Reset and RUN
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SYSTEM DESIGN
Figure 147 and Figure 148 show the system connection diagram for the AK4679. An evaluation board [AKD4679]
demonstrates the optimum layout, power supply arrangements and measurement results.
439H
40H
Top View
Digital
Ground
Analog
Ground
2.2u
0.1u
1.8V
2.2u
LIN2
RIN2
LIN1
LIN3
HPR
PVDD
CNA
VSS5
CNB
VSS1
CSN_SCLE
RIN1
RIN3
HPL
VEE
VEE
CPA
CPB
VCOM
LOUT
SCLK_CAD0
PDNE
RIN4
LIN4
PDNA
SDAA
VSS2
2.2u
1u
0.1u
0.1u
Analog
1.7 ∼ 2.0V
10u
SI_CAD1
SYNC2
BCLK1
SCLA
SDTO
TVDDA
SDIN1
SYNC1
LRCK
BICK
SDTOB
SDTI
SYNCB
MCKI
BICKA
BICKB
SDTOA
VDDE
SDOUT1
SDTIB
AVDD
ROUT
MPWR1
MPWR2
RCP
RCN
SDOUT2
SVDD
VSS3
SDIN4
SDIN2
SDIN3
SPN
VSS3
I2CE
SDOUT4_GP1
SDTIA
BCLK2
SVDD
SPP
SPFIL
TVDDE
DVDD
VSS4
Digital I/O
CODEC
1.6 ∼ 3.6V
AK4679
Analog
3.0 ∼ 5.5V
10u
SO_SDAE JX1_SYNC3
TEST
SDOUT3_GP0 SYNCA
JX0_BCLK3 STO_RDY
0.1u
0.1u
Digital I/O
DSP
1.6 ∼ 3.6V
0.1u
0.1u
DSP Core
1.1 ∼ 1.3V
Digital Core
1.7 ∼ 2.0V
Note:
- VSS1, VSS2, VSS3, VSS4 and VSS5 of the AK4679 should be distributed separately from the ground of
external controllers.
- 0.1μF capacitors at power supply pins should be ceramic capacitors. 2.2μF±50% capacitors between the CPA
to CNA pins, the CPB to CNB pins and the VEE to VSS5 pins should be low ESR ceramic capacitors. These
capacitors must be connected as close as possible to the pins.
Figure 147. Typical Connection Diagram (Power Supply Block)
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Top View
Digital
Ground
Analog
Ground
1k 1k
1k
1k
0.22u
0.22u
15
15
LIN2/IN2-
VSS1
Line Out
VCOM
AVDD
RIN2/IN2+
CSN_SCLE
LIN1/IN1+ LIN3/IN3
DMDAT
RIN1/IN1-/
DMCLK
LOUT/LOP SCLK_CAD0
ROUT/LON
SI_CAD1
HPR
PVDD
CNA
VSS5
CNB
RIN3/IN3-
HPL
VEE
VEE
CPA
CPB
PDNE
RIN4
LIN4
PDNA
SDAA
VSS2
BCLK1
SCLA
SDTO
TVDDA
SDIN1
SYNC1
LRCK
BICK
SDTOB
SDTI
SYNCB
MCKI
SYNC2
Line In
AK4679
MPWR1
MPWR2
SO_SDAE
JX1_SYNC3
RCP
RCN
SDOUT2
SVDD
VSS3
SDIN4
SDIN2
SDIN3
SPN
VSS3
I2CE
SDOUT4_GP1
SDTIA
BCLK2
BICKA
BICKB
SDTOA
SVDD
SPP
SPFIL
TVDDE
DVDD
VSS4
VDDE
SDOUT1
SDTIB
TEST
SDOUT3_GP0 SYNCA
JX0_BCLK3 STO_RDY
2.2n
Figure 148. Typical Connection Diagram (Analog Input/Output Block)
(In case of Internal Full-differential Mic and External pseudo differential Mic)
Typical signal connections are shown in Figure 38.
41H
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1. Grounding and Power Supply Decoupling
The AK4679 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and SVDD are
usually supplied from the system’s analog supply, and DVDD, TVDDA, TVDDE and VDDE are supplied from the
system’s digital power supply. The power-up sequence between supplies (AVDD, PVDD, SVDD, DVDD, TVDDA,
TVDDE or VDDE) is not critical. PDNA and PDNE pins should be held “L” when power supplies are tuning on. PDNA
and PDNE pins are allowed to be “H” after all power supplies are applied and settled.
To avoid pop noise at receiver output, headphone outputs, speaker output and line outputs, the AK4679 should be
operated along the following recommended power-up/down sequence.
1) Power-up
- PDNA and PDNE pins should be held “L” when power supplies are turning on. The AK4679 can be reset by keeping
the PDNA pin “L” for 1.5μs or longer after all power supplies are applied and settled.
- In the case that the power supplies are separated in two or more groups, SVDD should be powered ON first.
2) Power-down
- Each of power supplies can be powered OFF after PDNA and PDNE pins are set to “L”.
- In the case that the power supplies are separated in two or more groups, SVDD should be powered OFF last.
VSS1~5 of the AK4679 should be connected to the analog ground plane. System analog ground and digital ground should
be connected together near where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near the AK4679 as possible. Especially, the small value ceramic capacitor is to be closest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 1μF electrolytic capacitor attached to the VCOM pin eliminates the effects of
high frequency noise. No load current is allowed to be drawn from the VCOM pin. All signals, especially clocks, should
be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4679.
3. Charge Pump
2.2μF±50% capacitors between the CPA to CNA pins, the CPB to CNB pins and the VEE to VSS5 pins should be low
ESR ceramic capacitors. These capacitors must be connected as close as possible to the pins. No load current may be
drawn from the VEE pin.
4. Analog Inputs
The input signal range scales with 1.0 x AVDD Vpp (typ) at MGNL=MGNR=0dB, AVDD=1.8V and single-ended input,
centered around the internal common voltage (typ. 0.47 x AVDD). The input signal must be AC coupled using a
capacitor. The cut-off frequency (fc) is 1/(2πRC).
5. Analog Outputs
Stereo Line outputs and Mono Receiver output are centered at typ. 0.8 x AVDD. Stereo line output (LOUT/ROUT pins)
must be AC –coupled using a capacitor. Receiver output (RCP/RCN pins) should be connected directly to a receiver.
Headphone outputs (HPL/HPR pin) are centered at 0V and should be directly connected to a headphone. Speaker output
is PWM output (Class-D) and it is not necessary to add an external filter such as LC filters.
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CONTROL SEQUENCE (AUDIO)
■ Clock Set-up
When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
Power Supply
PDNA pin
PMVCM bit
(1)
(2)
(1) Power Supply & PDNA and PDNE pins = “L” Æ “H”
(3)
(Addr:00H, D0)
(2)Addr:00H, Data:00H
Addr:03H, Data:F4H
Addr:04H, Data:22H
Addr:05H, Data:02H
PMPLL bit
(Addr:04H, D0)
MCKI pin
(4)
Input
M/S bit
(3)Addr:00H, Data:01H
(Addr:04H, D1)
10msec(max)
(5)
BICK pin
LRCK pin
Output
(4)Addr:04H, Data:23H
BICK and LRCK output
Figure 149. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDNA pins = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates. Power-up time of VCOM is maximum
1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.
(4) PLL lock time is 10ms(max.) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(5) The AK4679 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
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2. PLL Slave Mode (BICK pin)
Example:
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
PDNA pin
PMVCM bit
(1)
4fs(1)ofPower Supply & PDNA and PDNE pins = “L” Æ “H”
(2)
(3)
(Addr:00H, D0)
(2)Addr:00H, Data:00H
Addr:03H, Data:F3H
Addr:05H, Data:02H
PMPLL bit
(Addr:04H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:01H
(4)
Internal Clock
(5)
(4) Addr:04H, Data:01H
Figure 150. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDNA pin = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set. DIF1-0, FS3-0 and
PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates. Power-up time of VCOM is maximum
1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is supplied. PLL
lock time is 2ms (max.).
(5) Normal operation starts after that the PLL is locked.
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3. EXT Slave Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
Power Supply
PDNA pin
PMVCM bit
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
(2)
(3)
Input
(2)Addr:00H, Data:00H
Addr:03H, Data:F0H
Addr:04H, Data:00H
Addr:05H, Data:02H
Input
(3) Addr:00H, Data:01H
(Addr:00H, D0)
(4)
MCKI pin
(4)
LRCK pin
BICK pin
MCKI, BICK and LRCK input
Figure 151. Clock Set Up Sequence (3)
<Example>
(1) After Power Up, PDNA pin = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
DIF1-0, CM1-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates. Rise-up time of the VCOM pin is 1.5ms
(max) when the external capacitance is 1μF.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
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4. EXT Master Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
Power Supply
PDNA pin
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
(4)
PMVCM bit
(2) MCKI input
(Addr:00H, D0)
(2)
MCKI pin
(3)Addr:00H, Data:00H
Addr:03H, Data:F0H
Addr:04H, Data:02H
Addr:05H, Data02H
Input
(3)
M/S bit
(Addr:04H, D1)
LRCK pin
BICK pin
BICK and LRCK output
Output
(4) Addr:00H, Data:01H
Figure 152. Clock Set Up Sequence (4)
<Example>
(1) After Power Up, PDNA pin = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) MCKI should be input.
(3) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
After DIF1-0, CM1-0 and FS3-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates. Power-up time of VCOM is maximum
1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.
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■ MIC Input Recording (Stereo)
Example:
FS3-0 bits
(Addr:03H, D7-4)
0000
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +15dB
MIC Power 1: 2.5V Output
ALC setting: Refer to Table 34
ALC: Enable
1111
(1)
MIC Control
(Addr:07H, D7-0)
55H
AAH
MIC Signal Select 00H
(Addr:06H)
ALC Setting
(Addr:13H, 15H, 16H)
ALC Enable
(Addr:17H)
ALC State
(1) Addr:04H, Data:FxH
(2)
(2) Addr:07H, Data: AAH
xxH
(3)
xxH
(3) Addr:06H, Data: xxH
xxH
(4)
02H
03H
02H
(5)
(10)
ALC Disable
(4) Addr:13H, 15H, 16H, Data:xxH
(5) Addr:17H, Data:03H
ALC Disable
ALC Enable
(6)
(9)
(6) Addr:02H, Data:01H
PMMP1 bit
(Addr:02H, D0)
(7) Addr:00H, Data:33H
PMADL/R bits
PMPFILbit
(7)
(8)
Recording
(Addr:00H, D5-4, D1)
1059/fs
(8) Addr:00H, Data:01H
ADC Output
Data
"L" Output
Initialize Normal State
"L" Output
(9) Addr:02H, Data:00H
(10) Addr:17H, Data:02H
Figure 153. Stereo MIC Input Sequence
(MIC Recording: LINx/RINx → MICL/R → ADCL/R → ALC → Audio I/F → SDTO)
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Example of the ALC setting (Recording Path)”.
430H2
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). MIC, ADC and Programmable Filter should be powered-up in
consideration of VCOM ride time and PLL lock time after a sampling frequency is changed when the AK4679 is
in PLL mode.
(2) Set up Gain for MIC-Amp (Addr: 07H)
(3) Set up MIC Input Selector (Addr: 06H)
(4) Set up REF value for ALC (Addr: 13H) , Timer Select for ALC (Addr: 15H) and ALC mode (Addr: 16H)
(5) ALC Enable (Addr: 17H): ALC bit = “0” → “1”
(6) Power Up MIC Power1: PMMP1 bit = “0” → “1”
(7) Power Up MIC-Amp, ADC and Programmable Filter: PMADL/R = PMPFIL bits = “0”→“1”
The initialization cycle time of ADC is 1059/fs=24ms @ fs=44.1kHz, ADRST bit = “0”. ADC outputs “0” data
during the initialization cycle. After the ALC bit is set to “1”, the ALC operation starts from IVOL value
(8) Power Down MIC-Amp, ADC and Programmable Filter: PMADL/R= PMPFIL bits = “1” → “0”
18H
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the ADC block is powered-down. If the registers for the ALC operation are also changed when the
sampling frequency is changed, it should be done after the AK4679 goes to the manual mode (ALC bit = “0”) or ADC
block is powered-down (PMADL = PMADR bits = “0”). IVOL gain is not reset when PMADL = PMADR bits = “0”,
and then IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”.
(9) Power Down MIC Power 1: PMMP1 bit = “1” → “0”
(10) ALC Disable: ALC bit = “1” → “0”
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■ Headphone-Amp Output
Example :
FS3-0 bits
(Addr:03H, D7-4)
0000
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
HP Volume Level: −6dB
5 band EQ: Enable
1111
(1)
HPG5-0 bits
(Addr:0FH, D5-0)
(1) Addr:03H, Data FxH
(2)
23H
20H
(2) Addr:0FH, Data 20H
(3)
5EQ bit
(Addr:17H, D3)
(8)
0
1
PMDAL/R bits
PMEQ bit
0
(4)
(3) Addr:17H, Data 0AH
(4) Addr:01H, Data 0DH
(7)
(Addr:01H, D3-2, D0)
(5) Addr:0BH, Data 03H
(5)
PMHPL/R bits
28ms
(Addr:0BH, D1-0)
(6)
HPL/R pins
0V
Normal Output
Playback
0V
(6) Addr:0BH, Data 00H
(7) Addr:01H, Data 00H
(8) Addr:17H, Data 02H
Figure 154. Headphone-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → HPL/HPR)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). DAC and Headphone-Amp should be powered-up in consideration
of VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL
mode.
(2) Set up analog volume for HP-Amp (Addr: 0FH, HPG5-0 bits)
(3) Enable 5-band Equalizer: 5EQ bit = “0” Æ “1” (Frequency Response and gain are selected by Addr =
50H-6EH.)
(4) Power up DAC and EQ : PMDAL = PMDAR = PMEQ bits = “0” → “1”
(5) Power up Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = “0” → “1”
The power-up time of HP-Amp block is 28ms. HPL and HPR pins output 0V until the power-up time of
HP-Amp block passes.
(6) Power down Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = “1” → “0”
HPL and HPR pins go to 0V.
(7) Power down DAC and EQ: PMDAL = PMDAR = PMEQ bits = “1” → “0”
(8) Disable 5-band Equalizer: 5EQ bit = “1” Æ “0”
19H
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■ Speaker-Amp Output
Example :
FS3-0 bits
(Addr:03H, D7-4)
0000
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
SPK Volume Level: −9dB
5 band EQ: Enable
1111
(1)
SPKG3-0 bits
(Addr:10H, D3-0)
(1) Addr:03H, Data FxH
(2)
1011
1000
(2) Addr:10H, Data B8H
(3)
DACSL/R bits
(10)
(3) Addr:09H, Data C0H
(Addr:09H, D7-6)
(9)
(4)
5EQ bit
(Addr:17H, D3)
0
1
PMDAL/R bits
PMEQ bit
0
(5)
(4) Addr:17H, Data 0AH
(5) Addr:01H, Data 0DH
(8)
(Addr:01H, D3-2, D0)
(6) Addr:0DH, Data 08H
(6)
PMSPK bit
32ms
(Addr:0DH, D4)
(7)
SPP/SPN pins
Hi-Z
0V Normal Output
Playback
Hi-Z
(7) Addr:0DH, Data 00H
(8) Addr:01H, Data 00H
(9) Addr:17H, Data 02H
(10) Addr:09H, Data 00H
Figure 155. Speaker-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → SPP/SPN)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). DAC and Speaker-Amp should be powered-up in consideration of
VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL mode.
(2) Set up analog volume for SPK-Amp (Addr: 10H, SPKG3-0 bits)
(3) Set up the path of “SDTI Æ DAC Æ SPK-Amp”: DACSL = DACSR bits = “0” → “1”
(4) Enable 5-band Equalizer: 5EQ bit = “0” Æ “1” (Frequency Response and gain are selected by Addr =
50H-6EH.)
(5) Power up DAC and EQ: PMDAL = PMDAR = PMEQ bits = “0” → “1”
(6) Power up SP-Amp block: PMSPK bit = “0” → “1”
The power-up time of SPK-Amp block is 32ms. SPP and SPN pins output 0V until the power-up time of
SPK-Amp block passes.
(7) Power down SPK-Amp block: PMSPK bit = “1” → “0”
SPN and SPP pins go to 0V.
(8) Power down DAC and EQ: PMDAL = PMDAR = PMEQ bits = “1” → “0”
(9) Disable 5-band Equalizer: 5EQ bit = “1” Æ “0”
(10) Disable the path of “DAC → Speaker-Amp”: DACSL = DACSR bits = “1” → “0”
20H
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■ Stereo Line Output
Example:
FS3-0 bits
(Addr:03H, D7-4)
0000
PLL, Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kH z
OVOLC bit = “1”(default)
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
1111
(1)
LVL2-0 bits
(Addr:0EH, D2-0)
011
010
(1) Addr:03H, Data:FxH
(2)
(2) Addr:0EH, Data:02H
Addr:19H, Data:03H
Addr:14H, Data:05H
Addr:09H, Data:03H
PFSEL bis
(Addr:19H, D0)
PFMXL/R1-0 bits 0000
0101
(Addr:14H, D3-0)
(3) Addr:1DH&1EH, Data:1CH
DACL/R bits
(9)
(Addr:09H, D1-0)
OVL/R6-0 bits
(Addr:1DH&1EH, D6-0)
0CH
(4) Addr:0AH, Data:04H
(5) Addr:01H, Data:0CH
Addr:00H, Data:03H
Addr:0AH, Data:07H
1CH
(3)
LOPS bit
(Addr:0AH, D2)
PMDAL/R bits
PMPFIL bit
(Addr:00H, D7-6, D1)
(6) Addr:0AH, Data:03H
(4)
(6)
(7)
(10)
(8)
(5)
PML/RO bits
(Addr:0AH, D1-0)
LOUT pin
ROUT pin
>300 ms
Normal Output
>300 ms
Playback
(7) Addr:0AH, Data:07H
(8) Addr:0AH, Data:04H
Addr:00H, Data:01H
Addr:01H, Data:00H
(9) Addr:09H, Data:00H
(10) Addr:0AH, Data:00H
Figure 156. Stereo Lineout Sequence
(Lineout Playback: SDTI → Audio I/F → SVOLA → DATT-A → DACL/R → LOUT/ROUT)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). DAC and Stereo Line-Amp should be powered-up in consideration
of VCOM rise time and PLL lock time after the sampling frequency is changed when the AK4679 is in PLL
mode.
(2) Set up the path of “SDTI Æ DAC Æ Stereo Line-Amp”: PFSEL = “0” Æ “1”, PFMXL1-0 = PFMXR1-0 bits =
“0000” Æ “0101”, DACL = DACR bits = “0” Æ “1”
Set up analog volume for Stereo Line-Amp (Addr: 0EH, LVL2-0 bits)
(3) Set up the output digital volume (Addr: 1DH and 1EH)
When OVOLC bit is “1” (default), OVL6-0 bits (1DH) set the volume of both channels. After DAC is
powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft
transition.
(4) Enter power-save mode of Stereo Line-Amp: LOPS bit = “0” Æ “1”
(5) Power-up DAC, Programmable Filter and Stereo Line-Amp: PMDAL = PMDAR = PMPFIL = PMLO =
PMRO bits = “0” → “1”
LOUT and ROUT pins rise up to VCOM voltage after PMLO and PMRO bits are changed to “1”. Rise time is
300ms (max.) at C=1μF and AVDD=1.8V.
(6) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
(7) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”
(8) Power-down DAC, Programmable Filter and Stereo Line-Amp: PMDAL = PMDAR = PMPFIL = PMLO =
PMRO bits = “1” → “0”
LOUT and ROUT pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=1.8V.
(9) Disable the path of “DAC Æ Stereo Line-Amp”: DACL = DACR bits = “1” Æ “0”
(10) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
21H
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■ Stop of Clock
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC )
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:04H, D0)
External MCKI
Input
(1) Addr:04H, Data:02H
(2)
(2) Stop an external MCKI
Figure 157. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop an external MCKI clock.
2. PLL Slave Mode (BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:04H, D0)
(2)
External BICK
Input
(1) Addr:04H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 158. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks.
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3. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 159. Clock Stopping Sequence (3)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
4. EXT Master Mode
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop the external MCKI
Figure 160. Clock Stopping Sequence (4)
<Example>
(1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”.
■ Power down
Power supply current can be shut down (typ. 50μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting the PDNA pin = “L”. When the PDNA pin = “L”, the registers are initialized.
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CONTROL SEQUENCE (PCM)
■ PCM I/F A(Baseband) to PCM I/F B(Bluetooth)
Example:
PCM I/F A/B Format: Linear, Long Frame
MSBSA=BCKPA= “0”, MSBSB=BCKPB=”0”
Power Supply
PDNA pin
PCM I/F A Sampling Frequency: 16kHz
PCM I/F B Sampling Frequency: 44.1kHz
(1)
BIVOL: -6dB, DATT-C : -6dB
(2)
(6)
(3)
(1) Power Supply & PDN pin = “L” Æ “H”
PMVCM bit
(Addr:00H, D0)
(4)
(5)
PMOSC bit
PMPCMA/B bit
PMSRx bits
(2)Addr:00H, Data:00H
Addr:18H, Data:0BH
Addr:20H, Data:01H
Addr:21H, Data:01H
Addr:24H, Data:18H
Addr:26H: Data:02H
Addr:27H, Data:07H
Addr:28H, Data:00H
(Addr:1FH, D6-0)
SYNCA/B pins
BICKA/B pins
SDTOA pin
Input
164/fs2
"0" data
Normal State
"0" data
(3) Addr:00H, Data:01H
164/fs3
SDTOB pin
"0" data
Normal State
"0" data
(4) Addr:1FH, Data:7FH
Phone Call
(5) Addr:1FH, Data:00H
(6) Addr:00H, Data:00H
Note: PMSRx bit means PMSRAI, PMSRAO, PMSRBI and PMSRBO bits
Figure 161. Sequence of PCM I/F A to PCM I/F B
(Baseband RX to Bluetooth TX: SDTIAÆPCM I/F AÆSRCAIÆDATT-CÆMIX3ÆPCM I/F BÆSDTOB &
Bluetooth RX to Baseband TX: SDTIBÆPCM I/F BÆBIVOLÆMIX2AÆMIX2CÆSRCAOÆPCM I/F AÆSDTOA)
<Example>
(1) After Power Up, PDNA pin = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679.
(2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
OVTMB, BIV2-0, SDOA/BD, FMTA/B1-0, LAWA/B1-0, BCKPA/B, MSBSA/B, CVL6-0, MX2A1-0,
MX2C1-0, MXSB2-0, SBMX1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Power Up Internal Oscillator, SRCAI, SRCAO, SRCBI, SRCBO, PCM I/F A port and PCM I/F B port.
PMSRBO=PMSRBI=PMPCMB=PMOSC=PMSRAO=PMSRAI=PMPCMA bits: “0” Æ “1”
SDTOA(SDTOB) outputs data after power-down state is released by inputting SYNCA(SYNCB). This initial
of SRCAO(SRCBO) is 164/fs2(164/fs3) for SDTOA(SDTOB) output enable after power-down state is
released by inputting SYNCA(SYNCB).
(5) Power down Internal Oscillator, SRCAI, SRCAO, SRCBI, SRCBO, PCM I/F A port and PCM I/F B port.
PMSRBO=PMSRBI=PMPCMB=PMOSC=PMSRAO=PMSRAI=PMPCMA bits: “1” Æ “0”
(6) Power Down VCOM: PMVCM bit = “1” Æ “0”
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■ Receiver-Amp Output
PCM I/F A
Format &
Path Setting
Example:
xxxx
(1)
PMMIX bit
PMOSC bit
PMPCMA bit
PMSRAI bit
(Addr:10H, D7-4)
(2) Addr:1FH, Data:1BH
(3)
(3) Addr:10H, Data:90H
1001
1011
5EQ bit
(4) Addr:17H, Data:0AH
(11)
(4)
(Addr:17H, D3)
(1) Addr:09H, Data:20H
Addr:14H, Data:40H
Addr:20H, Data:01H
Addr:25H, Data:00H
(12)
(2)
(Addr:1FH, D7,3, 1-0)
RCVG3-0 bits
PCM I/F A Format : Linear, Long
MSBSA=BCKPA= “0”
DATT: −8dB, DATT-B: 0dB(default)
R CV Volume Level: −6dB
5 band EQ: Enable
xxxx
0
1
0
(6) Addr:0DH, Data:02H
(5)
OVR6-0 bits
(Addr:1EH, D6-0)
(5) Addr:1EH, Data:1CH
0CH
1CH
(7) Addr:01H, Data:09H
Addr:0DH, Data:03H
156/fs2
(8) Addr:0DH, Data:01H
RCVPS bit
(Addr:0DH, D1)
(6)
(8)
PMDAR bit
PMEQ bit
(Addr:01H, D3, 0)
PMRCV bit
(Addr:0DH, D0)
RCP pin
RCN pin
(13)
(9)
(10)
Phone Call
(9) Addr:0DH, Data:03H
(10) Addr:0DH, Data:02H
Addr:01H, Data:00H
(7)
>1 ms
(11) Addr:17H, Data:02H
Normal Output
(12) Addr:1FH, Data:00H
(13) Addr:0DH, Data:00H
Figure 162. Receiver-Amp Output Sequence
(Baseband Rx: SDTIA→PCM I/F A→SRCAI→DATT-B→MIX1R→5-Band EQ→DATT-A→DACR→RCP/RCN)
<Example>
At first, audio clocks should be supplied according to “Clock Set Up” sequence. DAC and Receiver-Amp should be
powered-up in consideration of VCOM rise time
(1) Set up the format of PCM I/F A(FMTA1-0, LAWA1-0, BCKPA, MSBSA bits) and the path of “SDTIA Æ
DAC Æ Receiver-Amp”(MX1R2-0 bits = “000” Æ “000”, SRMXR1-0 bits = “00” Æ “01”, DACRR bit = “0”
Æ “1”)
(2) Power-up Internal Oscillator, MIX1 block and SRCAI: PMMIX = PMOSC= PMSRAI = PMPCMA bits = “0”
→ “1”. The initial time of SRCAI is 164/fs2 after SYNCA clock is supplied.
(3) Set up analog volume for Receiver-Amp (Addr: 10H, RCVG3-0 bits)
(4) Enable 5-band Equalizer: 5EQ bit = “0” Æ “1” (Frequency Response and gain are selected by Addr =
50H-6EH.)
(5) Set up the output digital volume (Addr: 1EH)
After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by
the soft transition.
(6) Enter power-save mode of Receiver-Amp: RCVPS bit = “0” Æ “1”
After passing the initial time of SRCAI, the Receiver-Amp should enter power-save mode.
(7) Power-up DAC, EQ and Receiver-Amp: PMDAR = PMEQ = PMRCV bits = “0” → “1”
The RCN pin rises up to VCOM voltage after PMRCV bit is changed to “1”.
(8) Exit power-save mode of Receiver-Amp: RCVPS bit = “1” Æ “0”
RCVPS bit should be set to “0” after the RCN pin rises up. Receiver-Amp goes to normal operation by setting
RCVPS bit to “0”.
(9) Enter power-save mode of Receiver-Amp: RCVPS bit: “0” Æ “1”
(10) Power-down DAC, EQ and Receiver-Amp: PMDAR = PMEQ = PMRCV bit = “1” → “0”
Receiver-Amp becomes to power-down mode.
(11) Disable 5-band Equalizer: 5EQ bit = “1” Æ “0”
(12) Power-down Internal Oscillator, MIX1 block and SRCAI: PMOSC = PMMIX = PMSRAI and PMPCMA bits
= “1” → “0”
(13) Exit power-save mode of Receiver-Amp: RCVPS bit = “1” Æ “0”
RCVPS bit should be set to “0” after Receiver-Amp power-down.
2H
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[AK4679]
PACKAGE
78pin BGA
Top View
Bottom View
3.2
A
4.5±0.1
B
0.4
0.4
3.2
0.9 MAX
4.5±0.1
4679
XXXX
78 φ 0.2 ~0.3
φ 0.08 M
S
AB
0.08 S
0.12∼0.2
S
■ Material & Lead finish
Package molding compound:
Solder ball material:
Epoxy, Halogen (bromine and chlorine) free
SnAgCu
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[AK4679]
MARKING
4679
XXXX
1
A
XXXX: Date code (4 digit)
Pin #A1 indication
REVISION HISTORY
Date (Y/M/D)
12/04/23
12/05/15
Revision
00
01
Reason
First Edition
Error
Correction
12/08/30
02
12/11/02
03
Error
Correction
Specification
Change
12/11/22
04
Description
Addition
13/01/28
05
Description
Addition
13/02/18
06
Error
Correction
Page
Contents
4, 8-12, Pin names were corrected.
58, 59,
LIN2/IN2+ → LIN2/IN2159, 201
RIN2/IN2- → RIN2/IN2+
4
■ Block Diagram
Figure 1 was changed.
59
■ MIC/LINE Input Selector
Figure 53 was changed.
201
SYSTEM DESIGN
Figure 148: A connection to the microphone was changed.
24
Switching Characteristics
External Slave Mode, BICK Input Timing
Period: 312.5ns → 312.5ns or 1/(126fs)s
Note 52 was added.
138
■ DSP STATE TRANSITION
Sleep: The description was changed.
Wait Sync: The description was changed.
48, 49,
■ PLL Mode
50
A detailed description was added:
Note 74 and Note 75 were added.
Table 7 was added.
51
■ PLL Master Mode
The description was changed.
136
■ PCM Audio Interface Format
Description was changed.
137-139
Figure 110 ~ 117 were changed.
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Date (Y/M/D)
Revision
Reason
Error
Correction
Page
152153
197
Description
Change
145
152
192
Specification
Addition
193
195
Description
Addition
200
201
Contents
■ SPI Serial Control Interface (DSP block)
Figure 135 and 137 were changed.
■ Command Format
7. Timing
Figure 138 and 139 were changed.
■ RAM Clear
Figure 122 was changed.
■ SPI Interface (I2C pin= “L”)
Note 79 was changed.
■ Command Code map for the DSP
Table 132 and 133 were changed: “(0000h fix)” was deleted.
■ Command Format
1. Write Operation during DSP Reset
1-1. Program RAM (PRAM) Write (during DSP Reset)
(2)(3) were changed.
4. Read Operation (DLRDY bit = “1”)
4-1. Program RAM (PRAM) Read (during DSP Reset)
(2)(3) were changed.
7-3. External Conditional Jump
Figure 143 and 144 were changed.
7-4. RAM Reading Timing during DSP Reset
Figure 145 was changed.
7-5: The title was changed
→ “RAM Reading Timing during DSP RUN”
Figure 146 was changed.
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[AK4679]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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