TI GC3021

SLWS131
GC3021
MIXER AND
CARRIER REMOVAL
CHIP
DATASHEET
June 22, 1998
This datasheet contains information which may be changed at any time without notice.
GC3021 MIXER AND CARRIER REMOVAL CHIP
1.0
DATA SHEET
KEY FEATURES..........................................................................................................................1
1.1
2.0
BLOCK DIAGRAM................................................................................................................................. 1
FUNCTIONAL DESCRIPTION ...................................................................................................2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.0
CONTROL INTERFACE ....................................................................................................................... 2
SYNC COUNTER ................................................................................................................................. 3
CLOCK GENERATOR ......................................................................................................................... 4
INPUT FORMAT ................................................................................................................................... 4
MIXER .................................................................................................................................................. 6
SYMBOL ALIGN ................................................................................................................................... 7
PHASE ERROR RAM .......................................................................................................................... 7
PHASE LOCK LOOP ............................................................................................................................ 8
NCO ...................................................................................................................................................... 9
SNAPSHOT RAM ............................................................................................................................... 10
OUTPUT FORMAT ............................................................................................................................. 10
DATA DELAYS ................................................................................................................................... 10
POWER DOWN AND KEEP ALIVE CIRCUIT .................................................................................... 11
DIAGNOSTICS ................................................................................................................................... 11
PACKAGING ............................................................................................................................12
3.1
4.0
PIN DESCRIPTIONS........................................................................................................................... 13
CONTROL REGISTERS ...........................................................................................................15
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
5.0
MODE CONTROL REGISTER ........................................................................................................... 16
SYNC CONTROL REGISTERS ......................................................................................................... 17
DELAY CONTROL REGISTER .......................................................................................................... 18
COUNTER CONTROL REGISTER .................................................................................................... 18
PLL CONTROL REGISTER ............................................................................................................... 19
FREQUENCY WORD REGISTERS ................................................................................................... 19
OUTPUT CONTROL REGISTERS .................................................................................................... 20
SNAPSHOT CONTROL REGISTER .................................................................................................. 21
PHASE REGISTER ............................................................................................................................ 21
ONE SHOT ADDRESS ...................................................................................................................... 21
TEST OUTPUT REGISTER ............................................................................................................... 21
SPECIFICATIONS ....................................................................................................................22
5.1
5.2
5.3
5.4
5.5
6.0
ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 22
RECOMMENDED OPERATING CONDITIONS ................................................................................. 22
DC CHARACTERISTICS ................................................................................................................... 22
AC CHARACTERISTICS .................................................................................................................... 22
HIGH SPEED MODE SPECIFICATIONS ........................................................................................... 24
APPLICATION NOTES .............................................................................................................25
6.1
6.2
6.3
6.4
6.5
6.6
POWER AND GROUND CONNECTIONS ......................................................................................... 25
STATIC SENSITIVE DEVICE ............................................................................................................. 25
REDUCED VOLTAGE OPERATION .................................................................................................. 25
HIGH SPEED MIXER ......................................................................................................................... 25
QAM DEMODULATOR ...................................................................................................................... 26
DIAGNOSTICS.................................................................................................................................... 27
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GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
GC3021 DATASHEET
KEY FEATURES
1.0
CARRIER REMOVAL MODE
•
80 Million Complex Samples per second (CSPS)
input data
•
160 MSPS real input data
(differential PECL data and clock)
•
12 bit input and output data
•
•
12 bit by 12 bit complex multiplier
80 MSPS complex input data
(TTL level inputs)
•
4K bit phase error lookup RAM
•
12 bit inputs and outputs
•
Phase error feedback loop for carrier and
phase offset removal
•
32 bit NCO phase control
•
NCO generates 12 bit sines and cosines
•
32 bit numerically controlled oscillator (NCO)
•
Snapshot memory for adaptive filtering
•
OVERALL
Microprocessor interface for control,
output, and diagnostics
•
750 mW power at 50 MHz, 5 volts
•
200 mW at 30 MHz, 3.3 volts
Built in diagnostics
•
160 pin plastic quad flat pack package
•
1.1
MIXER MODE
BLOCK DIAGRAM
A block diagram illustrating the major functions of the chip is shown in Figure 1
9 Bits
Internal Controls
CONTROL
INTERFACE
16 Bits
HSCK
HSI
HCKO
DATA OUT
(70 MHz)
High speed
clock and sync
12 Bits
Complex data at 70 MHz HSO
Real data at 140 MHz
SO
SA
SB
SYNC
COUNTER
CLOCK
GENERATOR
CKENA
CKENB
12 Bits
12 Bits
Odd/Even Complex Pairs,
Complex Samples,
or I/Q Symbols
YA[0:11]
YB[0:11]
YC[0:11]
YD[0:11]
Internal
Syncs
12 Bits
CK
12 Bits
OUTPUT
FORMAT
12 Bits
12 Bits
12 Bits
12 Bits
Q[0:11]
12 Bits
12 Bits
I[0:11]
DATA IN
MIXER
AND
DC REMOVAL
SYMBOL
ALIGN
12 Bits
INPUT
FORMAT
12 Bits
CS
R/W
A[0:8]
C[0:15]
Internal
Clocks
12 Bits
PHASE ERROR
LOOKUP RAM
4K BY 1 Memory
1 Bit
EOUT
12 Bits
EIN
1 Bit
PHASE
LOCK
LOOP
CIRCUIT
32 Bits
NCO
CIRCUIT
12 Bits
12 Bits
12 Bits
SNAPSHOT
RAM
Quad 64 Word
Memory
sync
Carry In
CIN
SN
1 Bit
Figure 1. GC3021 BLOCK DIAGRAM
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GC3021 MIXER AND CARRIER REMOVAL CHIP
2.0
DATA SHEET
FUNCTIONAL DESCRIPTION
Fabricated in 0.7 micron CMOS technology, the GC3021 chip is designed to mix input data with an
internally generated sine/cosine sequence. The chip can be used as a signal mixer, or if the phase error
lookup and phase lock loop (PLL) circuitry is enabled, as a carrier removal circuit for signal demodulation.
The mixer accepts complex data at rates up to 80 MHz , or real samples at rates up to 160 MHz in the high
speed input mode . The chip mixes the input with a complex sinusoid, and outputs the results at a 80 MHz
rate.
The input data in the high speed mode is assumed to be P-ECL (3 volt low, 4 volt high) differential
inputs. The 160 MHz input data is split into even and odd samples streams, each at a rate of 80 million
samples per second. The even and odd time sample data streams are mixed with sines and cosines which
have also been split into even and odd time streams. The complex results are then output as two complex
pairs at 80 MHz, one for the even time samples and one for the odd time samples.
The frequency of the sine/cosine sequence is specified as a 32 bit phase word which drives a phase
accumulator. A carry input to the phase accumulator allows the user to extend the tuning resolution with an
external accumulator.
The GC3021 chip’s carrier removal mode allows the chip to be used as part of a QPSK/QAM
demodulator using decision error feed back to achieve carrier lock. A phase error feedback circuit uses the
upper 7 bits of the I and Q mixer outputs to lookup a one bit phase error term. The phase error lookup is
performed by mapping the I/Q pair into a single quadrant so that the lookup table address is only 12 bits (6
bits of I and 6 bits of Q). The 4096 bit lookup table is programmed by the user to output the sign of the phase
error for each possible I/Q pair. This phase error feeds a phase-lock-loop (PLL) circuit which adjusts the
sinusoid frequency to drive the average phase error to zero.
A snapshot RAM is included to store blocks of I/Q symbol outputs and the sine/cosine pairs used
to generate them. This information is used by an external DSP chip or microprocessor to lookup the symbol
error, to rotate the error by the sine/cosine phase, and then update equalizer coefficients.
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus
consisting of a 16 bit data I/O port, a 9 bit address port, a read/write bit, and a control select strobe. The
control registers, coefficient registers, phase error RAM and snapshot memory are mapped into the 512
word address space of the control port.
A detailed description of the major circuits within the chip follows.
2.1
CONTROL INTERFACE
The control interface allows an external processor to configure the chip, to capture and read
samples from the chip and to perform diagnostics.
The chip is configured by writing control information into control registers within the chip. The
registers are written to or read from using the C[0:15], A[0:8], R/W, and CS pins. Each control register has
been assigned a unique address within the chip. An external processor (a microprocessor, computer, or
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DSP chip) can write into a register by setting A[0:8] to the desired register address, setting the R/W pin low,
setting C[0:15] to the desired value and then pulsing CS low.
To read from a control register the processor must set A[0:8] to the desired address, set R/W high,
and then set CS low. The chip will then drive C[0:15] with the contents of the selected register. After the
processor has read the value from C[0:15] it should set CS high. The C[0:15] pins are turned off (high
impedance) whenever CS is high or R/W is low. The chip will only drive these pins when CS is low and R/W
is high.
The chip’s control address space is divided into fourteen control registers, a test port, four DC offset
registers, 256 phase error memory words, and 256 snapshot memory words. The 14 control registers are
MODE_REG, SYNC_REG0, SYNC_REG1, DELAY_REG, COUNTER_REG, PLL_REG, FREQ_REG0,
FREQ_REG1, OUTPUT_REGA, OUTPUT_REGB, OUTPUT_REGC, OUTPUT_REGD, SNAP_REG, and
PHASE_REG. The control registers are mapped to addresses 0 to 13. See Section 4.0 for details about the
contents of these registers.
Address 14 is used to generate a one-shot pulse. This pulse, OS, which is one clock cycle wide,
can be output from the chip on the SO pin or used to synchronize internal circuits. Address 15 is a read only
port used to monitor the power-down and keepalive clock functions for test. Addresses 16 through 19 are
the DC offset registers DC_I_IN, DC_Q_IN, DC_I_OUT, DC_Q_OUT.
Addresses 20 through 255 are unused.
Addresses 256 through 511 are shared between the phase error memory and the snapshot
memory. Reading from these addresses accesses the contents of the snapshot memory. Writing to these
addresses loads the phase error lookup memory.
2.2
SYNC COUNTER
The sync counter circuit is used to generate sync pulses for the chip. The circuit accepts two sync
inputs (SA and SB) and generates internal syncs and a sync out (SO) pulse. The circuit contains a 20 bit
counter which can be set to count in cycles of 16*(COUNT+1) clocks, where COUNT ranges from 0 to 216-1.
The counter’s terminal count (TC) can be used as a synchronization pulse. The lower 12 bits from the
counter are used as input data during diagnostics.
The circuit can generate a one-shot pulse (OS) which can be used as a synchronization pulse.
The input syncs SA and SB can be delayed by up to 258 clock cycles. The delayed syncs (DSA and
DSB) can be used to adjust the sync timing to meet system requirements.
The internal syncs are used to synchronize the counter, the symbol align circuit, the snapshot
memory, the phase lock loop circuit and NCO circuit. Each circuit can be independently synchronized to SA,
SB, DSA, DSB, TC, OS, or left to free run. The sync output can also be chosen from these syncs.
2.3
CLOCK GENERATOR
The clock generator generates the internal clocks from the clock input (CK). Two clock enable
inputs (CKENA and CKENB) are used to enable or disable the clock. Both enables must be low for internal
clocks to be generated. The enables are clocked into the chip and are used to enable or disable the
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following clock edge. The enables are designed to be used with the data valid strobes from the GC3011
digital resampler and GC2011 digital filter chips.
2.4
INPUT FORMAT
The input format circuit accepts complex data at the clock rate of the chip, or real data at twice the
clock rate of the chip. The input format circuit outputs pairs of samples to the mixer circuit where the pair is
either a complex data pair, or an even and odd time sample pair. A block diagram of the input circuit is
shown in Figure 2.
VTERM
HSI
HSI
+
-
HS
DATA
(12 bits)
+
-
clock
Differential Receivers
and Clock divider
+
-
HCK
HCK
clock HCKO
out
TO CHIP
CLOCK
External Clock Driver
DATA
SPLITTER
sync
data
sync HSO
out
12 Bits
To Internal
Sync Generator
and Counter
Even Odd
Receiver Enable
and Termination Enable
COMPLEX
DATA
12 Bits
I
12 Bits
Q
12 Bits
Data
To
Mixer
DATA
MUX
12 Bits
Diagnostic
Ramp
12 Bits
XI
XQ
Mode
Select
Figure 2. INPUT FORMAT CIRCUIT
The data, clock and sync operate at a rate which is twice the chip’s clock rate in the high speed
mode. The differential receivers convert the PECL signals to CMOS voltage swings. The data splitter divides
the high speed data stream into two streams at half the high speed rate. One stream contains the odd time
samples and the other contains the even time samples. The high speed sync synchronizes the data splitter
by identifying a sample which should show up in the even data stream. The data splitter circuit divides the
high speed clock in half and outputs it as HCKO. The HCKO clock should be buffered and used as the clock
input to the chip (See Section 2.3). The HSO sync is the high speed sync reclocked by HCKO. The HSO
sync is used within the chip as one of the synchronization sources for the internal circuitry, or can be routed
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out of the chip on the SO pin (See Section 4.2). The timing relationships between the data, HCK, HSI and
HSO are shown in Figure 3.
HCK
HSI
HCKO
HSO
I/Q IN
x0
x1
x2
x3
XI OUT
x0
XQ OUT
x1
x4
x2
x3
Figure 3. SYNC TIMING
The differential data inputs share pins with the I/Q complex data inputs. The I input pins are used
as the positive differential inputs and the Q pins are used as the negative differential inputs. Termination
resistors (70 Ohms) are provided on the chip which are connected between each input signal and the
VTERM termination voltage as shown in Figure 4.
ENABLE
POS_IN
+
RCVR
OUT
-
NEG_IN
70 Ohms
70 Ohms
PTERM_ON
NTERM_ON
VTERM
Figure 4. DIFFERENTIAL INPUT
The positive and negative termination resistors can be independently turned off to allow the use of
external termination resistors. The differential voltage swing can be centered anywhere from VCC minus
3.5 volts to VCC minus 1 volt. The peak to peak differential swing can be as little as 0.5 volts. This is
intended to be compatible with PECL signal sources (ECL chips which have been connected between 5
volts and ground rather than from ground to minus 5 volts). The termination voltage for PECL logic should
be VCC minus 2 volts.
NOTE:
Care must be taken to insure that the VTERM voltage is always
between VCC and ground, even during power up. The VTERM pins on the chip
may be destroyed if the VTERM voltage exceeds these limits.
If single ended operation is desired, then the negative termination resistors should be turned off and
the unused pins forced to the middle voltage of the differential swing. The clock has independent termination
controls so that it can be differential while the data and sync are single ended. The VTERM voltage should
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be grounded if the internal terminators are not being used. TTL voltage levels can be used in the high speed
mode by setting the negative inputs to 1.5 volts so that the TTL input swing from 0.5 to 2.5 volts on the
positive inputs would toggle the differential receivers.
In the complex data input mode the HSI, HSI, HCK and HCK inputs are unused and the I and Q
pins are standard TTL inputs. The HSI, HSI, HCK and HCK pins and the VT pins should be grounded.
The data mux shown in Figure 2 outputs either the complex input data, the even/odd high speed
data or the diagnostic ramp from the sync counter circuit. The data mux output is sent to the mixer circuit.
2.5
MIXER
The mixer multiplies the pairs of samples from the input format circuit by sines and cosines and
outputs the results to the output format and the symbol offset circuits. A block diagram of the mixer circuit
is shown in Figure 5.
Round
Enable
Adder
Clear
Add
2X Gain
DC_I_IN
12 Bits
From
12 Bits
Input Format ACOS
DC_Q_IN
Circuit
XQ 12 Bits
(odd)
BSIN
Ieven
12 Bits
Qodd
12 Bits
12 Bits
ASIN
SI
Symbol
Data To
Symbol Offset
Circuit
Qeven
12 Bits
12 Bits
DC_Q_OUT
12 Bits
BCOS
12 Bits
12 Bits
DC_I_OUT
SYMBOL
GAIN
XI 12 Bits
(even)
12 Bits
SQ
Iodd
12 Bits
Figure 5. MIXER
The ACOS, BCOS, ASIN and BSIN values are generated by the NCO circuit. In the complex mode
BCOS will equal ACOS and BSIN will equal minus ASIN. In the high speed mode the ASIN and ACOS
values are the even time sine/cosine pairs and the BCOS and BSIN values are the odd time pairs. The lower
11 bits of the 23 bit multiplier products are either rounded off or truncated depending upon the state of the
round enable control. The rounding is performed using the “round to even” technique1. The 12 bit products
are passed to the output format circuit.
The adders sum the individual products to generate complex products. The adder outputs are
saturated to 12 bits if the add causes overflow. The adder outputs pass through a gain circuit and then to
the symbol offset circuit. The gain circuit, if it is enabled, doubles the data values. The gain outputs are
saturated to plus or minus full scale if the gain causes overflow2. The adder clear control allows the Ieven
and Qeven mixer outputs, instead of the complex products, to be passed to the symbol gain circuit. This
1. When the fraction to be rounded is exactly 1/2, the round to even technique rounds up when the integer portion is odd and rounds
down when it is even. This removes any DC bias in the rounding.
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permits the user to capture the high speed mode’s even outputs in the snapshot RAM, or to use them in the
phase error lookup circuit.
DC components before or after the mixer can be removed by adjusting the DC_I_IN, DC_Q_IN,
DC_I_OUT and the DC_Q_OUT values. These values are added to the input and output data as shown in
Figure 5. The outputs from these adders are saturated to plus or minus full scale (12 bits) if overflow is
detected.
2.6
SYMBOL ALIGN
The symbol align circuit is used in the carrier removal mode to process offset (or staggered) QPSK
signals. The offset is removed by delaying the SI sample by one clock cycle so that it is paired with the next
SQ sample. Every other SI and SQ pair is held for two clock cycles, effectively decimating the sample rate
by two. The symbol offset circuit is controlled by the OFFSET and OFFSET_HOLD control bits described
in Section 4.1 The symbol offset circuit is synchronized by the OFFSET_SYNC described in Section 4.2.
2.7
PHASE ERROR RAM
The the I and Q samples are passed to the phase error RAM. The phase error RAM uses the upper
7 bits of the I and Q values to look up the sign of the phase error for the sample. The phase error RAM
contents are downloaded through the control interface. The phase error RAM outputs a 1 or a 0 depending
upon whether the phase angle of the (I, Q) complex pair is greater than or smaller than the nearest decision
point for the signal’s constellation pattern. A “0” means that the phase angle needs to be increased to match
the decision point and a “1” means it needs to be decreased. A block diagram of the phase error RAM circuit
is shown in Figure 6.
C[0:15]
QMAP_ROUND
QMAP_ENABLE QMAP_INVERT
Enable
6/7 Bits
12 Bits
Enable
7 Bits
Q
From
Symbol
Offset
ROUND
Mode
UNSIGNED
MAGNITUDE
6 Bits
R[2:7]
W[0:7]
A[0:7]
sign
256 BY 16
RAM
Enable
6/7 Bits
12 Bits
ROUND
I
Enable
7 Bits
Mode
UNSIGNED
MAGNITUDE
6 Bits
2 MSBs
R[0:1]
WE
sign
A8*CS*R/W
16 Bits
QMAP_ENABLE
4 LSBs
16 TO 1
MUX
PHASE
ERROR
Figure 6. PHASE ERROR RAM
The round circuit rounds the 12 bit I and Q samples into the upper 6 or 7 bits, or, if rounding is
disabled, truncates them. If the quadrant map (Qmap) mode is enabled the circuit rounds to 7 bits, otherwise
it rounds to 6 bits. The rounding is performed using the round to even technique.
2. The input samples of QAM signals have an extra sign bit before the carrier is removed. The extra sign bit is needed because the
square QAM constellation is spinning. Once carrier has been removed the extra sign bit can be removed by the gain circuit. This
increases the resolution of the phase error RAM and simplifies the symbol mapping.
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The rounded bits are passed to the unsigned magnitude circuit where, if Qmap is enabled, they are
converted from 7 bit 2’s complement signed numbers to 6 bit unsigned numbers. The conversion is
performed using 2’s complement negation unless the invert control is set. If the invert control is set, then the
negation is performed by inverting the data bits (i.e., a 1’s complement negation is used).
If Qmap is enabled the circuit outputs the 6 bit magnitude and the sign bit. If Qmap is turned off the
circuit outputs the 6 bit signed number from the round circuit.
The Qmap mode is used to map the I, Q complex pair into one quadrant for looking up the phase
error. This is possible when the signal’s constellation pattern has quadrant symmetry. If the pattern does
not exhibit symmetry, then the quadrant map mode should not be used.
The 6 bit I and Q values are used to lookup the phase error in a 4096 by 1 bit memory. In the Qmap
mode the phase error is inverted as necessary to map it back into the proper quadrant.
The memory is implemented using a 256 word by 16 bit RAM as shown in Figure 6. The RAM is
loaded as 256 sixteen bit words mapped to addresses 256 to 511 of the control interface. The RAM is a
write only memory.
The phase error is passed to the phase lock loop (PLL) circuit. The phase error is also output on
the EOUT pin of the chip for external use.
2.8
PHASE LOCK LOOP
The phase error drives the PLL circuit shown in Figure 7.
2-A or Clear
External
32 BITS
Phase
Increment
To NCO
32 BITS
Error From
Phase RAM
FREQUENCY
(32 BITS)
32 BIT ERROR ACCUMULATOR
LATCH
External
Error Input
PLL Sync
2-B or Clear
16 MSBs
MUX
To
Control
Interface
phase_hold
Figure 7. PLL CIRCUIT
The phase error can either come from an input pad or from the phase error RAM. The error is
multiplied by the two constants 2-A and 2-B. These multipliers treat a phase error of “0” as +1 and a phase
error of “1” as -1. The multipliers also have a clear mode so that 2-A or 2-B can be set to zero.
The tracking bandwidth and damping of the of the phase lock loop filter are set using the constants
A and B. The filter will be critically damped when A is approximately one-half of B. When critically damped
the tracking bandwidth and residual phase jitter of the loop are set by B. A small value for B results in a wide
bandwidth with lots of jitter, but fast acquisition. A large value of B narrows the bandwidth and reduces the
residual jitter, but increases the initial acquisition time. Values of B between 24 and 31 are suggested. Use
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GC3021 MIXER AND CARRIER REMOVAL CHIP
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24 for initial acquisition and 31 for final tracking. The values of A and B are double buffered so that the loop
bandwidth can be changed synchronous to an external sync signal.
Initial acquisition can be greatly aided by presetting the PLL to an estimated frequency offset. This
is done by loading the frequency register with the estimated frequency.
In the mixer mode the PLL is turned off by clearing 2-A and 2-B, clearing the accumulator and setting
the frequency register to the desired tuning frequency. The 32 bit frequency word is set to the desired
Frequency 32
frequency using the formula:
FREQ = ----------------------------- 2
, where “Frequency” is the desired
Clock Rate
frequency and “Clock Rate” is the chip’s clock rate. The frequency register is double buffered so that
frequency changes can be made synchronous to external sync signals.
The upper 16 bits of the current phase increment is monitored by the phase increment register. The
register tracks the current phase increment when the “hold” control is low and holds the last value when
“hold” is high. The user may wish to monitor the phase increment in order to reinitialize the PLL after a loss
of signal, or to determine when carrier lock has been achieved.
2.9
NCO
The PLL circuit generates a phase increment word which is used by the NCO to generate a
sine/cosine sequence at the desired tuning frequency. The NCO circuit accumulates the phase and uses
the upper 13 bits of the 32 bit accumulator to lookup 12 bit sines and cosines. A block diagram of the NCO
circuit is shown in Figure 8.
NCO Sync
Dither
Sync
12 Bits
PHASE
INCREMENT
13 Bits
TRIG
TABLE
12 Bits
32 BIT PHASE ACCUMULATOR
12 Bits
DIVIDE BY 2
ACOS
ASIN
DITHER
CIN
17 Bits
17 Bits
13 Bits
TRIG
TABLE
Clear
12 Bits
BCOS
BSIN
Negate Sine
High Speed
Mode
Figure 8. NCO CIRCUIT
The accumulator output plus one half the phase increment is used in the high speed mode1 to look
up the BCOS and BSIN values. This generates the proper “odd time” sine/cosine values needed in the high
speed mode. The tuning range in the high speed mode is limited to +/- FIN/4, where FIN is thehigh speed
input data rate. To tune to frequencies above FIN/4, the user must negate the odd-time output samples (both
I and Q). This mixes the output down by FIN/2. For example, to mix down the frequency 0.3IN, the user
should set the tuning frequency to +0.2FIN, and then negate the odd-time output data to give a final tuning
of (0.2FIN - 0.5FIN) = -0.3FIN.
1. The high speed mode is the double rate real input mode, see Section 2.4
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The dither circuit adds a random value to the upper 17 bits of the accumulator output. The random
number sequence is initialized to zero by the dither sync input. The dithering can be turned off by forcing
the sync to be active. The BSIN output is negated if the high speed mode is not enabled.
2.10
SNAPSHOT RAM
The snapshot RAM is used to store blocks of 64 mixer and NCO outputs. The mixer outputs are the
SI and SQ outputs shown in Figure 5. The NCO samples are the ACOS and ASIN values shown in Figure
5. The NCO samples are delayed to match the pipeline delay from the XI and XQ inputs to the SI and SQ
outputs. The snapshot can be programmed to store every sample, every other sample, every third sample,
or every fourth sample. The rate control is primarily used when capturing samples of offset-QPSK data
which is processed by the chip at twice the baud rate. Only every other sample of the offset-QPSK sample
is of interest.
The snapshot can be triggered by the input syncs, the delayed input syncs, the sync counter’s
terminal count or the snap sync input. Once triggered, the snapshot start time can be delayed by up to 256
sample clocks, where the sample clock rate is dependant upon the snapshot rate control.
The snapshot RAM is a read only memory which is read using addresses 256 through 511 of the
control interface. Addresses 256 through 319 read SI, addresses 320 through 383 read SQ, addresses 384
through 447 read ASIN, and addresses 448 through 511 read ACOS. The 12 bit values are sign extended
to 16 bits in the control interface.
2.11
OUTPUT FORMAT
The chip has four 12 bit output ports labeled YA, YB, YC, and YD. Each port can be individually
configured to output mixer results (Ieven, Qeven, Iodd, Qodd), or symbol and NCO samples. The symbol and
NCO samples are the snapshot RAM inputs (SI, SQ, sine, cosine). The output selection is shown in Table
1 below:
Table 1: OUTPUT SELECTION
OUTPUT
PORT
OUTPUT SELECT
0
1
YA
Ieven
SI
YB
Qeven
SQ
YC
Iodd
cosine
YD
Qodd
sine
The YA, YB, YC and YD outputs can be rounded to 12, 10 or 8 bits and can be masked to a desired
number of bits through the use of four 12 bit mask words. The masks are bitwise ANDed with the output
words to selectively clear the output bits.
Output enable controls are provided to individually turn off these outputs.
GRAYCHIP, INC.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
2.12
DATA SHEET
DATA DELAYS
The data delay through the chip in input clock cycles is shown in Table 2 below.
Table 2: DATA DELAYS
2.13
FROM
TO
DELAY
MODE
I, Q
SI, SQ
15
OUTSEL=1
I, Q
I, Q (even/odd)
13
OUTSEL=0
POWER DOWN AND KEEP ALIVE CIRCUIT
This circuit is used to either power down the chip or to prevent excess power consumption when
the external clock is disconnected. In the power down mode the circuit selects a 1 KHz internal oscillator as
the chip’s internal clock, thereby reducing the chip’s power consumption down to a few milliwatts. In the
keep alive mode the chip detects when the clock has been inactive for one or two milliseconds and then
switches to the 1 KHz internal oscillator. This ensures that the chip’s internal dynamic nodes do not float to
middle voltages, a condition which can cause excessive power draw.
2.14
DIAGNOSTICS
The sync counter can be used as an input sync and data source in order to perform diagnostics.
The diagnostic outputs are captured in the snapshot RAM and compared with predicted results. The whole
chip except for the I/O pads, the high speed input circuit and the output format circuit can be checked this
way. Section 6.6 tabulates the diagnostic configurations and their expected snapshot outputs.
GRAYCHIP, INC.
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GC3021 MIXER AND CARRIER REMOVAL CHIP
PACKAGING
54
56
58
60
63
65
67
69
72
74
76
78
55
57
59
61
64
66
68
70
73
75
77
79
41
40
39
38
37
33
34
10
49
50
51
52
103
102
101
100
98
96
95
94
91
90
88
87
86
85
84
83
120
117
116
115
114
113
112
111
110
107
106
(MSB)YA11
YA10
YA9
YA8
YA7
YA6
YA5
YA4
YA3
YA2
YA1
YA0
I11 (MSB)
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
Q11 (MSB)
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
EIN
CIN
(MSB)YB11
YB10
YB9
YB8
YB7
YB6
YB5
YB4
YB3
YB2
YB1
YB0
(MSB)YC11
YC10
YC9
YC8
YC7
YC6
YC5
GC3021
YC4
YC3
YC2
YC1
YC0
SA
SB
SN
CKENB
CKENA
CK
HCK
HCK
(MSB)YD11
YD10
YD9
YD8
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
HSI
HSI
C15 (MSB)
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
122
123
124
125
128
129
130
131
132
133
134
135
139
140
141
142
143
144
145
146
149
150
151
152
154
155
156
157
160
1
4
5
6
7
8
9
15
16
17
18
19
20
22
24
27
28
29
31
EOUT
42
SO
43
HCKO
47
0.2 mm
(0.008")
3.7mm
(0.1457")
31.9mm
(1.2559")
120
0.3 mm
(0.0118")
0.65mm
(0.02559")
81
121
80
28 mm
(1.102")
3.0
DATA SHEET
GRAYCHIP
GC3021-PQ
160
41
1
40
160 PIN PLASTIC QUAD FLAT PACK CHIP CARRIER
VCC PINS: 3,12,13,23,26,32,36,44,48,81,89,93,97,104,108,118,126,136,147,158
GND PINS: 2,11,21,25,30,35,45,46,82,92,99,105,109,119,127,137,148,159
VTERM PINS: 53, 62, 71, 80
NOTE: 0.01 to 0.1 µf DECOUPLING CAPACITORS SHOULD BE PLACED
AS CLOSE AS POSSIBLE TO THE MIDDLE OF EACH SIDE OF THE CHIP
A8 (MSB)
A7
A6
A5
A4
A3
A2
A1
A0
R/W
CS AOE BOE
121
GRAYCHIP, INC.
138
COE
153
DOE
14
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
3.1
DATA SHEET
PIN DESCRIPTIONS
SIGNAL
DESCRIPTION
I[0:11]
IN-PHASE INPUT DATA. Active high
The 12 bit two’s complement input samples for the I half of the
complex input. New samples are clocked into the chip on the rising
edge of the clock. In the high speed mode this is the positive rail
of the differential PECL inputs.
Q[0:11]
QUADRATURE INPUT DATA. Active high
The 12 bit two’s complement input samples for the Q-half of the
complex input. New samples are clocked into the chip on the rising
edge of the clock. In the high speed mode this is the negative rail
of the differential PECL inputs
CIN
NCO CARRY INPUT. Active high
The carry input to the phase accumulator in the NCO. The CIN
input can be used to increase the tuning resolution of the NCO.
This signal is clocked into the chip on the rising edge of the clock.
The CIN input is cleared by the chip during diagnostics.
EIN
PHASE ERROR INPUT. Active high
This input can be used as the error input into the PLL circuit. This
signal is clocked into the chip on the rising edge of the clock.
SA,SB
SYNC INPUTS. Active low
The sync inputs to the chip. All timers, accumulators, and control
counters are, or can be, synchronized to these syncs. The syncs
are clocked into the chip on the rising edge of the clock.
SN
SNAPSHOT SYNC. Active low
The snapshot sync is provided to synchronously start the data
snapshot. This signal is clocked into the chip on the rising edge of
the clock.
CK
CLOCK INPUT. Active high
The clock input to the chip. The I, Q, SA, SB, SN, CKENA,
CKENB, EIN and CIN signals are clocked into the chip on the
rising edge of this clock. The YA, YB, YC, YD, EOUT and SO
signals are clocked out on the rising edge of this clock.
CKENA, CKENB
CLOCK ENABLE INPUTS. Active low
The clock enable inputs to the chip. These signals are gated with
CK to generate the chip’s internal clock. CKENA and CKENB are
clocked into the chip on the rising edge of CK and will enable or
disable the following clock edge. A low level on both CKENA and
CKENB enables the clock edge.
YA[0:11]
YB[0:11]
YC[0:11]
YD[0:11]
YA OUTPUT DATA. Active high
YB OUTPUT DATA. Active high
YC OUTPUT DATA. Active high
YD OUTPUT DATA. Active high
These pins output the complex mixer or symbol outputs. The bits
are clocked out on the rising edge of the clock.
AOE,BOE,COE,DOE
OUTPUT ENABLES. Active low
The YA, YB, YC and YD output pins are put into a high impedance
state when these pins are high. AOE controls the YA output pins.
BOE controls the YB output pins. COE controls the YC output
pins. DOE controls the YD output pins.
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GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
EOUT
PHASE ERROR OUT. Active high
The phase error RAM output is clocked out of the chip on this pin.
This signal is made available mostly for diagnostic purposes.
SO
SYNC OUT. Active low
This signal is either one of the input syncs, a reclocked version of
HSI, the one shot sync OS, or the internal counter’s terminal count
strobe TC.
C[0:15]
CONTROL DATA I/O BUS. Active high
This is the 16 bit control data I/O bus. Control register contents are
loaded into the chip or read from the chip through these pins. The
chip will only drive these pins when CS is low and R/W is high.
A[0:8]
CONTROL ADDRESS BUS. Active high
These pins are used to address the control registers, phase error
RAM and the snapram memory within the chip.
R/W
READ/WRITE CONTROL. High for read, low for write
This pin determines if the control bus cycle is a read or write
operation. The pin is high for a read and is low for a write.
CS
CONTROL STROBE. Active low
This control strobe enables the read or write operation. The
contents of the register or memory location selected by A[0:8] will
be output on C[0:15] when R/W is high and CS is low. If R/W is
low when CS goes low, then the selected register will be loaded
with the contents of C[0:15].
HCK,HCK
HIGH SPEED CLOCK INPUT. Active high
The differential PECL clock used in the high speed mode to clock
in the double rate real data.
HSI,HSI
HIGH SPEED SYNC INPUT. Active high
The differential PECL sync input used in the high speed mode to
synchronize the input format circuit.
HCKO
HS/2 CLOCK OUTPUT. Active high
The high speed clock is divided by two and output on this pin. The
HCKO clock should be buffered if it is to be used by other circuits.
The buffered version of HCKO should be used as the CK input to
the chip.
VTERM
TERMINATION SUPPLY VOLTAGE. Fixed voltage
The termination supply pins, The I, Q, HCK, HCK, HSI and HSI
pads have switchable 70 Ohm termination resistors tied to
VTERM. The VTERM voltage must not exceed VCC or be less
than GND.
VCC
SUPPLY VOLTAGE. Fixed voltage
The power supply pins.
GND
CHIP GROUND. Fixed voltage
The power supply ground pins.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.0
DATA SHEET
CONTROL REGISTERS
The chip is configured and controlled through the use of 14 sixteen bit control registers. These
registers are accessed for reading or writing using the control bus pins (CS, R/W, A[0:8], and C[0:15])
described in the previous section. The register names and their addresses are:
ADDRESS
NAME
ADDRESS
NAME
0
MODE_REG
8
OUTPUT_REGA
1
SYNC_REG0
9
OUTPUT_REGB
2
SYNC_REG1
10
OUTPUT_REGC
3
DELAY_REG
11
OUTPUT_REGD
4
COUNTER_REG0
12
SNAP_REG
5
PLL_REG
13
PHASE_REG
6
FREQ_REG0
14
ONE_SHOT
7
FREQ_REG1
15
TEST_OUT
16
DC_I_IN
17
DC_Q_IN
18
DC_I_OUT
19
DC_Q_OUT
20 to 255
unused
256 to 511
Snapshot memory (read only)
256 to 511
Phase Error memory (write only)
The DC offset registers contain two’s complement values. Only the 12 LSBs are used.
The following sections describe each of these registers. The type of each register bit is either R or
R/W indicating whether the bit is read only or read/write. All bits are active high.
Suggested default settings for using the chip in carrier removal applications is given for each
register.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.1
DATA SHEET
MODE CONTROL REGISTER
This register contains the mode control bits. The suggested default value is 5280 (HEX).
ADDRESS 0:
MODE_REG
BIT
TYPE
NAME
DESCRIPTION
0,1 (LSBs)
R/W
INPUT[0:1]
This two bit field controls the input data selection. The
input modes are:
INPUT
DESCRIPTION
0
Complex data input
1
High speed real data input
2
Diagnostic ramp input
3
Zero input
2
R/W
REC_ENABLE
Turns on the differential receivers. The high speed input
data and clock signals are cleared when this bit is low.
3
R/W
PTERM_ENABLE
Turns on the termination resistors to VTERM for the
positive rail (I) data and HSI inputs.
4
R/W
NTERM_ENABLE
Turns on the termination resistors to VTERM for the
negative rail (Q) data and HSI inputs.
5
R/W
PCK_ENABLE
Turns on the termination resistor to VTERM for HCK.
6
R/W
NCK_ENABLE
Turns on the termination resistor to VTERM for HCK.
7
R/W
MIXER_ROUND
Round the mixer multiplier products to 12 bits. The
products are truncated to 12 bits if this control is low.
8
R/W
ADDER_CLEAR
Clears one input to the adder in the mixer circuit to allow
the Ieven and Qeven outputs to be routed to the symbol
offset circuitry. See Section 2.5.
9
R/W
2X_GAIN
Enables the 2X gain circuit in the mixer circuit.
10
R/W
OFFSET
Delays the I sample in the symbol offset circuit by one
clock cycle relative to the Q sample.
11
R/W
OFFSET_HOLD
Samples and holds every other I,Q pair in the symbol
offset circuit. The OFFSET_SYNC mode (See Section
4.2) determines how the sample and hold timing is
synchronized to the input data.
12
R/W
QMAP_ENABLE
Enables the quadrant map mode. This mode maps the
I,Q pairs into the first quadrant for phase error lookup
when this mode is selected. The error is then mapped
back to the correct quadrant after it is looked up in the
phase error memory.
13
R/W
QMAP_ROUND
Round instead of truncate the I,Q samples in the phase
error circuit. If QMAP_ENABLE is set the values are
rounded into the 7 MSBs, otherwise they are rounded to
the 6 MSB.
14
R/W
QMAP_INVERT
Convert negative numbers to positive numbers in the
Qmap mode by inverting the data bits (1’s complement
negation) rather than negating them.
15
R/W
NCO_MODE
Turns on the high speed NCO mode. Must be high for
the high speed double rate input mode, low otherwise.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.2
DATA SHEET
SYNC CONTROL REGISTERS
Control registers SYNC_REG0 and SYNC_REG1 determine how the circuits within the chip are
synchronized. Each circuit which requires synchronization can be configured to be synchronized to the sync
inputs (SA and SB), to the delayed versions of these syncs (DSA and DSB), to the terminal count of the
internal counter (TC), or to the one-shot strobe (OS). The sync to each circuit can also be set to be always
on or always off. Each circuit is given a three bit sync mode control which is defined as:
Table 3: SYNC MODES
MODE
SYNC DESCRIPTION
0
“0” (never asserted)
1
SA
2
SB (or HSO if USE_HSO is set)
3
DSA
4
DSB (or HSO if USE_HSO is set)
5
TC
6
OS
7
“1” (always asserted)
NOTE: the internal syncs are active high. The SA and SB inputs have been inverted to be the active
high syncs SA and SB.
The suggested default setting for SYNC_REG0 is to sync everything to SA, value = 0249 (HEX).
ADDRESS 1:
SYNC_REG0
BIT
TYPE
NAME
DESCRIPTION
0-2 (LSBs)
R/W
COUNT_SYNC
The counter sync selection
3-5
R/W
OUTPUT_SYNC
The selected sync is inverted and output on the SO pin.
6-8
R/W
OFFSET_SYNC
The symbol offset sync.
9-11
R/W
SNAP_SYNC
The snapshot memory can be triggered by this sync.
12
R/W
USE_HSO
Use the HSO sync (See Section 2.4) for the SB sync.
13
R/W
USE_CLK_EN
The clock enables CKENA and CKENB are ignored
when this bit is low.
14,15
R/W
POWER_DOWN
These bits control the power down and keep alive circuit.
POWER_DOWN
MODE
0
Keep alive
1
Power down
2
Off
3
Test
The USE_CLK_EN and POWER_DOWN bits initialize to zero upon power up. This puts the chip in
the keep alive mode to prevent a current surge if there is no clock provided. See Section 2.13 for details.
GRAYCHIP, INC.
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GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
The suggested default value for SYNC_REG1 is 7DF7 (HEX) which is to always sync AB_SYNC,
FREQ_SYNC and DITHER_SYNC (turns dithering off) and to sync PLL_SYNC and NCO_SYNC with the
oneshot strobe.
ADDRESS 2:
SYNC_REG1
BIT
TYPE
NAME
DESCRIPTION
0-2 (LSBs)
R/W
AB_SYNC
The PLL circuit accepts new A and B values when the
sync is asserted.
3-5
R/W
PLL_SYNC
The PLL accumulator is cleared by this sync.
6-8
R/W
FREQ_SYNC
The PLL accepts the new FREQ value from the FREQ
registers when this sync is asserted.
9-11
R/W
NCO_SYNC
The NCO accumulator is cleared by this sync.
12-14
R/W
DITHER_SYNC
The dither value circuit is cleared by this sync.
15 (MSB)
R/W
-
unused
4.3
DELAY CONTROL REGISTER
The DSA and DSB syncs are generated by delaying the SA and SB sync inputs by (2+DELAY)
clocks where DELAY ranges from 0 to 255. The suggested default is zero.
ADDRESS 3:
DELAY_REG
BIT
TYPE
NAME
DESCRIPTION
0-7 (LSBs)
R/W
DELAY_A
The DELAY value for DSA.
8-15 (MSBs) R/W
DELAY_B
The DELAY value for DSB.
4.4
COUNTER CONTROL REGISTER
The internal counter counts in cycles of 16*(COUNT+1) clocks by counting down from
(16*COUNT+15) to zero and starting over again. The counter emits a terminal count (TC) each time it
reaches zero. The suggested default is 00FF (HEX) which sets a counter cycle of 4096.
ADDRESS 4:
COUNT_REG
BIT
TYPE
NAME
DESCRIPTION
0-15
R/W
COUNT
The counter period is 16*(COUNT+1) clocks.
GRAYCHIP, INC.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.5
DATA SHEET
PLL CONTROL REGISTER
The phase lock loop (PLL) phase hold control and filter coefficients are stored in this register. The
suggested default is 028A (HEX) which sets A=10 and B=20 for acquisition, and 038e (HEX) which sets
A=14 and B=28 for tracking.
ADDRESS 5:
PLL_REG
BIT
TYPE
NAME
DESCRIPTION
0-4
R/W
A[0:4]
The 5 bit “A” coefficient. See Figure 7. The phase error
is multiplied by 2-A for A equal to 1 through 31, and is
multiplied by 0 for A equal to 0.
5-9
R/W
B[0:4]
The 5 bit “B” coefficient. See Figure 7. The phase error
is multiplied by 2-B for B equal to 1 through 31, and is
multiplied by 0 for B equal to 0.
10
R/W
EXT_ERROR
Use the EIN input as the error input to the PLL circuit.
EIN = 0 adds to the phase, EIN = 1 subtracts.
11-14
R/W
-
unused
15 (MSB)
R/W
PHASE_HOLD
The phase register tracks the value of the phase
increment when this bit is low and holds the last value
when this bit is high.
The A and B coefficients stored in this register are not used until the AB_SYNC is asserted as
described in Section 4.2.
4.6
FREQUENCY WORD REGISTERS
Registers 6 and 7 contain the 32 bit frequency tuning word. The frequency word is added into the
PLL output as shown in Figure 6. Bit 0 is the LSB, bit 31 is the MSB. The suggested default is zero.
ADDRESS 6:
FREQ_REG0
BIT
TYPE
NAME
DESCRIPTION
0-15
R/W
FREQ[0:15]
16 LSBs of the frequency word
ADDRESS 7:
FREQ_REG1
BIT
TYPE
NAME
DESCRIPTION
0-15
R/W
FREQ[15:31]
16 MSBs of the frequency word
The tuning frequency is specified using the formula:
Frequency 32
FREQ = ----------------------------- 2
Clock Rate
where “Frequency” is the desired tuning frequency, and “clock rate” is the chip’s clock rate. The FREQ value
stored in these registers are transferred to the PLL circuit when the FREQ_SYNC is asserted as described
in Section 4.2.
GRAYCHIP, INC.
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JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.7
DATA SHEET
OUTPUT CONTROL REGISTERS
Registers 8, 9, 10 and 11 contain the four output format control words. Each register is identical.
OUTPUT_REGA controls output YA, OUTPUT_REGB controls output YB, OUTPUT_REGC controls output
YC and OUTPUT_REGD controls output YD. The suggested default is 1FFF.
ADDRESS 8:
ADDRESS 9:
ADDRESS 10:
ADDRESS 11:
OUTPUT_REGA
OUTPUT_REGB
OUTPUT_REGC
OUTPUT_REGD
BIT
TYPE
NAME
DESCRIPTION
0-11
R/W
MASK
12 Bit output mask. MASK is bitwise anded with the
output sample. Bit 0 is the LSB, bit 11 is the MSB.
12
R/W
OUTPUT_SEL
Selects which signal is output on this port. See
Table 2 in Section 2.11.
13
R/W
RND_8
Round to 8 bits
14
R/W
RND_10
Round to 10 bits
15
R/W
-
Unused
The RND_8 and RND_10 controls are used to round the 12 bit output values to 8 or 10 bits. Only
one control should be high.
GRAYCHIP, INC.
- 20 -
JUNE 22, 1998
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GC3021 MIXER AND CARRIER REMOVAL CHIP
4.8
DATA SHEET
SNAPSHOT CONTROL REGISTER
Registers 12 controls the snapshot memory. The suggested default is 0002 (HEX).
ADDRESS 12:
SNAP_REG
BIT
TYPE
NAME
DESCRIPTION
0,1 (LSB)
R/W
TRIGGER
This control sets the trigger condition which will start a
snapshot once the ARMED bit is set. The trigger
conditions are to start:
TRIGGER
DESCRIPTION
0
immediately,
1
when the SN strobe is received,
2
when the SNAP_SYNC is received
(See Section 4.2),
3
never
2
R/W
ARMED
The user sets this bit to arm the snapshot memory
so that it will start on the next trigger condition. The
chip clears this bit when the trigger occurs.
3
R/W
DONE
This bit goes high when the snapshot is complete.
4,5
R/W
SNAP_RATE
Determines the rate at which samples are stored
according to:
SNAP_RATE DESCRIPTION
0
every clock, full rate samples
1
every other clock, half rate samples
2
every 3rd clock, third rate samples
3
every 4th clock, quarter rate samples.
6,7
R/W
-
unused
8-15 (MSB)
R/W
SNAP_DELAY
Delay from snapshot trigger until the start of snapshot.
The delay is:
SNAP_DELAY*(SNAP_RATE+1)
clock cycles where SNAP_DELAY ranges from 0 to 255.
4.9
PHASE REGISTER
Register 13 is a read only register used to monitor the upper 16 bits of the NCO’s phase increment.
See PHASE_HOLD in Section 4.5.
4.10
ONE SHOT ADDRESS
The one shot pulse is generated on the OS pin by writing to address 14. This is a write-only address.
The data written to it is irrelevant.
4.11
TEST OUTPUT REGISTER
Register address 15 is a read only port used to monitor the keep alive clock (bit 0) and keep alive
status (bit 1). The status bit is high if the internal 1 kHz clock is being used by the chip.
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GC3021 MIXER AND CARRIER REMOVAL CHIP
5.0
SPECIFICATIONS
5.1
ABSOLUTE MAXIMUM RATINGS
DATA SHEET
Referenced to GND:
PARAMETER
MIN
VCC
DC Supply Voltage
-0.3
7
V
VTERM
Termination Voltage
0
VCC
V
VIN
Input voltage (undershoot and overshoot)
-0.7
VCC+0.7
V
TSTG
Storage Temperature
-65
150
°C
FCK
Clock Rate
5.2
TYP
MAX
UNITS
10
Hz
RECOMMENDED OPERATING CONDITIONS
PARAMETER
VCC
DC Supply Voltage
TA
Temperature Ambient, no air flow
5.3
MIN
TYP
3.0
5.0
MAX
0
UNITS
6.0
V
70
°C
DC CHARACTERISTICS
All parameters are at VCC=5V and temperature is 0 to 70 °C ambient unless noted
PARAMETER
5.4
VIL
Voltage input low
VIH
Voltage input high
IIN
Input current (Terminations off)
VOL
Voltage output low (IOL = 4mA)
VOH
Voltage output high (IOH = -4ma)
MIN
TYP
MAX
UNITS
0.8
V
VCC=5V
2.0
V
VCC=3.3V
1.5
V
µA
+/-50
0.5
V
VCC=5V
2.5
5
V
VCC=3.3V
1.5
3.3
V
CIN
Data input capacitance (All inputs except CK and C[0:15])
CCK
Clock input capacitance (CK input)
CCON
Control data capacitance (C[0:15] I/O pins)
4
pF
10
pF
6
pF
AC CHARACTERISTICS
Commercial temperature range (0 to 70°C), VCC +/- 5%, unless noted.
GRAYCHIP, INC.
- 22 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
PARAMETER
FCK
Clock
tCKL
DATA SHEET
MIN
frequency1
TYP
MAX
UNITS
VCC=
5v
3.3v
0.1
0.1
Clock low period (Below VIL)
VCC=
5v
3.3V
5
8
ns
tCKH
Clock high period (Above VIH)
VCC=
5v
3.3v
5
8
ns
tSU
Data setup (I,Q,SA, SB, SN, CKENA, or CKENB) before CK goes high
VCC= 5v
2
3.3v
4
ns
tHD
Data hold time after CK goes high
0
ns
tDLY
Data output delay (Y, EOUT, or SO) from CK2
VCC= 5v
3.3v
2
2
9
13
ns
5v
3.3v
2
2
5
5
ns
Tristate to data output delay (Y valid from OE)
VCC= 5v
3.3v
3
3
9
13
ns
Control setup before CS goes low
(A, R/W during read, and A, R/W, C during write)
5
ns
Control hold after CS goes high
(A, R/W during read, and A, R/W, C during write)
5
ns
30
ns
tDZ
tZD
tCSU
tCHD
Data to tristate delay (Y to hiZ from OE)
VCC=
80
45
MHz
tCSPW
Control strobe pulse width (Write operation)
tCDLY
Control output delay to C after CS goes low3
(Read operation)
30
ns
tCZ
Control tristate delay after CS goes high
10
ns
ICCQ
Quiescent supply current (VIN=0 or VCC, FCK=100Hz)
ICC
Supply current (FCK=50 MHz, VCC=5.0V)
µA
200
150
mA
VCC F CK
ICC (MAX) =  ------------  ----------- 150 mA
 5   50 M
1. The chip may not operate properly at clock frequencies below MIN and above MAX,
2. Capacitive output load is 20 pf. Delays are measured from the rising edge of the clock to the output level rising above VIH or falling
below VIL.
3. Capacitive output load is 80 pf.
GRAYCHIP, INC.
- 23 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
5.5
DATA SHEET
HIGH SPEED MODE SPECIFICATIONS
PARAMETER
MIN
VCC-3.5
TYP
MAX
UNITS
VMID
Differential middle voltage
VCC-1.0
VDELTA
Differential voltage swing (peak to peak)
FHCK
Clock frequency high speed input VCC=
5v
3.3v
0.1
0.1
tHCKL
High speed clock low period
VCC=
5v
3.3V
3
5
ns
tHCKH
High speed clock high period
VCC=
5v
3.3v
3
5
ns
tHSU
High speed data setup (I,Q,HSI, HSI) before HCK goes high
VCC= 5v
1
3.3v
2
ns
tHHD
High speed data hold time after HCK goes high
0
ns
tHCKD
High speed clock buffer delay HCKO to CK1
VCC= 5v
3.3v
0
0
0.5
V
V
160
90
7
?
MHz
ns
1. Allowable delay from HCKO output pin, through a buffer and then back to the CK input.
GRAYCHIP, INC.
- 24 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
6.0
APPLICATION NOTES
6.1
POWER AND GROUND CONNECTIONS
DATA SHEET
The GC3021 chip is a very high performance chip which requires solid power and ground
connections to avoid noise on the VCC and GND pins. If possible the GC3021 chip should be mounted on
a circuit board with dedicated power and ground planes and with at least two decoupling capacitors (0.01
and 0.1 µf) adjacent to each GC3021 chip. If dedicated power and ground planes are not possible, then the
user should place decoupling capacitors adjacent to each VCC and GND pair.
IMPORTANT
The GC3021 chip may not operate properly if these power and ground guidelines are violated.
6.2
STATIC SENSITIVE DEVICE
The GC3021 chip is fabricated in a high performance CMOS process which is sensitive to the high
voltage transients caused by static electricity. These parts can be permanently damaged by static electricity
and should only be handled in static free environments.
6.3
REDUCED VOLTAGE OPERATION
The power consumed by the GC3021 chip can be greatly reduced by operating the chip at the
lowest VCC voltage which will meet the application’s timing requirements.
6.4
HIGH SPEED MIXER
The GC3021 chip can be used with two GC2011 filter chips to implement a high speed quadrature
down converter capable of accepting data rates up to 160 MHz, tuning to a desired frequency and outputting
80 MHz complex data. A block diagram of the suggested configuration is shown below:
IEVEN
DATA
AND
CLOCK
INPUT
A
I/Q
HCK
GC3021
IODD
B
QEVEN
A
QODD
CK
HCKO
GC2011
I
GC2011
Q
B
BUF
Clock
Figure 9. HIGH SPEED MIXER EXAMPLE
The GC2011 Digital filter chips are used in a decimate by two, double rate in, full rate out mode.
GRAYCHIP, INC.
- 25 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
6.5
DATA SHEET
QAM DEMODULATOR
The GC3021 chip can be used for carrier removal high speed digital modems. Examples include
digital microwave links and HDTV systems. For details in using the GC3021 chips in a digital modem contact
GRAYCHIP for the application note: BUILDING DIGITAL PSK AND QAM DEMODULATORS, August 17,
1994.
6.6
DIAGNOSTICS
Eight diagnostic tests are defined on the following pages. Note that the CIN input to the chip must
be grounded.
GRAYCHIP, INC.
- 26 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test A
#
# This test uses odd parity map.
#
for (i=0;i<256;i++) write (base+i) odd_parity(i);
#
# where odd_parity(i) is 0x9669 if "i" contains an odd number of bits
# and is 0x6996 otherwise (e.g., base + 0 = 0x6996, base + 1 = 0x9669, etc)
# control register settings:
write 0 0x0002
write 1 0x0b6e
write 2 0x5fef
write 3 0x0000
write 4 0x00bf
write 5 0x0082
write 6 0x0000
write 7 0x0000
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0000
0x0000
0x0000
0x0000
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0xfa85 0xf800 0x01f0 0xf800
0xf800 0xfffc 0xf800 0x03d5
0x01f6 0x07ff 0x01fa 0x07ff
0x05b1 0x0745 0x05b5 0x074b
0x07ff 0x0000 0xfa34 0xf800
0x020b 0xf800 0xf800 0xf885
0xf800 0xfbe8 0xfde8 0xf800
0xfde3 0xf800 0xfddf 0xfffc
0xfa7d
0xf800
0x01fb
0x05bb
0xf800
0xfa1a
0xfde6
0x0605
0xf8f5
0x071f
0x07ff
0x0752
0xf894
0xfbec
0xf800
0x07ff
0xfa73
0x07ff
0x07ff
0x05c0
0xfdf0
0xfa16
0xfde3
0x07ff
0xfffc
0x07ff
0x0740
0x0757
0xf800
0xfbe9
0xf800
0x07b7
0xf800
0xfe09
0x07ff
0x07ff
0x05c8
0x07ff
0xfa11
0x07ff
0xfc36
0x07ff
0xfc1f
0xf8ba
0xf800
0xfbf3
0x07ff
0xfbdb
0xf800
0x01f1
0x07ff
0x07ff
0xf800
0xfa1e
0x07ff
0x07ff
0x03ca
0x07ff
0xfc1c
0xf8b4
0xfbfd
0xf882
0xfbe4
0x07ff
0xf800
0x01f3
0x07ff
0x07ff
0x0208
0x07ff
0x07ff
0x07ff
0x0708
0x0722
0xfc17
0xf8af
0x0767
0x07ff
0xfbe0
0x042b
0x07ff
0x01f8
0xfa51
0x07ff
0x07ff
0x07ff
0x07ff
0xfde1
0x07ff
0xfc23
0xf8c1
0xf8a8
0xfffc
0x07ff
0xfbdc
0xf848
0x0190
0xfb90
0xfb8d
0xfe6f
0x018e
0xfb8e
0xfe72
0xf959
0xfcf2
0xfa57
0x0762
0x07ff
0x05a8
0xfcf3
0xf89d
0xfcf2
0x06a8
0xf95c
0xfb8e
0xfe6f
0x0190
0xfe73
0xf959
0xf958
0xf89d
0xfcef
0x0762
0x07ff
0xfcf3
0x0002
0xfcf2
0xfa57
0x0191
0xf95c
0xfb8e
0xfe70
0xf95b
0xf828
0xf959
0xfe6f
0xf801
0xfffe
0x0763
0x07ff
0xf801
0xf89c
0xfcf3
0x030d
0xf828
0x0471
0x07d7
0xfe70
0xf958
0xf828
0xf958
0x06a5
0xfa57
0x0762
0x07ff
0x07ff
0xfa5a
0xf89c
0xfcf3
0x07ff
0x07d7
0x06a8
0xf95c
0xf829
0xf828
0xf95b
0x07d8
0xfb8f
0x0763
0xfa5a
0xfcef
0xffff
0x05a7
0x0764
0xfcf2
0x0763
0x0470
0x0473
0xf95b
0xf829
0x07d7
0x07d8
0xfb8f
0xfb90
0x0310
0xf89e
0xfcef
0xffff
0x0764
0x07ff
0x0763
0xfa5a
0x07d7
0x0473
0xf95b
0xf829
0x0472
0xfe72
0xfb8f
0xf829
0x0001
0xf801
0xfcf0
0xfffe
0x0002
0xfcf3
0x0764
0xf89c
0xfe73
0xf959
0xfe70
0xf829
0xfb90
0xfe72
0xfb90
0xfb8e
0xfa5a
0xfcef
0xfffe
0xffff
0x05a9
0xfcf3
0x0764
0xffff
GRAYCHIP, INC.
- 27 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test B
#
# use the odd parity map, see testA
# control register settings:
write 0 0x0202
write 1 0x0b6e
write 2 0x5fef
write 3 0x0000
write 4 0x00ff
write 5 0x0044
write 6 0xaaaa
write 7 0xeaaa
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0fff
0x0400
0x0001
0x0bff
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0xfe5c 0xfcd4 0x0622 0xfa8a
0x0170 0xfc4c 0xf9b0 0xfc52
0xf98e 0xfc4a 0x067c 0xfa94
0xf97e 0xfa42 0xf978 0xfa96
0x00d8 0x043c 0x069c 0x0450
0xfdee 0xf9c8 0xf900 0x0646
0xf8de 0xfce2 0x0260 0xfaa4
0x0750 0xf94e 0x02a4 0x02fa
0x018a
0xfeaa
0x0126
0xf94e
0xff42
0x06b8
0xf8c8
0x0766
0x0352
0x03a6
0x0388
0xfc96
0xfaa0
0x055c
0xf96e
0x02f2
0xf9c6
0x014a
0xfe80
0xf96e
0x00b0
0x0718
0x004a
0x0016
0xfaca
0xfa8e
0xfc16
0xfbd4
0x0560
0xfaa4
0x0558
0x0554
0xf800
0xfe40
0xf938
0xf800
0xfec4
0xfeaa
0xf86e
0xf800
0xfd72
0xf800
0xfd6a
0xfb76
0xf800
0xfb38
0xf800
0xfafe
0xf800
0xf960
0xf800
0xf800
0xf9dc
0xf892
0xf800
0xf800
0xf800
0xf800
0xf800
0xf800
0xf800
0xf800
0xf800
0xfebc
0xfe2a
0xf800
0xfe82
0xf8ee
0xf800
0xfa2c
0xf852
0xf800
0xf800
0xfd5e
0xfd9a
0xf800
0xf800
0xfca0
0xfb0c
0xfecc
0xf97a
0xfe62
0xfe78
0xf800
0xfee6
0xf800
0xff40
0xff6c
0xfbba
0xfb9a
0xfd64
0xfd62
0xfc6c
0xf800
0xfcf4
0xfd38
0x07fb
0xf805
0x0089
0x038b
0xf805
0xf8d5
0x0086
0xff7a
0xfaba
0x0794
0xfabc
0xfd70
0x0546
0xfd71
0x0793
0xfd70
0xff78
0x0088
0xff7a
0x038b
0xfc77
0x0088
0x072b
0x072b
0x0603
0x0793
0x0605
0x0603
0x0543
0x028f
0x0603
0xf86d
0xf805
0x07fb
0xf805
0x0086
0x07fb
0xfc77
0x0088
0xff77
0x0544
0xf86c
0xf86d
0x0793
0x0605
0xf9fb
0xfd70
0xf86d
0x0088
0xf805
0xf8d5
0x0389
0xf805
0xff7a
0xf805
0xf805
0xfd70
0xfd71
0xfabd
0xfaba
0xf9fb
0x0605
0xf9fb
0xf9fb
0xff78
0x0089
0x07fb
0x072b
0x0086
0x038b
0x07fb
0xf805
0x0603
0x028f
0x0605
0x0793
0xf9fd
0x0794
0x0290
0x0793
0xf805
0x07fb
0xf805
0x072b
0xf8d5
0x07fb
0xfc77
0xfc75
0x0546
0x0290
0x0544
0x0546
0xf9fa
0xf86c
0x0546
0xfd70
0x0088
0xff78
0x0086
0x07fb
0xff7a
0xf8d5
0x07fb
0xf805
0xf9fb
0xfd71
0xfd70
0x0290
0x0544
0xfabc
0x0793
0xfd70
0x07fb
0x0088
0x0389
0x072b
0x0089
0xf805
0x0089
0x0088
0x0793
0x0794
0x0606
0x0603
0xfabc
0x0544
0xfabc
0xfabc
GRAYCHIP, INC.
- 28 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test C
#
# use the odd parity map, see testA
# control register settings:
write 0 0x0e02
write 1 0x0b6e
write 2 0x5bff
write 3 0x0000
write 4 0x003f
write 5 0x0000
write 6 0xf0f0
write 7 0xf0f0
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0001
0x0bff
0x0fff
0x0400
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0x020c 0xfa38 0xf9fa 0x0178
0xfb28 0x03cc 0x0650 0x01c8
0x0666 0xff3c 0xfb02 0xfb3c
0xf9a4 0xfd56 0x0232 0x0686
0x0488 0x0578 0x0140 0xf95a
0xfe8e 0xf908 0xfb68 0x04e8
0xfdc4 0x0692 0x06c2 0xfe34
0x056e 0xfb9c 0xf8c6 0xfdf8
0x0542
0xfd1a
0xff98
0x03b0
0xf9d4
0x070a
0xf9f2
0x034a
0x03fe
0xf9ee
0x068e
0xfaa8
0x0290
0x00fc
0xfb80
0x06e0
0xff94
0xfd1e
0x057c
0xf936
0x063e
0xfbfc
0x0086
0x033c
0xf996
0x0596
0xfcbc
0xffe6
0x038a
0xf9c6
0x0744
0xf998
0x01b2
0x07ff
0x0470
0x07ff
0x07ff
0x0224
0x07ff
0x017c
0x07ae
0x07ff
0x022e
0x07ff
0x022a
0x07ff
0x07ff
0x0418
0x07ff
0x06dc
0x05c8
0x07ff
0x013c
0x07ff
0x0352
0x07ff
0x07ff
0x018a
0x07ff
0x0412
0x07ff
0x07ff
0x0220
0x07ff
0x07ff
0x039e
0x07ff
0x0162
0x07ff
0x05cc
0x067c
0x07ff
0x01ea
0x07ff
0x0684
0x0604
0x07ff
0x0116
0x07ff
0x02f4
0x0234
0x07ff
0x0284
0x07ff
0x07ff
0x03fa
0x07ff
0x0096
0x07ff
0x07ff
0x03bc
0x07ff
0x011e
0x07ff
0x0572
0x06bc
0xfa9e
0x0176
0x02e6
0xf99d
0x07f7
0xf8d8
0x0436
0x0001
0xf84e
0x07b0
0xfa9e
0x0178
0x02e5
0xf99d
0x07f7
0xf8d8
0xfe85
0x0565
0xf84e
0x07b1
0xfa9d
0x0176
0x02e5
0xf99d
0x0662
0xfd1e
0xfe85
0x0564
0xf84f
0x07b0
0xfa9d
0x0176
0x0729
0xf80a
0x0662
0xfd1d
0xfe87
0x0563
0xf84e
0x07b0
0x0001
0xfbc8
0x0729
0xf80a
0x0660
0xfd1e
0xfe85
0x0565
0xf8d8
0x0436
0x0001
0xfbca
0x072a
0xf80a
0x065f
0xfd1d
0xf99d
0x07f7
0xf8d9
0x0436
0x0002
0xfbc8
0x072a
0xf80a
0x05ea
0xf823
0x0774
0xfb31
0x00bb
0x0392
0xf933
0x07ff
0xfdd1
0xfdcd
0x05ea
0xf824
0x0775
0xfb31
0x00bb
0x0392
0xf824
0x05e7
0xfdd1
0xfdce
0x05e9
0xf823
0x0775
0xfb2f
0xfb2e
0x0776
0xf824
0x05e8
0xfdd3
0xfdcd
0x05e9
0xf823
0x038f
0x00be
0xfb2e
0x0775
0xf824
0x05e9
0xfdd1
0xfdcd
0x07ff
0xf935
0x038f
0x00be
0xfb2d
0x0776
0xf824
0x05e7
0x0392
0xf933
0x07ff
0xf933
0x038e
0x00bd
0xfb2c
0x0775
0xfb31
0x00ba
0x0394
0xf933
0x07ff
0xf935
0x038e
0x00be
GRAYCHIP, INC.
- 29 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test D
#
# use the odd parity map, see testA
# control register settings:
write 0 0x0082
write 1 0x0b6e
write 2 0x5bff
write 3 0x0000
write 4 0x00ff
write 5 0x0000
write 6 0x0f0f
write 7 0x0f0f
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0400
0x0001
0x0c00
0x0fff
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0xfec2 0xfe98 0xfb91 0xf901
0xfa86 0xf8c9 0xfa96 0xfdf4
0xfba3 0xfebf 0xfed8 0xfbcd
0xfe27 0xfaaf 0xf8a6 0xfa4d
0xf8b9 0xfb60 0xfebb 0xff16
0xff54 0xfe6e 0xfad7 0xf883
0xf9c0 0xf882 0xfb1e 0xfeb9
0xfc5d 0xff6b 0xfeb6 0xfaff
0xf9bb
0xff2f
0xf8f7
0xfdd7
0xfc0a
0xfa05
0xff56
0xf860
0xfcf6
0xfce8
0xf976
0xff5d
0xf8ed
0xfdba
0xfc44
0xf9be
0xff26
0xf99e
0xfcc3
0xfd2f
0xf933
0xff8b
0xf8e2
0xfd9d
0xfddf
0xf8f1
0xff3d
0xf9af
0xfc91
0xfd74
0xf8ee
0xffba
0xfe7c
0x02d7
0xfcbf
0x028d
0xff0c
0xfef5
0x02c3
0xfc5d
0x01c8
0xfff5
0xfe35
0x0313
0xfca2
0x0283
0xff3a
0xfeb1
0x0321
0xfd1b
0x01a5
0x0033
0xfdec
0x034e
0xfc85
0x0278
0x0107
0xfd6d
0x0349
0xfd17
0x0183
0x0072
0xfda4
0x0389
0xfdc7
0x0096
0x014e
0xfd2a
0x0372
0xfd14
0x0160
0x00b1
0xfcf6
0x031d
0xfdde
0x005e
0x0194
0xfce9
0x039b
0xfd10
0xff7e
0x0237
0xfcc3
0x032d
0xfdf4
0x0026
0x01db
0xfca6
0x0296
0xfedc
0xff3a
0x027c
0xfc90
0x033e
0xfe0b
0xfff0
0x0564
0xfe85
0xfd1e
0x0660
0xf80a
0x0729
0xfbc9
0x0001
0x07b1
0xf84f
0x0565
0xfe87
0xfd1d
0x065f
0xf80a
0x0729
0x0176
0xfa9e
0x07b1
0xf84f
0x0564
0xfe85
0xfd1d
0x0660
0xf99e
0x02e6
0x0176
0xfa9d
0x07b0
0xf84f
0x0564
0xfe85
0xf8d8
0x07f7
0xf99d
0x02e5
0x0178
0xfa9d
0x07b1
0xf84f
0x0001
0x0434
0xf8d8
0x07f7
0xf99d
0x02e6
0x0176
0xfa9e
0x072a
0xfbc9
0x0001
0x0436
0xf8d9
0x07f6
0xf99d
0x02e5
0x0660
0xf80a
0x072a
0xfbc9
0x0002
0x0434
0xf8d8
0x07f7
0x05e8
0xf824
0x0776
0xfb2d
0x00bd
0x038f
0xf934
0x07ff
0xfdd0
0xfdd3
0x05e7
0xf824
0x0775
0xfb2c
0x00be
0x038f
0xf823
0x05ea
0xfdd0
0xfdd3
0x05e8
0xf824
0x0775
0xfb2d
0xfb2e
0x0774
0xf823
0x05e9
0xfdcd
0xfdd3
0x05e8
0xf824
0x0392
0x00bb
0xfb2f
0x0775
0xf824
0x05e9
0xfdce
0xfdd3
0x07ff
0xf933
0x0392
0x00bb
0xfb31
0x0774
0xf823
0x05ea
0x038e
0xf934
0x07ff
0xf933
0x0394
0x00bd
0xfb31
0x0775
0xfb2d
0x00c0
0x038e
0xf934
0x07ff
0xf933
0x0392
0x00bb
GRAYCHIP, INC.
- 30 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test E
#
# This test uses even parity map.
#
for (i=0;i<256;i++) write (base+i) even_parity(i);
#
# where even_parity(i) is 0x9669 if "i" contains an even number of bits
# and is 0x6996 otherwise (base + 0 = 0x9669, base + 1 = 0x6996, etc)
# control registers settings:
write 0 0x7282
write 1 0x0b6e
write 2 0x7fef
write 3 0x0000
write 4 0x007f
write 5 0x0067
write 6 0x5555
write 7 0x1555
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0bff
0x0bff
0x0000
0x0000
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0xfdae 0xfea6 0xff92 0xfe8e
0x01a4 0xfeaa 0xfe06 0x00b4
0xfe86 0xff76 0x003e 0x022e
0x0210 0x007c 0x0130 0x01b0
0xffba 0xff14 0xffba 0x007c
0xff18 0xfe8c 0xfeda 0xff4e
0xff3e 0x00a6 0x00fc 0x0122
0x0028 0xffba 0x0024 0x00e4
0xfdde
0x0276
0x01b8
0x01ee
0xfea4
0xfedc
0x0020
0x00e0
0x00c4
0x0258
0x0216
0x01a2
0xff36
0xff48
0xff04
0x00d2
0xff98
0x01e0
0x021e
0x011c
0xfeb2
0xffdc
0xff52
0x00d0
0xfebc
0xff54
0x020e
0x0070
0xfe76
0xfeb8
0xffc0
0x00c0
0x01b2
0x0208
0xfe2e
0x0038
0x01ca
0xfec0
0xfef6
0xff00
0x027e
0x0232
0xfdc2
0x01fc
0x0184
0x006c
0xfeee
0xff0e
0x02c6
0x019a
0xfdbe
0x01a0
0x01ba
0x00ee
0xff48
0xff10
0x025e
0x0268
0xff7a
0x0108
0x01a4
0x0146
0xffaa
0xffc8
0x01ba
0x0042
0xfe9c
0x0036
0x00fc
0x00d4
0xfedc
0x0024
0x0298
0xff50
0xff62
0x00fe
0x0172
0x012c
0xff78
0xffc2
0x02a4
0xfe7c
0x0056
0x0184
0x00f2
0x0158
0xff2a
0x0018
0x0250
0xfdb8
0xff82
0x01cc
0x005e
0x0050
0xfefc
0xffc8
0x07e6
0x00d9
0xff27
0xfafb
0x0675
0xfec3
0xfec3
0xf98b
0x07ab
0x07c5
0xfbd5
0x042b
0x07c5
0x0706
0xf83b
0xfc2c
0x0675
0x07f4
0xf9c8
0x013d
0x0675
0x07f4
0xf81a
0xf98b
0x07c5
0x03d4
0xf92c
0xfe1f
0x03d4
0x07ab
0xf8fa
0xf92c
0x07f4
0xfafb
0xf80c
0xfafb
0x07e6
0x07e6
0xf9c8
0xfb4a
0x03d4
0xf8fa
0xf8fa
0xfe1f
0x07ab
0x07c5
0x0242
0xf8fa
0x0675
0xf80c
0xfb4a
0x013d
0x07e6
0x0638
0xff27
0xfafb
0x07ab
0xfc2c
0xf92c
0x042b
0x06d4
0x06d4
0xfbd5
0xf8fa
0xfec3
0x07f4
0xf80c
0x0638
0x04b6
0xf81a
0xf81a
0xfb4a
0x0242
0x01e1
0xf92c
0x06d4
0x01e1
0xfc2c
0xfe1f
0xf8fa
0x04b6
0xff27
0xfafb
0x07e6
0x04b6
0xff27
0x013d
0xfb4a
0x01e1
0x0706
0x042b
0x07c5
0x0706
0x0242
0x03d4
0x042b
0xff27
0x0638
0x00d9
0x0638
0xfec3
0xfec3
0xfafb
0x0675
0x0706
0x03d4
0x03d4
0x07c5
0x0242
0x01e1
0xf855
0x03d4
0x04b6
0x00d9
0x0675
0x07e6
0xfec3
0x0505
0xf80c
0x0638
0x0242
0xf8fa
0x042b
0x06d4
0xfbd5
0xfbd5
0xf92c
0x03d4
GRAYCHIP, INC.
- 31 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test F
#
# This test uses even parity map, see testE
# control registers settings:
write 0 0x3e02
write 1 0x0b6e
write 2 0x7fef
write 3 0x0000
write 4 0x00ff
write 5 0x00e3
write 6 0x210f
write 7 0x6543
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0aaa
0x0555
0x0555
0x0aaa
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0x07fc 0x07f4 0x07ff 0xfe1e
0x07d0 0x07c8 0xfd0c 0x07ff
0xffb0 0x07ff 0xff12 0xff0e
0x07ff 0x039a 0x07ff 0x07ff
0x07ff 0x067c 0x07ff 0x07ff
0x065a 0x04cc 0x0408 0x0294
0x07ff 0x0078 0xffda 0x07ff
0x0060 0x005a 0x07ff 0x07ff
0xfd96
0xfd84
0x07ff
0x07ff
0x07ff
0x01de
0x07ff
0x019a
0xfd94
0x07ff
0x07ff
0x07ff
0x0668
0x0088
0x01b6
0x0194
0xfd14
0x07ff
0x07ff
0x075a
0x07ff
0x07ff
0x010c
0x07ff
0xfd12
0x07ff
0x07ff
0x05c0
0x07ff
0x0126
0x07ff
0x07ff
0x05d6
0x05c4
0x0178
0x0502
0x03bc
0x0510
0x056c
0x01c6
0x05d4
0x05c0
0x05e2
0x0414
0x0524
0x0484
0x01e6
0x01c0
0x05ea
0xfe80
0x00dc
0x04bc
0x0358
0x042c
0x015c
0x0588
0xfff4
0x05d6
0x00d4
0x0418
0x035a
0x0368
0x058a
0x0542
0xff4c
0xff1e
0x05de
0x03b4
0x02ea
0x02f4
0x056a
0x02ae
0xff44
0x05e4
0x05ba
0x02da
0x0518
0x01f8
0x02cc
0x02aa
0xfe96
0x05ea
0x059a
0x0562
0x035e
0x058e
0x0250
0x0542
0xfe8e
0x05d4
0x053e
0x04ec
0x0362
0x026e
0x0588
0x0542
0xfd5b
0xfd5b
0xfbef
0xf809
0xf856
0xf92b
0xfaab
0xf80c
0xf8b6
0xf8b6
0xf835
0xf9fa
0xf912
0xf97e
0xfb1f
0xfb1f
0xf87d
0xf8cb
0xf841
0xf815
0xf8f9
0xf9da
0xf81a
0xf804
0xfccf
0xf88f
0xfc1b
0xf82f
0xf864
0xfa3e
0xf808
0xf801
0xf8a2
0xf8a2
0xf82b
0xf856
0xf8cb
0xfaab
0xf801
0xf801
0xfd2c
0xf86c
0xf812
0xf886
0xf912
0xfb1f
0xfa86
0xfa86
0xf8cb
0xf841
0xf804
0xf8f9
0xf8f9
0xf804
0xfaf8
0xfa62
0xfd8b
0xf822
0xf801
0xf946
0xf864
0xfad1
0xf808
0xf801
0x078c
0x078c
0x06e3
0xff45
0xfdbb
0x0428
0x05f5
0x00d6
0x034a
0x034a
0x01ce
0x0543
0x03fd
0x04a5
0x0656
0x0656
0x02be
0x0377
0x01ff
0xfee1
0x03d1
0x051d
0x013a
0x0072
0x0755
0x02ed
0x06fc
0xfe4d
0xfd8b
0x058d
0x00a4
0xffdb
0x031c
0x031c
0x019d
0xfdbb
0x0377
0x05f5
0x000e
0x000e
0x077a
0x028f
0x0108
0xfd2c
0x03fd
0x0656
0x05d3
0x05d3
0x0377
0x01ff
0x0072
0x03d1
0x03d1
0x0072
0x0637
0x05b1
0x079c
0x016b
0xffdb
0x0452
0xfd8b
0x0616
0x00a4
0xffdb
GRAYCHIP, INC.
- 32 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test G
#
# This test uses even parity map, see testE
# control registers settings:
write 0 0x0002
write 1 0x0b6e
write 2 0x7bff
write 3 0x0000
write 4 0x003f
write 5 0x0000
write 6 0xffff
write 7 0x3210
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0555
0x0aaa
0x0aaa
0x0555
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0xf800 0xfe57 0xfafb 0xf800
0xf978 0xff96 0xf800 0x0221
0x021e 0xf800 0xff92 0xf978
0xf800 0xfafa 0xfe50 0xf800
0xf800 0x019e 0xf800 0x0099
0x0204 0xf800 0xfc78 0xfce8
0xf9b4 0xf800 0x00d9 0xf800
0xf800 0x0235 0xf800 0xfde3
0x0195
0xf800
0xf800
0x0243
0xf805
0xf800
0x0164
0xfb6d
0xf800
0xfcb6
0x00c3
0xf800
0xf941
0x021a
0xf800
0xf800
0x00cb
0xfcb4
0xf800
0xfe1b
0xffb6
0xf800
0xfac3
0x01a9
0xf800
0xf800
0x018a
0xfb36
0xf800
0xff5b
0xfe7c
0xf800
0x0178
0x07ff
0x03b5
0xfefb
0x07ff
0x0729
0xfdd3
0x07ff
0x07ff
0xff7a
0x02dd
0x07ff
0x0249
0xfff7
0x07ff
0x05aa
0xfda9
0x07cc
0x07ff
0xfea8
0x0458
0x07ff
0x00fc
0x0124
0x07ff
0x06f3
0xfdcb
0x07ff
0x07ff
0xfe18
0x05db
0x07ff
0x020a
0x0015
0x07ff
0x0572
0xfe38
0x07ff
0x07ff
0xfdd0
0x0492
0x07ff
0x00c4
0x014e
0x07ff
0x03f2
0xfee7
0x07ff
0x07ff
0xfdf9
0x0617
0x07ff
0xffad
0x02ac
0x07ff
0x0280
0xfe3c
0x07ff
0x07ff
0xfdc1
0x078f
0x07ff
0xfecf
0x0422
0xf8ca
0x05bd
0x033d
0xf805
0x024a
0x0666
0xf948
0xfe42
0x07f5
0xfdfb
0xf971
0x068f
0x0205
0xf80b
0x037e
0x0589
0xf999
0xfdb8
0x07fb
0xfcc2
0xfa44
0x0736
0x00bd
0xf846
0x02fd
0x05ed
0xf8e8
0xfefd
0x07ca
0xfb9e
0xfb3e
0x07ad
0x014a
0xf827
0x0425
0x04fb
0xf868
0x0047
0x0767
0xfa98
0xfacf
0x0781
0xffff
0xf880
0x0533
0x03e7
0xf81a
0x0191
0x0798
0xfb04
0xfbdd
0x07d9
0xfeb4
0xf90c
0x061d
0x02b8
0xf835
0x0105
0x0717
0xfa13
0xfd04
0x07fe
0xfd73
0xf9c7
0xfc8b
0xfa6f
0x0750
0x0082
0xf856
0x04cd
0x0456
0xf832
0xff36
0x07bd
0xfb6e
0xfb6e
0x07bd
0xff36
0xf8cf
0x05c5
0x04cc
0xf856
0x0083
0x074f
0xfa6e
0xfc8d
0x07f6
0xfdef
0xf896
0x055f
0x03b3
0xf812
0x01cc
0x06b0
0xf992
0xfdc4
0x07e5
0xfe7b
0xf929
0x0641
0x0281
0xf802
0x0308
0x05e4
0xf9eb
0xfd3c
0x07ff
0xfd3b
0xf9ed
0x06fb
0x013e
0xf829
0x0283
0x0640
0xf929
0xfe7c
0x07e3
0xfc0d
0xfad9
0x0785
0x01cb
0xf812
0x03b4
0x055e
0xf895
0xffc5
0x0794
0xfafc
GRAYCHIP, INC.
- 33 -
JUNE 22, 1998
This document contains information which may be changed at any time without notice
GC3021 MIXER AND CARRIER REMOVAL CHIP
DATA SHEET
# GC3021 diagnostic test H
#
# This test uses even parity map, see testE
# control registers settings:
write 0 0x0002
write 1 0x0b6e
write 2 0x7bff
write 3 0x0000
write 4 0x00ff
write 5 0x0000
write 6 0x8888
write 7 0xcdef
write 8 0x1fff
write 9 0x1fff
write 10 0x1fff
write 11 0x1fff
write 12 0xff22
write
write
write
write
16
17
18
19
0x0fff
0x0fff
0x0001
0x0001
# perform snapshot
write 12 0xff22
write 12 0xff26
# wait until bit 3 (0x0008) of register 12 goes high
# the snapshot should be:
0x0408 0xfd30 0x00c4 0x0186
0xffc3 0xfdf1 0x03c5 0xfb99
0xfbe3 0x0476 0xfc7d 0x0189
0x0332 0xfeff 0xfe83 0x0391
0x0213 0xfc00 0x04c8 0xfbd2
0xfb25 0x03ec 0xfe29 0xff36
0x0146 0x016c 0xfc45 0x04f8
0x0436 0xfada 0x049a 0xfd4a
0xfc9f
0x03c2
0x00e6
0xfb61
0x025a
0x0335
0xfb3b
0x0005
0x0446
0xfdfc
0xfce9
0x0459
0x002b
0xfb4a
0x0330
0x02b0
0xfc12
0xffad
0x0467
0xfd32
0xfd5a
0x04db
0xff56
0xfb5c
0x0272
0x0296
0xfb8e
0x006f
0x0463
0xfc68
0xfdf0
0x0540
0xfec1
0x0458
0xfe38
0xfcab
0x0446
0x0078
0xfb27
0x02f5
0x032b
0xfc26
0xff65
0x0486
0xfd69
0xfd11
0x04d3
0xffa7
0xfbd1
0x023c
0x02d8
0xfb98
0x0025
0x048e
0xfc9a
0xfd9f
0x03fd
0x000a
0xfbbc
0x0302
0x025d
0xfb21
0x00fb
0x046f
0xfd5e
0xfdad
0x0475
0xff46
0xfbcd
0x03c4
0x01be
0xfaca
0x0081
0x03f3
0xfca4
0xfe38
0x04d4
0xfe6f
0xfc05
0x047b
0x01c9
0xfb90
0x0148
0x03c9
0xfbf1
0xfee6
0x0511
0xfd8d
0xfc6b
0x03a5
0x0131
0xfb4a
0x021a
0x0379
0xfb4d
0xffb1
0x0713
0xfa0c
0xfd10
0x07ff
0xfd62
0xf9d4
0x06e8
0x0160
0xf805
0x0253
0x065e
0xf940
0xfe53
0x07ea
0xfc2e
0xfabe
0x0694
0x01fa
0xf80c
0x038c
0x057c
0xf8a4
0xffa1
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GRAYCHIP, INC.
- 34 -
JUNE 22, 1998
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logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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Wireless
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