DRAM
AS4LC4M16
Austin Semiconductor, Inc.
4 MEG x 16 DRAM
PIN ASSIGNMENT
(Top View)
Extended Data Out (EDO) DRAM
50-Pin TSOP (DG)
FEATURES
• Single +3.3V ±0.3V power supply.
• Industry-standard x16 pinout, timing, functions, and
package.
• 12 row, 10 column addresses
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data retention
• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020
OPTIONS
MARKINGS
• Package(s)
50-pin TSOP (400-mil)
DG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh
None
S*
• Operating Temperature Ranges
Military (-55°C to +125°C)
Industrial (-40°C to +85°C)
XT
IT
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
A0-A11
A0-A9
NOTE: The \ symbol indicates signal is active LOW.
*Contact factory for availability. Self refresh option available on IT
version only.
For more products and information
please visit our web site at
www.austinsemiconductor.com
KEY TIMING PARAMETERS
tRAC
SPEED tRC
-5
84ns 50ns
-6
104ns 60ns
AS4LC4M16
Rev. 1.0 7/02
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
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1
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
AS4LC4M16
Rev. 1.0 7/02
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2
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The row address is latched by the RAS\ signal, then the
column address is latched by CAS\. This device provides
EDO-PAGE-MODE operation, allowing for fast successive data
operations (READ, WRITE or READ-MODIFY-WRITE) within
a given row.
The 4 Meg x 16 DRAM must be refreshed periodically in
order to retain stored data.
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic
random-access memory device containing 67,108,864 bits and
designed to operate from 3V to 3.6V. The device is functionally
organized as 4,194,304 locations containing 16 bits each. The
4,194,304 memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location is
uniquely addresses via the address bits: 12 row-address bits
(A0 - A11) and 10 column-address bits (A0 - A9). In addition,
both byte and word accesses are supported via the two CAS\
pins (CASL\ and CASH\).
The CAS\ functionality and timing related to address and
control functions (e.g., latching column addresses or selecting
CBR REFRESH) is such that the internal CAS\ signal is
determined by the first external CAS\ signal (CASL\ or CASH\)
to transition LOW and the last to transition back HIGH. The
CAS\ functionality and timing related to driving or latching data
is such that each CAS\ signal independently controls the
associated either DQ pins.
DRAM ACCESS
Each location in the DRAM is uniquely addressable, as
mentioned in the General Description. Use of both CAS\
signals resulted in a word access via the 16 I/O pins
(DQ0 - DQ15). Using only one of the two signals results in a
BYTE access cycle. CASL\ transitioning LOW selects an
access cycle for the lower byte (DQ0 - DQ7), and CASH\
transitioning LOW selects an access cycle for the upper byte
(DQ8-DQ15). General byte and word access timing is shown in
Figures 1 and 2.
FIGURE 1: WORD and BYTE WRITE Example
AS4LC4M16
Rev. 1.0 7/02
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DRAM
AS4LC4M16
Austin Semiconductor, Inc.
not allowed during the same cycle. However, an EARLY WRITE
on one byte and a LATE WRITE on the other byte, after a CAS\
precharge has been satisfied, are permissible.
DRAM ACCESS (continued)
A logic HIGH on WE\ dictates read mode, while a logic
LOW on WE\ dictates write mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS\ (CASL\
or CASH\), whichever occurs last. An EARLY WRITE occurs
when WE is taken LOW prior to either CAS\ falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE falls after
CAS\ (CASL\ or CASH\) is taken LOW. During EARLY WRITE
cycles, the data outputs (Q) will remain High-Z, regardless of
the state of OE\. During LATE WRITE or READ-MODIFYWRITE cycles, OE\ must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE\ LOW,
no write will occur, and the data outputs will drive read data
from the accessed location.
Additionally, both bytes are active. A CAS\ precharge
must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte are
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output
buffers off (High-Z) with the rising edge of CAS\. If CAS\ went
HIGH and OE\ was LOW (active), the output buffers would be
disabled. The 64MB EDO DRAM offers an accelerated page
mode cycle by eliminating output disable from CAS\ HIGH.
This option is called EDO, and it allows CAS\ precharge time
(tCP) to occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS\ goes HIGH,
as long as RAS\ and OE\ are held LOW and WE\ is held HIGH.
OE\ can be brought LOW or HIGH while CAS\ and RAS\ are
LOW, and the DQs will transition between valid data and HighZ. Using OE\, there are two methods to disable the outputs and
FIGURE 2: WORD and BYTE READ Example
AS4LC4M16
Rev. 1.0 7/02
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DRAM
AS4LC4M16
Austin Semiconductor, Inc.
FIGURE 3: OE\ Control of DQs
FIGURE 4: WE\ Control of DQs
AS4LC4M16
Rev. 1.0 7/02
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DRAM
Austin Semiconductor, Inc.
EDO PAGE MODE (Continued)
AS4LC4M16
retain stored data in the DRAM. The refresh requirements are
met by refreshing all rows in the 4 Meg x 16 DRAM array at
least once every 64ms* (4,096 rows). The recommended
procedure is to execute 4,096 CBR REFRESH cycles, either
uniformly spaced or grouped in bursts, every 64ms*. The
DRAM refreshes one row for every CBR cycle. For this device,
executing 4,096 CBR cycles will refresh the entire device. The
CBR REFRESH will invoke the internal refresh counter for automatic RAS\ addressing. Alternatively, RAS\-ONLY
REFRESH capability is inherently provided. However, with this
method, only one row is refreshed on each cycle. JEDEC
strongly recommends the use of CBR REFRESH for this device.
An optional self refresh mode is also available on the “S”
version. The self refresh feature is initiated by performing a
CBR Refresh cycle and holding RAS\ low for the specified tRASS.
The “S” option allows the user the choice of a fully static,
low-power data retention mode or a dynamic refresh mode at
the extended refresh period of 128ms, or 31.25µs per cycle, when
using a distributed CBR refresh. This refresh rate can be
applied during normal operation, as well as during a standby or
battery backup mode.
The self refresh mode is terminated by driving RAS\ HIGH
for a minimum time of tRPS. This delay allows for the completion
of any internal refresh cycles that may be in process at the time
of the RAS\ LOW-to-HIGH transition. If the DRAM controller
uses a distributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh, however, if the controller is
using RAS\ only or burst CBR refresh then a burst refresh
using tRC (MIN) is required.
two methods to disable the outputs and keep them disabled
during the CAS\ HIGH time. The first method is to have OE\
HIGH when CAS\ transitions HIGH and keep OE\ HIGH for
tOEHC thereafter. This will disable the DQs, and they will
remain disabled (regardless of the state of OE\ after that point)
until CAS\ falls again. The second method is to have OE\ LOW
when CAS\ transitions HIGH and then bring OE\ HIGH for a
minimum of tOEP anytime during the CAS\ HIGH period. This
will disable the DQs, and they will remain disabled (regardless
of the state of OE\ after that point) until CAS\ falls again (see
Figure 3). During other cycles, the outputs are disabled at tOFF
time after RAS\ and CAS\ are HIGH or at tWHZ after WE\
transitions LOW. The tOFF time is referenced from the rising
edge of RAS\ or CAS\, whichever occurs last. WE\ can also
perform the function of disabling the output drivers under
certain conditions, as shown in Figure 4.
EDO-PAGE-MODE operations are always initiated with a
row address strobed in by the RAS\ signal, followed by a
column address strobed in by CAS\, just like for single location
accesses. However, subsequent column locations within the
row may then be accessed at the page mode cycle time. This is
accomplished by cycling CAS\ while holding RAS\ LOW and
entering new column addresses with each CAS\ cycle.
Returning RAS\ HIGH terminates the EDO-PAGE-MODE
operation.
DRAM REFRESH
The supply voltage must be maintained at the specified
levels, and the refresh requirements must be met in order to
NOTES:
*64ms for IT version, 32ms for XT version.
AS4LC4M16
Rev. 1.0 7/02
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6
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
Voltage on VCC Relative to VSS .......................................-1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to VSS...................................................-1V to +4.6V
Power Dissipation...........................................................................1W
Operating temperature range, TA (ambient)..............-55°C to 125°C
Storage temperature (plastic)......................................-55°C to 150°C
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS1
(VCC = +3.3V ±0.3V)
PARAMETERS
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at VIN (0V < VIN < VCC +0.3V);
All other pins not under test = 0V
OUTPUT LEAKAGE CURRENT:
Any input at VOUT (0V < VOUT < VCC +0.3V);
DQ is disabled and in High-Z state
OUTPUT HIGH VOLTAGE:
IOUT = -2mA
OUTPUT LOW VOLTAGE:
IOUT = 2mA
AS4LC4M16
Rev. 1.0 7/02
SYM
MIN
MAX
UNITS
NOTES
VCC
3
3.6
V
VIH
2
VCC + 0.3
V
35
VIL
-0.3
0.8
V
35
II
-2
2
µA
36
IOZ
-5
5
µA
VOH
2.4
---
V
VOL
---
0.4
V
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7
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS1,2,3,5,6
(VCC = +3.3V ±0.3V)
SYM
-5
MAX
-6
MAX
UNITS
ICC1
1.5
1.5
mA
ICC2
1
1
mA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS\, CAS\, address cycling: tRC = tRC [MIN])
ICC3
165
150
mA
26
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS\ = VIL, CAS\, address cycling: tPC = tPC [MIN])
ICC4
125
120
mA
26
REFRESH CURRENT: RAS\-ONLY
Average power supply current
(RAS\ cycling, CAS\ = VIH: tRC = tRC [MIN])
ICC5
165
150
mA
22
REFRESH CURRENT: CBR
Average power supply current
(RAS\, CAS\, address cycling: tRC = tRC [MIN])
ICC6
165
150
mA
4, 7, 23
ICC7
1
1
mA
4, 7,
23, 37
ICC8
1
1
mA
4, 7, 37
PARAMETERS
STANDBY CURRENT: TTL
RAS\ = CAS\ = VIH
STANDBY CURRENT: CMOS
(RAS\ = CAS\ > VCC - 0.2V; DQs may be left open;
NOTES
Other inputs: VIN > VCC - 0.2V or VIN < 0.2V)
REFRESH CURRENT: Extended ("S" version only)
Average power supply current: CAS\ = 0.2V or CBR cycling;
RAS\ = tRAS (MIN); WE\ = VCC - 0.2V; A0 - A10, OE\ and
DIN = VCC - 0.2V or 0.2V (DIN may be left open); tRC = 125µS
REFRESH CURRENT: Self ("S" version only)
Average power supply current: CBR with RAS\ > tRASS (MIN)
and CAS\ held LOW; WE\ = VCC - 0.2V; A0 - A10, OE\ and
DIN = VCC - 0.2V or 0.2V (DIN may be left open)
AS4LC4M16
Rev. 1.0 7/02
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8
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
CAPACITANCE2
PARAMETER
SYM
MAX
UNIT
Input Capacitance: Address Pins
CI1
5
pF
Input Capacitance: RAS\, CAS\, WE\, OE\
CI2
7
pF
Input/Output Capacitance: DQ
CI0
7
pF
AC ELECTRICAL CHARACTERISTICS5,6,7,8,9,10,11,12
(VCC = +3.3V ±0.3V)
DESCRIPTION
Access time from column address
-5
SYMBOL
MIN
MAX
MIN
25
tAA
-6
MAX
30
UNITS
NOTES
ns
Column-address setup to CAS\ precharge
tACH
12
15
ns
Column-address hold time (referenced to RAS\)
tAR
38
45
ns
Column-address setup time
tASC
0
0
ns
28
Row-address setup time
tASR
0
0
ns
28
42
ns
18
ns
29
Column address to WE\ delay time
tAWD
Access time from CAS\
tCAC
Column-address hold time
49
13
15
tCAH
8
CAS\ pulse width
tCAS
8
10
CAS\ LOW to "Don't Care" during Self Refresh
tCHD
15
15
ns
CAS\ hold time (CBR Refresh)
tCHR
8
10
ns
4, 31
Last CAS\ going LOW to first CAS\ to return HIGH
tCLCH
5
5
ns
31
CAS\ to output in Low-Z
tCLZ
0
0
ns
29
Data output hold after CAS\ LOW
tCOH
3
3
ns
CAS\ precharge time
tCP
8
Access time from CAS\ precharge
tCPA
10,000
10
10,000
10
28
35
ns
28
ns
30, 32
ns
13, 33
ns
29
CAS\ to RAS\ precharge time
tCRP
5
5
ns
31
CAS\ hold time
tCSH
38
45
ns
31
CAS\ setup time (CBR Refresh)
tCSR
5
5
ns
4, 28
CAS\ to WE\ delay time
tCWD
28
35
ns
18, 28
WRITE command to CAS\ lead time
tCWL
8
10
ns
31
Data-in hold time
tDH
8
10
ns
19, 29
Data-in setup time
tDS
0
0
ns
19, 29
Output disable
tOD
0
15
ns
24, 25
Output enable time
tOE
15
ns
20
OE\ hold time from WE\ during
READ-MODIFY-WRITE cycle
tOEH
8
10
ns
25
OE\ HIGH hold time from CAS\ HIGH
tOEHC
5
10
ns
OE\ HIGH pulse width
tOEP
5
5
ns
OE\ LOW to CAS\ HIGH setup time.
tOES
4
5
ns
Output buffer turn-off delay
tOFF
0
OE\ setup prior to RAS\ during HIDDEN REFRESH cycle
tORD
0
AS4LC4M16
Rev. 1.0 7/02
12
0
12
12
0
0
15
ns
17, 24, 29
ns
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9
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS (Continued)5,6,7,8,9,10,11,12
(VCC = +3.3V ±0.3V)
DESCRIPTION
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
-5
MAX
MIN
-6
MAX
SYMBOL
MIN
tPC
20
25
ns
34
tPRWC
47
56
ns
34
50
60
UNITS NOTES
ns
Access time from RAS\
tRAC
RAS\ to column-address delay time
tRAD
Row address hold time
tRAH
7
RAS\ pulse width
tRAS
50
10,000
60
10,000
ns
RAS\ pulse width (EDO PAGE MODE)
tRASP
50
125,000*
60
125,000*
ns
RAS\ pulse width during Self Refresh
tRASS
80
80
µs
Random READ or WRITE cycle time
tRC
84
104
ns
RAS\ to CAS\ delay time
tRCD
11
14
ns
14, 28
READ command hold time (referenced to CAS\)
tRCH
0
0
ns
16, 30
READ command setup time
tRCS
0
0
ns
28
Refresh period
tREF
64/24**
ms
22, 23
Refresh period ("S" version)
tREF
100
ms
23, 38
9
12
ns
10
64/24**
100
15
ns
tRP
30
40
ns
tRPC
5
5
ns
RAS\ precharge time exiting Self Refresh
tRPS
90
105
ns
READ command hold time (referenced to RAS\)
tRRH
0
0
ns
16
RAS\ hold time
tRSH
13
15
ns
35
READ-WRITE cycle time
tRWC
116
140
ns
RAS\ to WE\ delay time
tRWD
67
79
ns
WRITE command to RAS\ lead time
tRWL
13
15
ns
Transitioin time (rise or fall)
tT
2
WRITE command hold time
RAS\ precharge time
RAS\ to CAS\ precharge time
25
2
25
ns
tWCH
8
10
ns
WRITE command hold time (referenced to RAS\)
tWCR
38
45
ns
WE\ command setup time
tWCS
0
0
ns
WE\ to outputs in High-Z
tWHZ
WRITE command pulse width
tWP
5
5
ns
WE\ pulse widths to disable outputs
tWPZ
10
10
ns
WE\ hold time (CBR Refresh)
tWRH
8
10
ns
WE\ setup time (CBR Refresh)
tWRP
8
10
ns
12
15
18
35
18, 28
ns
NOTES:
*For XT Temp (-55°C to +125°C) tRASP (MAX) = 80,000ns for -5 and -6 speed.
**64ms Refresh for IT Temp, 24ms Refresh for XT Temp.
AS4LC4M16
Rev. 1.0 7/02
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10
DRAM
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC = +3.3V; f = 1 MHz; TA = 25°C.
3. I CC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time and the
outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
is ensured.
6. An initial pause of 100µs is required after power-up, followed
by eight RAS\ refresh cycles (RAS\-ONLY or CBR with WE\
HIGH), before proper device operation is ensured. The eight
RAS\ cycle wake-ups should be repeated any time the tREF
refresh requirements is exceeded.
7. AC characteristics assume tT = 2.5ns.
8. VIH (MIN) and VIL (MAX) are reference levels for measuring
timing of input signals. Transition times are measured between
VIH and VIL (or between VIL and VIH).
9. In addition to meeting the transition rate specification, all
input signals must transit between VIH and VIL (or between VIL
and VIH) in a monotonic manner.
10. If CAS\ and RAS\ = VIH, data output is High-Z.
11. If CAS\ = VIL, data output may contain data from the last
valid READ cycle.
12. Measured with a load equivalent to two TTL gates and
100pF; and VOL = 0.8V and VOH = 2V.
13. If CAS\ is LOW at the falling edge of RAS\, output data will
be maintained from the previous cycle. To initiate a new cycle
and clear the data-out buffer, CAS\ must be pulsed HIGH
for tCP.
14. The tRCD (MAX) limit is no longer specified. tRCD (MAX)
was specified as a reference point only. If tRCD was greater than
the specified tRCD (MAX) limit, then access time was controlled
exclusively by tCAC (tRAC [MIN] no longer applied). With our
without the tRCD limit, tAA and tCAC must always be met.
15. The tRAD (MAX) limit is no longer specified. tRAD (MAX)
was specified as a reference point only. If tRAD was greater than
the specified tRAD (MAX) limit, then access time was controlled
exclusively by tAA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always
be met.
16. Either tRCH or tRRH must be satisfied for a READ cycle.
AS4LC4M16
17. tOFF (MAX) defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or VOL.
18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating
parameters. tWCS applies to EARLY WRITE cycles. If
tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout the entire
cycle. tRWD, tAWD, and tCWD define READ-MODIFY-WRITE
cycles. Meeting these limits allows for reading and disabling
output data and then applying input data. OE\ held HIGH and
WE\ taken LOW after CAS\ goes LOW results in a LATE WRITE
(OE\-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not
applicable in a LATE WRITE cycle.
19. These parameters are referenced to CAS\ leading edge in
EARLY WRITE cycles and WE\ leading edge in LATE WRITE
or READ-MODIFY-WRITE operations are not possible.
20. If OE\ is tied permanently LOW, LATE WRITE, or READMODIFY-WRITE operations are not possible.
21. A HIDDEN REFRESH may also be performed after a WRITE
cycle. In this case, WE\ is LOW and OE\ is HIGH.
22. RAS\-ONLY REFRESH that all 4,096 rows of the device be
refreshed at least once every 64ms.
23. CBR REFRESH for the device requires that at least 4,096
cycles be completed every 64ms.
24. The DQs go High-Z during READ cycles once tOD or tOFF
occur. If CAS\ stays LOW while OE\ is brought HIGH, the DQs
will go High-Z. If OE\ is brought back LOW (CAS\ still LOW),
the DQs will provide the previous read data.
25. LATE WRITE and READ-MODIFY-WRITE cycles must
have both tOD and tOEH met (OE\ HIGH during write cycle) in
order to ensure that the output buffers will be open during the
WRITE cycle. If OE\ is taken back LOW while CAS\ remains
LOW, the DQs will remain open.
26. Column address changed once each cycle.
27. The first CAS\ edge to transition LOW.
28. Output parameter (DQx) is referenced to corresponding CAS\
input; DQ0 - DQ7 by CASL\ and DQ8 - DQ15 by CASH\.
29. Each CASx\ must meet minimum pulse width.
30. The last CASx\ edge to transition HIGH.
31. Last falling CASx\ edge to first rising CASx\ edge.
32. Last rising CASx\ edge to first falling CASx\ edge.
33. Last rising CASx\ edge to next cycles last rising CASx\
edge.
34. Last CASx\ to go LOW.
Notes continued on next page.
*64ms for IT version, 32ms for XT version.
AS4LC4M16
Rev. 1.0 7/02
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11
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Austin Semiconductor, Inc.
AS4LC4M16
NOTES (Continued):
35. VIH overshoot: VIH (MAX) - VCC + 2V for a pulse width £
3ns, and the pulse width cannot be greater than one third of the
cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £
3ns, and the pulse width cannot be greater then one third of the
cycle rate.
36. NC pins are assumed to be left floating and are not tested for
leakage.
37. Self refresh and extended refresh for the device requires that
at least 4,096 cycles be completed every 128ms.
38. Self refresh version on IT temp parts only.
AS4LC4M16
Rev. 1.0 7/02
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12
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Austin Semiconductor, Inc.
AS4LC4M16
READ CYCLE
NOTES:
1. tOFF is referenced from rising edge of RAS\ or CAS\, whichever occurs last.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
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AS4LC4M16
Austin Semiconductor, Inc.
EARLY WRITE CYCLE
AS4LC4M16
Rev. 1.0 7/02
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Austin Semiconductor, Inc.
AS4LC4M16
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
EDO-PAGE-MODE READ CYCLE
NOTES:
* tRASP (MAX) = 80,000ns for XT temperature version.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
DRAM
Austin Semiconductor, Inc.
AS4LC4M16
EDO-PAGE-MODE EARLY WRITE CYCLE
NOTES:
* tRASP (MAX) = 80,000ns for XT temperature version.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
DRAM
Austin Semiconductor, Inc.
AS4LC4M16
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
NOTES:
* tRASP (MAX) = 80,000ns for XT temperature version.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
DRAM
Austin Semiconductor, Inc.
AS4LC4M16
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
NOTES:
* tRASP (MAX) = 80,000ns for XT temperature version.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
READ CYCLE
(with WE\-controlled disable)
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
RAS\-ONLY REFRESH CYCLE
(OE\ and WE\ = DON’T CARE)
CBR REFRESH CYCLE
(Addresses and OE\ = DON’T CARE)
NOTES:
1. End of first CBR REFRESH cycle.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
HIDDEN REFRESH CYCLE1
(WE\ = HIGH; OE\ = LOW)
NOTES:
1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE\ is LOW and OE\ is HIGH.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
SELF REFRESH CYCLE
(Addresses and OE\ = DON’T CARE)
NOTES:
1. Once tRASS (MIN) is met and RAS\ remains LOW, the DRAM will enter self refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS\-only or burst CBR refresh is used.
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
23
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS
(Package Designator DG)
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS4LC4M16DG-6S/XT
Device Number
AS4LC4M16
AS4LC4M16
Package
Type
DG
DG
Speed
ns
-5
-6
Options
Process
S
S
/*
/*
*AVAILABLE PROCESSES
XT = Industrial Temperature Range
IT = Industrial Temperature Range
-55oC to +125oC
-40oC to +85oC
OPTION DEFINITIONS
S = Self Refresh
AS4LC4M16
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25