SN54ALS133, SN74ALS133 13-INPUT POSITIVE-NAND GATES SDAS202B – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS133 . . . J PACKAGE SN74ALS133 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs A B C D E F G GND description These devices contain a 13-input positive-NAND gate. They perform the following Boolean functions in positive logic: Y = A• B• C • D • E• F • G • H• I • J • K• L • M Y = A+ B+ C+ D + E+ F + G + H+ I + J + K+ L + M The SN54ALS133 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS133 is characterized for operation from 0°C to 70°C. All inputs H 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC M L K J I H Y B A NC VCC M 3 C D NC E F OUTPUT Y L H 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 L K NC J I G GND NC Y H One or more inputs L 16 SN54ALS133 . . . FK PACKAGE (TOP VIEW) FUNCTION TABLE INPUTS A – M 1 NC – No internal connection logic symbol† A B C D E F G H I J K L M 1 logic diagram (positive logic) A & 2 B 3 C 4 D 5 E 6 F 7 9 G Y 10 H 11 I 12 J 13 K 14 L 15 M 1 2 3 4 5 6 7 9 Y 10 11 12 13 14 15 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS133, SN74ALS133 13-INPUT POSITIVE-NAND GATES SDAS202B – APRIL 1982 – REVISED DECEMBER 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS133 VCC VIH Supply voltage High-level input voltage SN74ALS133 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 VIL Low level input voltage Low-level 0.8‡ 0.7§ IOH IOL High-level output current – 0.4 Low-level output current – 55 125 V V 4 TA Operating free-air temperature ‡ Applies over temperature range – 55°C to 70°C § Applies over temperature range 70°C to 125°C UNIT 0 0.8 – 0.4 mA 8 mA 70 °C V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = – 0.4 mA VOL 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO# VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, VI = 0 VI = 4.5 V SN54ALS133 TYP¶ MAX MIN SN74ALS133 TYP¶ MAX MIN –1.2 VCC – 2 –1.5 VCC – 2 0.25 0.5 V V 0.25 0.4 0.35 0.5 0.1 – 20 UNIT 0.1 V mA 20 20 µA – 0.1 – 0.1 mA –112 mA mA –112 – 30 0.24 0.34 0.24 0.34 0.56 0.8 0.56 0.08 mA ¶ All typical values are at VCC = 5 V, TA = 25°C. # The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS133, SN74ALS133 13-INPUT POSITIVE-NAND GATES SDAS202B – APRIL 1982 – REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) Any TO (OUTPUT) Y VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54ALS133 SN74ALS133 MIN MAX MIN 1 16 3 11 1 47 5 25 UNIT MAX ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS133, SN74ALS133 13-INPUT POSITIVE-NAND GATES SDAS202B – APRIL 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan 5962-8859001FA ACTIVE CFP W 16 1 TBD JM38510/37005B2A ACTIVE LCCC FK 20 1 TBD JM38510/37005BEA ACTIVE CDIP J 16 1 TBD M38510/37005B2A ACTIVE LCCC FK 20 1 TBD M38510/37005BEA ACTIVE CDIP J 16 1 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type A42 N / A for Pkg Type SN54ALS133J ACTIVE CDIP J 16 1 TBD SN74ALS133D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133N ACTIVE PDIP N 16 25 Pb-Free (RoHS) TBD CU NIPDAU N / A for Pkg Type SN74ALS133N3 OBSOLETE PDIP N 16 SN74ALS133NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) SN74ALS133NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS133NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ALS133FK ACTIVE LCCC FK 20 1 TBD SNJ54ALS133J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type SNJ54ALS133W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Call TI Samples (Requires Login) Call TI POST-PLATE N / A for Pkg Type A42 (3) Call TI CU NIPDAU N / A for Pkg Type POST-PLATE N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN54ALS133, SN74ALS133 : • Catalog: SN74ALS133 • Military: SN54ALS133 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALS133DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74ALS133NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS133DR SN74ALS133NSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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