SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994 • • • • • • • • DW OR NT PACKAGE (TOP VIEW) BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to AMD Am29853 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Latch for Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT) OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE description The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-erro (ERR)r flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29853 provides true logic. The SN74BCT29853 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT AND I/O Bi† ∑ of H’s A B PARITY ERR‡ FUNCTION OEB OEA CLR LE Ai ∑ of H’s L H X X Odd Even NA NA A L H NA H L X L NA Odd Even B NA NA H L H L H H NA X X NA NA N−1 X X L H X X X NA NA H Clear error-flag register H H H L X X H H L L X X L Odd H Even X Z Z Z NC H H L Isolation§ (parity check) L L X X Odd Even NA NA A H L NA A data to B bus and generate inverted parity A data to B bus and generate parity B data to A bus and check parity Store error flag NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume the ERR output was previously high. § In this mode, the ERR output, when enabled, shows inverted parity of the A bus. Copyright 1994, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2−1 SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994 logic diagram (positive logic) 8x 8 8 B1 −B8 A1 −A8 EN 8x 8 EN OEB OEA PARITY 8 8 MUX 1 1 2k 9 P 1 1 G1 ERR LE CLR 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994 error-flag waveforms OEB H L OEA H L Even Bi + PARITY Odd LE H L CLR H L ERR H L Pass Sample Store Clear ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRESTATE OUTPUT FUNCTION LE CLR POINT P ERRn−1† ERR L L L H X L H Pass L H L X H X L H L L H Sample H L X X H Clear X L H L H Store H H † ERRn−1 represents the state of the ERR output before any changes at CLR, LE, or point P. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−3 SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994 recommended operating conditions VCC VIH Supply voltage VIL VOH Low-level input voltage IOH IOL High-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX 4.5 5 5.5 2 V V 0.8 High-level output voltage UNIT ERR Low-level output current 0 V 2.4 V −24 mA 48 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VOH All inputs /outputs except ERR VCC = 4.5 V IOH VOL ERR VCC = 4.5 V, VCC = 4.5 V, II IIH‡ IIL‡ MIN II = −18 mA IOH = − 15 mA IOH = − 24 mA VOH = 2.4 V TYP† V V 2 20 0.35 µA 0.5 V 0.1 mA VI = 2.7 V 20 µA VCC = 5.5 V, VI = 0.4 V −0.75 VCC = 5.5 V, VCC = 5.5 V, VO = 0 Outputs open Data IOS§ ICCL UNIT −1.2 2.4 IOL = 48 mA VI = 5.5 V VCC = 5.5 V, VCC = 5.5 V, Control MAX −0.2 −75 ICCZ VCC = 5.5 V, Outputs open † All typical values are at VCC = 5 V, TA = 25°C. ‡ These parameters include off-state output current for I/O ports only. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. mA −250 mA 55 80 mA 30 45 mA timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN LE low 10 CLR low 10 MAX UNIT tw Pulse duration tsu Setup time before LE↓ Bi and PARITY 18 ns th Hold time after LE↓ Bi and PARITY 8 ns 2−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPZH tPZL OEA or OEB A or B tPHZ tPLZ OEA or OEB A or B PARAMETER tPLH tPHL CLR ERR LE tPLH tPHL OEA PARITY tPLH tPHL Bi / PARITY ERR VCC = 5 V, TA = 25°C MIN MAX 7 1 10 5 7 1 10 1.5 10 13 1.5 15 1.5 10 13 1.5 15 2 13 16 2 20 2 13 16 2 20 2 13 16 2 20 2 13 16 2 20 1.5 11 14 1.5 15 1.5 5 7 1.5 9 1.5 10 13 1.5 15 1.5 10 13 1.5 15 1.5 17 22 1.5 24 1.5 10 13 1.5 16 MIN TYP MAX 1 5 1 UNIT ns ns ns ns ns ns ns NOTE 1: Load circuits and voltage waveforms are shown in Section 1. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−5 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74BCT29853DW OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available SN74BCT29853DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available SN74BCT29853NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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