CADEKA SPT5240

www.cadeka.com
SPT5240
10-bit, 400 MWPS Current Output
Digital-to-Analog Converter
Features
Description
• 400 MWPS update rate
• Complementary current outputs
• +3.3 V power supply
• Low power dissipation:
149mW (typ) @ƒCLK = 400MHz and 12mA output
• Excellent AC performance:
SFDR = 58dBc for ƒCLK = 400MHz and ƒOUT = 1.27 MHz
• Internal reference
The SPT5240 is a 10-bit digital-to-analog converter that
performs at an update rate of 400M words per second. The
architecture achieves excellent high-frequency performance
with very low power dissipation. This makes it ideal for all
types of battery-operated equipment requiring high-speed
digital-to-analog conversion.
Applications
The SPT5240 operates over an extended industrial
temperature range from -40°C to +85°C and is available in a
32-lead LQFP package.
• Battery-operated devices
• Portable RF devices
• Set top boxes
• Video displays
• Broadband RF
• High-speed test equipment
Functional Block Diagram
PWD
ISET
D0 – D9
DVDD
AVDD
Reference
Circuit
10 Bits
10-bit
Current Output
DAC
IOP
ION
CLK
DGND
AGND
REV. 1 June 2003
DATA SHEET
SPT5240
Electrical Specifications
(TA = 25°C, AVDD = 3.3V, DVDD = 3.3V, ƒOUT = 1.27MHz, ƒCLK = 400MHz, Clock Duty Cycle = 50%,
IOUT = 20mA, RL = 50Ω; unless otherwise noted)
Parameter
Conditions
Test Level
Min
Typ
Max Units
DC Performance
Resolution
10
Bits
Differential Linearity Error (DLE)
DC at ION
I
-1
Integral Linearity Error (ILE)
DC at ION
I
-4
Offset Error
DC at both outputs
I
-.005
Full Scale Error
DC at both outputs
I
-15
+15
%FS
Gain Error
DC at both outputs
I
-15
+15
%FS
±1.34
2
LSB
4
LSB
+.005 %FS
Maximum Full Scale Output Current
V
30
mA
Output Compliance Voltage
V
1.5
V
V
250
kΩ
V
±300
ppm
FS/°C
Output Impedance
Full-scale output
Gain Error Tempco
AC Performance
Maximum Clock Rate
IV
400
MHz
Glitch Energy
Major code transition
V
7
pV-s
Settling Time (tsettling)
See Figure 1, major code trans.
V
7.5
ns
Output Rise Time
V
1.3
ns
Output Fall Time
V
1.5
ns
V
1.8
ns
Spurious Free Dynamic Range (SFDR)
V
58
dBc
Total Harmonic Distortion (THD)
V
-55
dBc
VIH Minimum
V
2
V
VIL Maximum
V
1
V
Logic “1” Current
I
-10
+10
µA
Logic “0” Current
I
-10
+10
µA
Output Delay Time (tD)
See Figure 1
Digital and Clock Data Input
Input Setup Time (tS)
See Figure 1
V
1
ns
Input Hold Time (tH)
See Figure 1
V
1
ns
V
-29
dBFS
Clock Feedthrough
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.
LEVEL
I
IV
V
2
TEST PROCEDURE
100% production tested at the specified temperature.
Parameter is guaranteed by design or characterization data.
Parameter is a typical value for information purposes only.
REV. 1 June 2003
SPT5240
DATA SHEET
Electrical Specifications (Continued)
(TA = 25°C, AVDD = 3.3V, DVDD = 3.3V, ƒOUT = 1.27MHz, ƒCLK = 400MHz, Clock Duty Cycle = 50%,
IOUT = 20mA, RL = 50Ω; unless otherwise noted)
Parameter
Conditions
Test Level
Min
Typ
Max Units
AVDD = DVDD
IV
3.0
+3.3
3.6
AVDD
25MHz Clock
V
9.5
mA
DVDD
25MHz Clock
V
200
µA
20mA IOUT
IV
12mA IOUT
V
Power Supply Requirements
Supply Voltage
V
Supply Current Sleep Mode
Power Dissipation
170
195
149
215
mW
mW
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.
LEVEL
I
IV
V
TEST PROCEDURE
100% production tested at the specified temperature.
Parameter is guaranteed by design or characterization data.
Parameter is a typical value for information purposes only.
REV. 1 June 2003
3
DATA SHEET
SPT5240
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter
Min
Max
Units
AVDD
3.7
V
DVDD
3.7
V
Supply Voltage
Voltage Difference between AGND and DGND
-0.5
0.5
V
Voltage Difference between AVDD and DVDD
-0.5
0.5
V
D0 – D9
-0.5
DVDD +0.5
V
CLK
-0.5
DVDD +0.5
V
Junction Temperature
150
°C
Lead, soldering (10 seconds)
260
°C
+150
°C
Input Voltages
Storage Temperature
Thermal Resistance (ΘJA) for 32 lead LQFP
-65
64
°C/W
Note:
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper
nominal applied conditions in typical applications.
4
REV. 1 June 2003
SPT5240
DATA SHEET
Typical Performance Characteristics
(TA = 25°C, AVDD = 3.3V, DVDD = 3.3V, ƒOUT = 1.27MHz, ƒCLK = 400MHz, Clock Duty Cycle = 50%,
IOUT = 20mA, RL = 50Ω; unless otherwise noted)
AC Performance vs. Temperature
AC Performance vs. Clock Frequency
65
65
Clock frequency = 327MHz
60
SFDR
THD
THD
50
55
SNR
dB
dB
60
SFDR
55
45
50
40
35
SNR
45
30
40
25
0
100
200
300
400
500
-50
600
-25
0
50
75
Intergral Nonlinearity vs. Code
AC Performance vs. VDD
2.0
65
60
SFDR
55
THD
1.5
LSB's
dB
25
Temperature (°C)
Clock Frequency (MHz)
50
1.0
0.5
45
SNR
40
0
-0.5
35
3.0
3.3
0
3.6
128
256
384
512
640
768
896 1024
Code
VDD (V)
Differential Nonlinearity vs. Code
AVDD, DVDD vs. Clock Frequency
0.6
45
AVDD
0.4
35
mA
LSB's
0.2
0
-0.2
25
15
DVDD
-0.4
5
-0.6
0
128
256
384
512
Code
REV. 1 June 2003
640
768
896 1024
40
105
205
245
328
400
Clock (MHz)
5
DATA SHEET
Specification Definitions
Differential Linearity Error (DLE) or
Differential Nonlinearity (DNL)
In an ideal DAC, output transitions between two adjacent
codes are 1 LSB apart. Differential Linearity Error is the
deviation, expressed in LSBs, from this ideal value.
Integral Linearity Error (ILE) or
Integral Nonlinearity (INL)
The ideal transfer for a DAC is a straight line drawn between
"zero-scale" output and "full-scale" output. ILE is the
deviation of the output from the straight line. The deviation
of the output at each code is measured and compared to the
ideal output at that code. ILE may also be expressed as a
sum of DLE starting from code 0…0 to the code that ILE
measurement is desired.
Monotonic
A digital-to-analog converter is considered monotonic if
the analog output never decreases as the code value at the
input increases. A DLE less than -1 LSB would indicate a
non-monotonic DAC.
Offset Error
The deviation, from ideal, at the DAC output when set to
zero-scale. In the current output DAC there should be no
current flow at zero-scale. Therefore, Offset Error is the
amount of current measured with the DAC set to zero-scale.
Full-Scale Error
The ideal maximum full-scale current output of the DAC is
determined by the value of RSET. Full-scale error is the
deviation of the output from ideal with the offset error
included.
Gain Error
The ideal maximum full-scale current output of the DAC is
determined by the value of RSET. Gain error is the deviation
of the output from ideal with the offset error removed.
Full-Scale Output
The maximum current output available for a given value of
RSET. In the SPT5240 IOP is full-scale at code 1111111111
and ION is full-scale at code 0000000000.
Zero-Scale Output
The minimum current output, ideally zero amps. In the
SPT5240 IOP is zero-scale at code 0000000000 and ION
is zero-scale at code 1111111111.
6
SPT5240
Compliance Voltage
The maximum terminal output voltage for which the device
will provide the specified current output characteristics.
Harmonic
1. Of a sinusoidal wave, an integer multiple of the frequency
of the wave. Note: The frequency of the sine wave is called
the fundamental frequency or the first harmonic, the
second harmonic is twice the fundamental frequency, the
third harmonic is three times the fundamental frequency, etc.
2. Of a periodic signal or other periodic phenomenon, such
as an electromagnetic wave or a sound wave, a component
frequency of the signal that is an integer multiple of the
fundamental frequency. Note: The fundamental frequency
is the reciprocal of the period of the periodic phenomenon.
Total Harmonic Distortion (THD)
The ratio of the sum of the power of first 9 harmonics above
the fundamental frequency to the power of the fundamental
frequency. Usually expressed in dBc.
Spurious Free Dynamic Range (SFDR)
The ratio of the fundamental sinusoidal power to the power
of the single largest harmonic or spurious signal within the
range of the 9th harmonic.
Clock Feedthrough
The ratio of the full-scale output to the peak-to-peak noise
generated at the DAC output by input clock transitions.
Expressed in dBFS.
Major Code Transition
The DAC code transition between 011…1 and 100…0 is
referred to as major code transition. This transition often
involves maximum number of internal circuit elements to
switch states, resulting in worst DLE, ILE, glitch, etc.
Glitch Energy
A glitch is a switching transient that appears in the output of
a DAC during a code transition. Glitch energy is measured as
a product of the output voltage and time duration for major
code transition, expressed in pV-s.
Output Rise Time
The amount of time for the output to change from 10%
to 90% of the full-scale voltage, for a positive full scale
transition from zero-scale to full-scale.
Output Fall Time
The amount of time for the output to change from 90%
to 10% of the full-scale voltage, for a negative full scale
transition from full-scale to zero-scale.
REV. 1 June 2003
SPT5240
DATA SHEET
D3
DVDD
DGND
D4
D5
DVDD
D6
D7
31
30
29
28
27
26
25
Pin Assignments
32
Pin Configuration
D2
1
24
D8
D1
2
23
DGND
DVDD
3
22
D9
21
DGND
20
PWD
SPT5240SIT
32-pin LQFP
15
16
ISET
N/C
17
AVDD
8
14
AGND
AGND
AGND
13
18
ION
7
12
DGND
11
AVDD
IOP
19
AGND
6
10
CLK
AGND
5
9
4
AVDD
D0
DGND
Analog Outputs
IOP
DAC current output. Full-scale output at 11…11
input code.
Complementary current output. Full-scale output
ION
at 00…00 input code.
Digital Inputs
D0 – D9 Digital inputs (D0 = LSB).
PWD
Power down mode pin. Active high. Internally
pulled down.
CLK
Clock input pin. Data is latched on the rising edge.
Reference
ISET
Full-scale adjust control. Connection for
reference-current setting resistor.
Power
AGND
DGND
AVDD
DVDD
N/C
Theory of Operation
outputs of the decoders are latched using a second bank
of master-slave latches whose outputs then drive differential
current switches, which steer the appropriate current to
the IOP or ION outputs.
The SPT5240 is a 10-bit 400 MWPS digital-to-analog
converter. It integrates a DAC core with a bandgap reference
and operates from a +3.3V power supply.
The analog (AVDD) and digital (DVDD) power supplies are
separated on chip to allow flexibility in the interface board.
The analog (AGND) and digital (DGND) are separated on
chip. Circuit board ground planes should be separated and
tied together with a ferrite bead.
The DAC architecture is a compound differential current
output DAC consisting of a 6-bit fully segmented DAC for
the MSBs and a 4-bit fully segmented DAC for the LSBs.
The input cell, followed by a master-slave latch, buffers the
digital inputs. A 6:64 decoder decodes the digital data for
the MSBs, and a 4:16 decoder does so for the LSBs. The
N
Analog Supply Ground.
Digital Supply Ground.
Analog +3.3V supply.
Digital +3.3V supply.
No Connect
N+1
CLK
tH
tS
Digital
Inputs
N+1
N
N+2
N+3
tD
VOP
1 LSB
N-2
N-1
N
N+1
VON
1 LSB
tsettling
NOTE: Not to scale. For definition purposes only.
Figure 1: Timing Diagram
REV. 1 June 2003
7
DATA SHEET
SPT5240
IOUT
Adjust
Sleep
Mode
Select
RSET
Clock In
CLK
ISET
PWD
VOP
IOP
50Ω
10-bit
Data Bus
SPT5240
AVDD
AGND
DVDD
DGND
50Ω
ION
0.01µF
0.01µF
0.1µF
0.1µF
FB
10µF
+
+
+D3.3V
10µF
VON
Notes:
1. FB = Ferrite Bead across analog and digital ground planes.
Place as close to DAC as feasible.
2. Minimum resistance (RSET) from ISET to ground relsults
in maximum current output.
3. PWD pin has an internal pull-down resistor.
Set pin high to initate sleep mode.
4. Outputs (IOP and ION) require minimum 5Ω load.
+A3.3V
Figure 2: Typical Interface Circuit Diagram
Typical Interface Circuit
The SPT5240 requires few external components to achieve
the stated performance. Figure 2 shows the typical interface
requirements when used in normal circuit operation. The
following sections provide descriptions of the major
functions and outline performance criteria to consider for
achieving optimal performance.
Digital Inputs
The SPT5240 has a 10-bit-wide parallel data input designed
to work at +3.3V CMOS levels. Fast edges and low
transients provide for improved performance.
Clock Input
The SPT5240 is driven by a single-ended clock circuit. In
order to achieve best performance at the highest throughput,
a clock generation circuit should provide fast edges
and low jitter.
Input Protection
All I/O pads are protected with an on-chip protection circuit.
This circuit provides robust ESD protection in excess of
3,000 volts, in human body model, without sacrificing speed.
8
Power Supplies and Grounding
The SPT5240 may be operated in the range of 3.0 to 3.6
volts. Normal operation is recommended to be separate
analog and digital supplies operating at +3.3 volts. All
power supply pins should be bypassed as close to the
package as possible with the smallest capacitor closest to
the device. Analog and digital ground planes should be
connected together with a ferrite bead as shown in Figure 2
and as close to the DAC as possible.
Sleep Mode
To conserve power, the SPT5240 incorporates a power down
function. This function is controlled by the signal on
pin PWD. When PWD is set high, the SPT5240 enters the
sleep mode. The analog outputs are both set to zero current
output, resulting in less than 10mA current draw from
the analog supply. For minimum power dissipation, data
and clock inputs should be set to logic low or logic high.
Reference
The SPT5240 utilizes an on-chip bandgap reference to set
full-scale output current level. The current reference to the
DAC circuitry is set by the external resistance value between
the ISET pin and analog ground.
REV. 1 June 2003
SPT5240
DATA SHEET
Analog Outputs
The SPT5240 provides differential current outputs which
provide an output level based on the value of RSET at
maximum output code (see Figure 3). The required value of
RSET may be calculated using the formulas:
35
RSET Steps = 2.75kΩ
IOUT (mA)
30
LSB = IFS/1023
25
20
15
10
Then:
5
RSET = 1.111 – (1000 • LSB)
4 • LSB
0
60.3
11.2
RSET Value (kΩ)
Where IFS is the desired full-scale current output.
Figure 3: RSET vs. IOUT
Each output requires a minimum 5Ω load to analog ground.
The typical circuit utilizes 50Ω loads to develop voltage for
the output transformer (refer to EB5240 data sheet).
Table 1: Input Data Format
Input Code D9 – D0
Analog Output
ION
IOP
0000000000
FS
0
1111111111
0
FS
Sleep XXXXXXXXXX
0
0
X indicates either data state.
Package Dimensions
LQFP-32
A
INCHES
G
B
H
C D
I
J
E
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
Min
0.346
0.272
0.346
0.272
0.031
0.012
0.053
0.002
0.037
0°
0.020
Max
0.362
0.280
0.362
0.280
Typ
0.016
0.057
0.006
0.041
0.007
7°
0.030
MILLIMETERS
Min
Max
8.80
9.20
6.90
7.10
8.80
9.20
6.90
7.10
0.80 BSC
0.30
0.40
1.35
1.45
0.05
0.15
0.95
1.05
0.17
0°
7°
0.50
0.75
F
K
L
REV. 1 June 2003
9
SPT5240
DATA SHEET
Ordering Information
Model
Part Number
Package
Container
Pack Qty
SPT5240
SPT5240SIT
32-pin LQFP
Tray
–
Temperature range for all parts: -40°C to +85°C.