TPS92023 www.ti.com SLUSBH3 – JUNE 2013 Resonant-Switching Driver Controller for LED Lighting Check for Samples: TPS92023 FEATURES 1 • • • • • • • • • • • • DESCRIPTION LLC Resonant Switching Driver Controller for Multi-String LED Lighting Applications Half-Bridge Topology Fixed or Variable Switching Frequency Control Programmable Soft-Start Time Programmable Dead Time for Best Efficiency Easy ON/OFF Control Overcurrent Protection Over-Temperature Protection Bias Voltage UVLO and OVP Integrated Gate Driver With 0.4-A Source and 0.8-A Sink Capability Operating Temperature Range: –40°C to 125°C SOIC 8-Pin Package The TPS92023 is a high-performance resonantswitching LED driver controller. It is designed for use in higher power LED lighting systems. The TPS92023 uses resonant switching in an LLC topology to achieve a very high efficiency compared to traditional half-bridge converters. The programmable dead time enables zero-voltage switching with minimum magnetizing current, maximizing system efficiency across a variety of applications. The TPS92023 can operate in two switching frequency modes. Fixed frequency allows for simple design when the load current is constant while variable switching allows for optimal closed-loop control for loads with varying currents. The internal oscillator supports the switching frequencies from 30 kHz to 380 kHz. This high-accuracy oscillator realizes the minimum switching frequency limiting with 4% tolerance, allowing the designer to avoid over-design of the power stage and, thus, further reducing overall system cost. APPLICATIONS • • • • • • • • • Commercial / Industrial LED Lighting Drivers High Bay LED Lighting Low Bay LED Lighting Street LED Lighting Area LED Lighting Stadium LED Lighting LED Wall Washing LED DTV and Monitor Back-lighting Electronic Lighting Ballasts UCC28810 Bias TPS92023 1 2 3 4 VSENS E VDD EAOUT GDRV VINS GND 8 3 OC VCC 7 2 RT 6 1 DT ISENSE TZE 4 5 7 GD1 8 GND 6 GD2 5 SS UDG-13072 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS92023 SLUSBH3 – JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) The programmable soft-start timer maximizes design flexibility demanded by the varied requirements of end equipments utilizing a half-bridge topology. The TPS92023 incorporates a 0.4-A source and 0.8-A sink for driving a low-cost gate driver transformer, delivering complete system protection functions including overcurrent, UVLO, bias supply OVP and OTP. Table 1. PACKAGE INFORMATION (1) (1) ORDERABLE DEVICE PINS PACKAGE OPERATING FREQUENCY OPERATING TEMPERATURE TPS92023D 8 SOIC Variable -40°C to 125°C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com/package. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) (4) over operating free-air temperature range (unless otherwise noted) VALUE MIN Voltage range Gate drive current – continuous Current range VCC UNITS MAX 22 GD1, GD2 -0.5 VVCC + 0.5 GD1, GD2 ± 25 RT –5 DT -0.7 Operating junction temperature TJ −40 125 Storage temperature Tstg −65 150 Electrostatic Discharge Human Body Model (HBM) Charged Device Model (CDM) Lead temperature (10 seconds) (1) (2) (3) (4) 2 2,000 500 V mA °C V 260 These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. All voltages are with respect to GND. All currents are positive into the terminal, negative out of the terminal. In normal use, terminals GD1 and GD2 are connected to an external gate driver and are internally limited in output current. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VVCC VCC input voltage from a low-impedance source 11.5 18.0 RRT RT resistor 1 8.666 RDT DT resistor 3.3 39 CSS SS capacitor 0.01 1 V kΩ μF THERMAL INFORMATION TPS92023 THERMAL METRIC (1) D (SOIC) UNITS 8 PINS Junction-to-ambient thermal resistance (2) θJA 117.3 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 57.5 ψJT Junction-to-top characterization parameter (5) 15.2 ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 63.4 (7) °C/W 57.0 n/a For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 3 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, −40°C < TA < 125°C, TJ = TA, VVCC = 12 V, GND = 0 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, CVCC = 1 μF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BIAS SUPPLY (VCC) 1 1.5 2.5 5 7.5 100 400 Measured at VCC rising 9.9 10.5 11.1 UVLO turn-off threshold Measured at VCC falling 8.9 9.5 10.1 UVLO hysteresis Measured at VCC 0.7 1 1.3 OVP turn-off threshold Measured at VCC rising 18 20 22 OVP turn-on threshold Measured at VCC falling 16 18 20 OVP hysteresis Measured at VCC 1.5 2 2.5 Dead time RDT = 16.9 kΩ 390 420 450 fSW(min) Minimum switching frequency at GD1, GD2 -40°C ≤ TA ≤ 125°C 40.04 41.70 43.36 -20°C ≤ TA ≤ 105°C 40.45 41.70 42.95 KICO Switching frequency gain/I (RT) RRT = 4.7 kΩ, IRT = 0 to 1 mA 60 80 100 t GD1, GD2 on- time mismatching fSW(clamp) Switching frequency clamp mode fSW(start) Switching frequency at soft start VUVLO VOVP VCC current, disabled SS = 0 V VCC current, enabled SS = 5 V, CGD1 = CGD2 = 1 nF VCC current, UVLO VCC = 9 V UVLO turn-on threshold mA μA V DEAD TIME (DT) tDT ns OSCILLATOR -50 kHz Hz/μA 50 ns kHz VSS = 5 V 330 380 430 -40°C ≤ TA ≤ 125°C 122 142.5 162 -20°C ≤ TA ≤ 105°C 125 142.5 160 1.3 EXTERNAL DISABLE/SOFT START ISS 4 Enable threshold Measure at SS rising 1.1 1.2 Disable threshold Measured at SS falling 0.85 1 Disable hysteresis Measured at SS 0.15 Disable prop. delay Measured between SS (falling) and GD2 (falling) 250 500 750 Source current on SS pin VSS = 0.5 V -225 -175 -125 Source current on SS pin VSS = 1.35 V -5.5 -5 -4.5 Submit Documentation Feedback 1.1 V 0.35 ns μA Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, −40°C < TA < 125°C, TJ = TA, VVCC = 12 V, GND = 0 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, CVCC = 1 μF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PEAK CURRENT LIMIT VOC1(off) Level 1 over current threshold – VOC rising 0.9 1 1.1 VOC2(off) Level 2 overcurrent latch threshold – VOC rising 1.8 2.0 2.2 VOC1(on) Level 1 over current threshold – VOC falling 0.5 0.6 0.7 tdOC Propagation delay 60 200 500 ns IOC OC bias current VOC = 0.8 V 200 nA GD1, GD2 output voltage high IGD1 = −20 mA, IGD2 = −20 mA GD1, GD2 on-resistance high IGD1 = −20 mA, IGD2 = −20 mA GD1, GD2 output voltage low GD1, GD2 on-resistance low tRISE Rise time GDx tFALL -200 V GATE DRIVE 9 11 V 12 30 Ω IGD1 = −20 mA, IGD2 = 20 mA 0.08 0.2 V IGD1 = −20 mA, IGD2 = 20 mA 4 10 Ω VVCC rising from 1 V to 9 V, CLOAD = 1 nF 18 35 Fall time GDx VVCC falling from 9 V to 1 V, CLOAD = 1 nF 12 25 GD1, GD2 output voltage during UVLO VVCC = 6 V, IGD1 = 1.2 mA, IGD2 = 1.2 mA ns 0.5 1.75 V THERMAL SHUTDOWN TSD Thermal shutdown threshold 160 Thermal shutdown recovery threshold 140 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 °C 5 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com DEVICE INFORMATION TPS92023 (Top View) DT 1 8 GD1 RT 2 7 VCC OC 3 6 GND SS 4 5 GD2 TERMINAL FUNCTIONS TERMINAL 6 DESCRIPTION NAME NO. I/O DT 1 I GD1 8 O GD2 5 O High-side and low-side switch gate driver. Connect gate driver transformer primary side to these two pins to drive the half bridge. GND 6 - Ground. OC 3 I Overcurrent protection. When the voltage on this pin is above 1 V, gate driver signals are actively pulled low. After the voltage falls below 0.6 V, the gate driver signal recovers with soft start. When OC pin voltage is above 2 V, the device is latched off. Bringing VCC below UVLO level resets the overcurrent latch off. Sets the dead time of high-side and low-side switch driving signals. Connect a resistor to ground. With internal 2.25-V voltage reference, the current flowing through the resistor sets the dead time. To prevent shoot through when this pin is accidentally short to ground, the minimum dead time is set to 120 ns. Any dead time setting less than 120 ns defaults to 120-ns dead time. RT 2 I The current flowing out of this pin sets the frequency of the gate driver signals. Connect the opto-coupler collector to this pin to control the switching frequency for regulation purpose. Parallel a resistor to ground to set the minimum current flowing out of the pin and set the minimum switching frequency. To set the maximum switching frequency limiting, place a resistor in series with the opto-coupler transistor. This resistor sets the maximum current flowing out of the pin and limits the maximum switching frequency. SS 4 I Soft-start. This pin sets the soft-start time of the system. Connect a capacitor to ground. Pulling this pin below 1 V disables the device to allow easy ON/OFF control. The soft-start function is enabled after all fault conditions, including bias supply OV, UVLO, overcurrent protection and over-temperature protection. VCC 7 - Bias supply. Connect this pin to a power supply less than 20 V. Place a 1-μF capacitor in parallel to ground to filter out noise. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 BLOCK DIAGRAM 2.25V DT T J 160oC/140oC + TSD Thermal ShutDown 1 OV + 10.5V 9.5V Dead time generator RDT 20V 18V UVLO + 7 VCC 2.5V Feed back RT 2 Ic 8 GD1 OSC Vss UVLO OV Q OC TSD SET VCC D 5 GD2 FAULT Q CLR 5uA 6 GND GD_Stop 6V 170uA OC SS 3 + OC 1V Vss 4 Css OC_latch + + 2V 1.2V/1V FAULT S R SET CLR Q Q Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 7 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS At VVCC = 12 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, VSS = 5 V, VOC = 0 V; all voltages are with respect to GND, TJ = TA = 25°C, unless otherwise noted. 1.0 350 0.9 300 Switching Frequency (kHz) Bias Supply Current (mA) 0.8 0.7 0.6 0.5 0.4 0.3 250 200 150 100 0.2 –40 °C 50 0.1 125 °C 0 0 6 7 8 9 10 11 12 13 14 0 Bias Supply Voltage (V) Figure 1. Bias Supply Current vs. Bias Supply Voltage 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Timing Resistance Current (mA) Figure 2. Switching Frequency vs. Timing Resistance 1000 1000 –40 °C 900 900 25 °C 125 °C 800 800 Dead Time (ns) 700 Dead Time (ns) 25 °C VOC = OPEN 600 500 400 700 600 500 400 300 300 200 200 100 100 0 0 –40 °C 25 °C 0 100 200 300 400 500 600 Dead Time Current (mA) Figure 3. Dead Time vs. Dead Time Current 8 700 125 °C 0 5 10 15 20 25 30 35 40 45 Dead Time Resistance (kW) Figure 4. Dead Time vs. Dead Time Resistance Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 TYPICAL CHARACTERISTICS (continued) Gate Drive Voltage 0.8 VCC = 15 V 12 1.2 12 0.6 10 1.0 10 0.5 8 0.8 8 0.4 6 0.6 6 0.3 4 0.4 4 0.2 2 Gate Drive Voltage (V) 14 Gate Drive Current (A) 1.4 14 Gate Drive Voltage (V) 16 1.6 VCC = 15 V 0.2 2 0 0 –0.2 600 –2 Gate Drive Voltage Gate Drive Current 0.7 Gate Drive Current (A) 16 0.1 Gate Drive Current 0 –2 0 100 200 300 400 500 0 0 Time (ns) Figure 5. Gate Drive Voltage vs. Gate Drive Current vs. Time 200 400 600 800 –0.1 1000 Time (ns) Figure 6. Gate Drive Voltage vs. Gate Drive Current vs. Time 12.0 300 UVLO-On Threshold (VCC Rising) UVLO-Off Threshold (VCC Falling) 11.5 UVLO Threshold Voltage (V) Propagation Delay Time (ns) 250 200 150 100 11.0 10.5 10.0 9.5 9.0 50 8.5 0 –60 –40 –20 0 20 40 60 80 100 120 140 Junction Temperature (°C) Figure 7. Propagation Delay Time vs. Temperature 8.0 –60 –40 –20 0 20 40 60 80 100 120 140 Junction Temperature (°C) Figure 8. UVLO Threshold Voltage vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 9 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 22.0 2.4 OVP-Off Threshold (VCC Rising) OVP-On Threshold (VCC Falling) 21.5 2.2 Overcurrent Threshold Voltage (V) Overvoltage Threshold (V) 21.0 20.5 20.0 19.5 19.0 18.5 18.0 17.5 17.0 2.0 1.8 OC Off Threshold (VOC Rising) OC On Threshold (VOC Falling) OC Latch Threshold (VOC Rising) 1.6 1.4 1.2 1.0 0.8 0.6 16.5 16.0 –60 –40 –20 0 20 40 60 80 0.4 –60 –40 –20 100 120 140 0 20 40 60 80 100 120 140 Junction Temperature (°C) Figure 10. Overcurrent Threshold Voltage vs. Temperature Junction Temperature (°C) Figure 9. Overvoltage Threshold vs. Temperature 100 90 On-Time Mismatch Time (ns) 80 70 60 50 40 30 20 10 0 0 50 100 150 200 250 300 350 Switching Frequency (kHz) Figure 11. On-Time Mismatch vs. Switching Frequency 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 APPLICATION INFORMATION Principle of Operation The soft-switching capability, high efficiency and long holdup time make the LLC resonant converter attractive for many applications, such as digital TV, ac/dc adapters and computer power supplies. Figure 12 shows the schematic of the LLC resonant converter. The LLC resonant converter is based on the series resonant converter (SRC). By using the transformer magnetizing inductor, zero-voltage switching can be achieved over a wide range of input voltage and load. As a result of multiple resonances, zero-voltage switching can be maintained even when the switching frequency is higher or lower than resonant frequency. This simplifies the converter design to avoid the zero-current switching region, which can lead to system damage. The converter achieves the best efficiency when operated close to its resonant frequency at a nominal input voltage. As the switching frequency is lowered the voltage gain is significantly increased. This allows the converter to maintain regulation when the input voltage falls low. These features make the converter ideally suited to operate from the output of a high-voltage boost PFC pre-regulator, allowing it to hold up through brief periods of ac line-voltage dropout. Due to the nature of resonant converter, all the voltages and currents on the resonant components are approximately sinusoidal. The gain characteristic of LLC resonant converter is analyzed based on the First Harmonic Approximation (FHA), which means all the voltages and currents are treated as sinusoidal shape with the frequency same as switching frequency. According to the operation principle of the converter, the LLC resonant converter can be draw as the equivalent circuit as shown in Figure 13. CR CR LR LR n:1:1 VGE LM LM RE VOE UDG-10044 UDG-10045 Figure 12. LLC Resonant Converter Figure 13. LLC Resonant Converter Equivalent Circuit In this equivalent circuit, the Vge and Voe are the fundamental harmonics of the voltage generated by the half bridge and the voltage on the transformer primary side, respectively. These voltages can be calculated through Fourier analysis. The load resistor Re is the equivalent resistor of the load, and it can be calculated as: æ ö 8 ÷ 2 RE = ç ´ (n ) ´ R ç p2÷ è( ) ø (1) Based on this equivalent circuit, the converter gain at different switching frequencies can be calculated as: æ ö ç ÷ ç VOUT ÷ = ç æ VDC ö ÷ çç ÷÷ èè 2 øø jw ´ LM ´ RE (jw ´ LM ) + RE jw ´ LM ´ RE 1 + + jw ´ LR (jw ´ LM ) + RE jw ´ CR where • VDC/2 is the equivalent input voltage due to the half-bridge structure (2) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 11 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com Table 2. Circuit Definition Calculations RESONANT FREQUENCY NORMALIZED GAIN æ ö ç ÷ V M = ç OUT ÷ ç æ VDC ö ÷ çç ÷÷ èè 2 øø f0 = NORMALIZED FREQUENCY QUALITY FACTOR 1 LR 2p ´ LR ´ CR QE = (4) CR RE (5) æ f ö fn = ç ÷ è f0 ø INDUCTOR RATIO æL ö Ln = ç M ÷ è LR ø (6) (7) (3) Following the definitions in Table 2, the converter gain at different switching frequencies can be calculated in Equation 8. 2 Ln ´ (fn ) M= 2 Ln ´ (fn ) + (fn - 1)´ (fn + 1 + j ´ fn ´ Ln ´ Qe ) where • • • • M is the converter voltage gain Ln is the ratio of the magnetizing inductance to the resonant inductance fn is the normalized switching frequency Qe is the quality factor (8) Because of the FHA, Equation 8 is an approximation. When the switching frequency moves away from the resonant frequency, the error becomes larger. However, this equation can be used as the design tool. The final results need to be verified by the time based simulation or hardware test. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 From Equation 8, when switching frequency is equal to resonant frequency, fn = 1 and converter voltage gain is equal to 1. Converter gain at different loads and inductor ratio conditions are shown in Figure 14 through Figure 17. 2 2 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1.5 M 1.5 M 1 0.5 0 0.1 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1 0.5 0.5 1 1.5 0 0.1 2 0.5 1 fn Figure 14. Normalized Switching Frequency vs.Converter Voltage Gain, Ln=1 2 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1.5 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1.5 M 1 0.5 0 0.1 2 Figure 15. Normalized Switching Frequency vs.Converter Voltage Gain, Ln=5 2 M 1.5 fn 1 0.5 0.5 1 1.5 2 0 0.1 fn 0.5 1 1.5 2 fn Figure 16. Normalized Switching Frequency vs.Converter Voltage Gain, Ln=10 Figure 17. Normalized Switching Frequency vs.Converter Voltage Gain, Ln=20 Based on its theory of operation the LLC resonant converter is controlled through Pulse Frequency Modulation (PFM). The output voltage is regulated by adjusting the switching frequency according to the input and output conditions. Optimal efficiency is achieved at the nominal input voltage by setting the switching frequency close to the resonant frequency. When the input voltage droops low the switching frequency is decreased to boost the gain and maintain regulation. The TPS92023 resonant half-bridge controller uses variable switching frequency control to adjust the resonant tank impedance and regulate output voltage. This 8-pin package device integrates the critical functions for optimizing the system performance while greatly simplifying the design and layout. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 13 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com Adjustable Dead Time Resonant half-bridge converter relies on the resonant tank current at MOSFETs turn-off to achieve soft switching and reduce switching loss. Higher turn-off current provides more energy to discharge the junction capacitor, while it generates more turn-off loss. Smaller turn-off current reduces turn-off loss, but it requires longer time to discharge MOSFETs junction capacitors and achieve soft switching. By choosing an appropriate dead time, turnoff current is minimized while still maintaining zero-voltage switching, and best system performance is realized. In TPS92023, dead time can be adjusted through a single resistor from DT pin to ground. With internal 2.25-V voltage reference, the current flow through the resistor sets the dead time. tD = 20ns + RDT ´ 24ns (9) To prevent shoot through when the DT pin accidentally connects to ground, the two gate driver outputs limit the dead-time to a minimum of 120-ns. Any dead-time setting less than 120-ns, defaults to the minimum 120-ns limit. Oscillator With variable switching frequency control, TPS92023 relies on the internal oscillator to vary the switching frequency. The oscillator is controlled by the current flowing out of RT pin. Except during soft start, the relationship between the gate signal frequency and the current flowing out of RT pin can be represented in Equation 10. 1 1 » IRT ´ 83Hz mA fSW = ´ 2 æ 6ns ´ 1A ö ç ÷ + 150ns è IRT ø (10) Since the switching frequency is proportional to the current, by limiting the maximum and minimum current flowing out of RT pin, the minimum and maximum switching frequency of the converter could be easily limited. As shown in Figure 18, putting a resistor from RT pin to ground limits the minimum current and putting a resistor in series with the opto-coupler limits the maximum current. Maximum Frequency Limiting TPS92023 R1 2 Minimum Frequency Limiting RT R2 UDG-13071 Figure 18. Maximum and Minimum Frequency Setting for TPS92023 The frequency limiting resistor can be calculated in Equation 11 through Equation 14. IF(max ) = IF(min ) = 14 6ns æ ö 1 çç ÷÷ - 150ns è (2 ´ fMAX ) ø 6ns æ ö 1 çç ÷÷ - 150ns è (2 ´ fMIN ) ø æ 1 1 ö IF(max ) = 2.5 V ç + ÷ è R1 R2 ø (11) IF(min ) = (13) Submit Documentation Feedback 2.5 V R2 (12) (14) Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 Soft Start During start up and fault recovery conditions, soft start is always implemented to prevent excessive resonant tank current and ensure Zero-Voltage Switching (ZVS). During soft start, the switching frequency is increased. The soft-start time can be programmed by placing a capacitor from SS pin to ground. The soft-start pin also serves as an ON/OFF control pin of the device. By actively pulling the SS pin below 1 V, the device is disabled. When the pull down is removed, SS pin voltage is increased because of internal charging current. Once SS pin becomes above 1.2 V, the device starts to generated gate-driver signal and enters softstart mode. The time sequence of soft start is shown in Figure 19. 4V 1.2 V VSS Gate Driver tSS tSS(delay) UDG-10047 Figure 19. Soft-Start Sequence To prevent a long delay between the ON command and appearance of a gate driver signal, the SS pin current is set as two different levels. When SS pin voltage is below 1.2 V, its output current is 175 μA. This high current could charge the soft-start pin capacitor to 1.2 V in a short period of time, and reduces the time delay. This time delay is calculated in Equation 15. 1.2 V ´ CSS tSS(delay ) = 175 mA (15) The switching frequency during soft start is determined by both the current flowing out of the RT pin and the voltage on SS pin. The switching frequency can be calculated based on the Equation 16. fSW = 1 ´ 2 1 6ns ´ 1A V æ ö IRT + ç 1.81mA - VSS ÷ 2.2k W è ø + 150ns (16) After the SS pin voltage reaches 4 V, the soft-start period ends and the switching frequency equals that as demanded by the RT pin current. The time used to charge the SS pin from 1.2 V to 4 V is defined as the softstart time and can be calculated in Equation 17. 2.8 V tSS = ´ CSS 5 mA (17) To ensure reliable operation, the gate drivers restart with GD2 turning high. This prevents uncertainty during system start up. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 15 TPS92023 SLUSBH3 – JUNE 2013 www.ti.com Overcurrent Protection To prevent power stage failure under excessive load current condition, the TPS92023 includes an overcurrent protection function. With a dedicated OC pin, the power stage is shut down when OC pin voltage is above 1 V. Once the OC pin voltage falls below 0.6 V, the gate driver recovers with a soft start. To enhance system safety, the TPS92023 latches up the entire system when the OC pin voltage rises above 2 V. Bringing the VCC voltage below the UVLO voltage level resets the device. The current can be indirectly sensed through the voltage across resonant capacitor by using the sensing network shown in Figure 20. LR From half-bridge TR LM D2 To OC CP RP RS CS D1 CR UDG-10048 Figure 20. Current Sensing for LLC Resonant Converter The general concept of this sensing method is that the ac voltage across the resonant capacitor is proportional to load current. According to the FHA model, peak voltage of the ac component on the resonant capacitor can be calculated in Equation 18. VCR(pk ) = jwn ´ Ln ´ (Qe + 1) 4 ´ n ´ VOUT p (w )2 ´ L n n (18) Therefore, the resonant capacitor voltage reaches its maximum value at the minimum switching frequency and maximum load. According to Equation 18, the current sensing network components can be calculated. Due to the nature of FHA, the final circuit parameters must be verified through actual hardware test. Table 3. Calculated Current Sensing Network Components SYMBOL RS CS RP CP 16 FUNCTION Transfer ac voltage across resonant capacitor into current source Blocking dc voltage on resonant capacitor Load resistor of the current source DESIGN EQUATION Rs CS = RP = CP = Filter capacitor Submit Documentation Feedback 2 (V = CR(pk )MAX ) 2 ´ PRS(max ) (19) 10 RS ´ fMIN RS VCR(pk )MAX (20) ´ p 2 (21) 10 (RP´ fMIN ) (22) Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 TPS92023 www.ti.com SLUSBH3 – JUNE 2013 Gate Driver Half-bridge resonant converter is controlled by the nearly 50% duty cycle variable frequency square wave voltage. This allows the half bridge to be easily driven by the gate-driver transformer. Compared with a halfbridge driver device, a gate-driver transformer provides a simple and reliable solution, which: • Eliminate the need for gate driver power supply • Enable simplified layout • Preventing shoot through due to the transformer coupling • No latch up The TPS92023 integrates two-gate drivers with 0.4-A source and 0.8-A sink capability to directly drive the gate driver transformer. For LLC resonant converter, it is critical for the gate-driver signal to be precisely symmetrical. Otherwise, the resonant tank operation is symmetrical. The load current distribution is unbalanced for the output rectifiers, which in turn requires over design of the power stages and thermal management. In TPS92023, the gate-driver output is precisely trimmed to have less than 50 ns mismatch. Although the gatedriver signal is quite symmetrical, it is still recommended to insert the dc blocking capacitor in the gate-driver transformer primary side to prevent transformer saturation during fast transients. VCC Pin Connect a regulated bias supply to VCC pin. When VCC becomes above 10.5 V the device is enabled and after all fault conditions are cleared the gate driver starts with soft start. When the VCC voltage drops below 9.5 V, the device enters UVLO protection mode and both gate drivers are actively pulled low. When VCC rises above 20 V the device enters VCC overvoltage protection mode and the device is disabled with both gate drivers actively pulled low. VCC overvoltage protection recovers with soft-start operation when the VCC voltage returns below 18 V. Over-Temperature Protection TPS92023 continuously senses its junction temperature. When the junction temperature rises above 160°C the device enters over-temperature protection mode with both gate drivers actively pulled low. When junction temperature drops below 140°C, gate driver restarts with soft start. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS92023 17 PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS92023D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 92023D TPS92023DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 92023D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS92023DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92023DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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