F72569
ACPI Controller IC for AMD K8/AM2 Platform
Release Date: Oct, 2006
Version: 0.26P
Fintek
Feature Integration Technology Inc.
F72569
F72569 Datasheet Revision History
Version
Date
Page
Revision History
0.20P
Dec, 2005
Preliminary version
0.21P
Apr, 2006
Model name modification
Re-compose
0.22P
May, 2006
1
Delete the description about Vref for overclock
14
Description of linear controller correction
23
Application circuit correction
0.23P
June, 2006
1
Delete the description about Vref in general description
0.24P
Aug, 2006
11
Add over current protection description
0.25P
Sep,2006
3
Pin description
20
Application circuit correction
0.26P
Oct, 2006
20
Application circuit correction
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
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F72569
Table of Contents
1
GENERAL DESCRIPTION ........................................................................................................................................................ 1
2
FEATURE ..................................................................................................................................................................................... 1
3
PIN CONFIGURATION .............................................................................................................................................................. 2
4
PIN DESCRIPTION..................................................................................................................................................................... 2
5
ELECTRICAL CHARACTERISTIC......................................................................................................................................... 6
6
BLOCK DIAGRAM ..................................................................................................................................................................... 8
7
SIMPLIFIED POWER SYSTEM DIAGRAM .......................................................................................................................... 9
8
FUNCTIONAL DESCRIPTION ................................................................................................................................................. 9
9
8.1
ACPI STATE .............................................................................................................................................................................. 9
8.2
CHARGE PUMP ........................................................................................................................................................................ 10
8.3
SOFT-START ............................................................................................................................................................................ 10
8.4
REFERENCE VOLTAGE ............................................................................................................................................................. 10
8.5
OVER-CURRENT PROTECTION ................................................................................................................................................. 11
8.6
ACCESS INTERFACE ................................................................................................................................................................ 11
REGISTER DESCRIPTION ..................................................................................................................................................... 13
9.1 Register Index 01h .............................................................................................................................................................. 13
9.2
PWM_VRAM_11, PWM_VRAM_10 Fine Tune Voltage Register Index 02h ................................................................. 13
9.3 Register Index 03h .............................................................................................................................................................. 13
9.4
PWM_VTT_10, PWM_VTT_11 Fine Tune Voltage Register Index 04h.......................................................................... 14
9.5 Register Index 05h .............................................................................................................................................................. 14
9.6
LR_VDDA_10, LR_VDDA_11 Fine Tune Voltage Register Index 06h ........................................................................... 14
9.7 Register Index 07h .............................................................................................................................................................. 15
9.8
LRVLDT_10, LRVLDT_11 Fine Tune Voltage Register Index 08h ................................................................................. 15
9.9
LRVDDA, LRVLDT Fine Tune Voltage Register Index 09h ............................................................................................ 15
9.10
LED ACPI Frequency setting Register Index 0Ah .......................................................................................................... 16
9.11
PLED ACPI Frequency setting Register Index 0Bh ........................................................................................................ 16
9.12
SLED ACPI Frequency setting Register Index 0Ch ........................................................................................................ 17
9.13
Under Voltage, Over Current Enable Protection Register Index 10h............................................................................... 17
9.14
Register Index 11h ........................................................................................................................................................... 17
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F72569
9.15
Register Index 12h........................................................................................................................................................... 17
10 ORDERING INFORMATION .................................................................................................................................................. 18
11 PACKAGE DIMENSIONS (48LQFP)...................................................................................................................................... 19
12 APPLICATION CIRCUIT ........................................................................................................................................................ 20
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F72569
1 General Description
The F72569 is a fully compliant ACPI controller IC specific for AMD K8 CPU platform. The chip is used with an ATX
power supply, and it integrates synchronous PWM controllers, regulators, several linear controllers, switching
signals, monitoring and control function into a 48 pin LQFP package. Its operation mode (sleep or active) is
selectable through some control signals. The F72569 provides 3 switch signals which can provide 5VDUAL, 5VUSB &
3.3VDUAL etc. The F72569 can also provide 5 linear regulators for system requirements. This chip integrates a
charge pump engine to provide higher driving voltage for appropriate gate during standby. Besides, this chip offers
current limiting that protects each PWM outputs, and provides soft-start for a linear regulator to avoid rush current.
The power LED is programmable and compliant with PC2001. Moreover, this high-performance chip integrates I2C
interface and provides adjustable linear controllers mechanism for dynamic over/under-voltage use. This chip is in
a 48pin LQFP package and powered by 5VSB.
2 Feature
Compliant with AMD K8 timing sequence
Provide 3 switching controlled signals for 5VDUAL, 5VUSB and 3.3VDUAL
Programmable 5VDUAL/5VSTR/5VCC for USB device wake up
Provide 5 linear controller and typically use for –
-- 1 channel for DUAL3V power
-- 1 channel for VDDA power
-- 1 channel for VLDT power
-- 2 channels for 0.8~5V voltage requirement
Provide one PWM controller for DDR VDDQ
Provide one PWM regulator for chipset power requirement
1 PWROK input signal(typically from ATXPWOKIN) and 1 PWROK output signal
Provide resume reset signal(RSMRST#)
Programmable power LED control
Provide VREF and VSB9V voltage for generating different voltage use
Power up soft-start and under-voltage monitoring for the linear regulators
Over current protection(OCP) on PWM controller and under-voltage monitoring of all linear regulators
Integrate I2C interface
48 pin LQFP package and 5VSB operation
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F72569
3 Pin Configuration
4 Pin Description
I/O12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/O12ts
- TTL level and schmitt trigger
I/OD16
- TTL level bi-directional pin. Open-drain output with 16 mA sink capability
OUT12
- Output pin with 12 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
OD16
- Open-drain output pin with 16 mA sink capability
OD24
- Open-drain output pin with 24 mA sink capability
O24V4
- Output pin with 24mA driving capability, output 4V
INt
- TTL level input pin
INts
- TTL level input pin and schmitt trigger
AIN
- Input pin(Analog)
AOUT
- Output pin(Analog)
P
- Power
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F72569
Power Pins
PIN NO
PIN NAME
8
GND
12
VSB5V
21
GND
30
GND
32
VSB5V
42
GND
45
VCC3V
18
VCC_PWM
TYPE
DESCRIPTION
Power pins
P
VRAM_UGATE and VRAM_LGATE signal power, recommend to connect to
Vcc12V
Reset & Power Good & Control signal
PIN NO
PIN NAME
TYPE
PWR
DESCRIPTION
1
PS_ONIN#
INts
VSB5V
Normal power control signal input.
2
PS_ONOUT#
OD12
VSB5V
Power control signal output. Connected to ATX power ON/OFF pin, normally.
3
S5#
INts
VSB5V
A low active ACPI control signal governs the S5 state. Typically, connected to
chipset S5# signal.
10
VCORE_EN
OD12
VSB5V
This pin is the open drain output to control CPU Vcore power enabled signal.
11
VCORE_GD
INts
VSB5V
This pin is the CPU Vcore power ready signal input.
43
RSMRST#
OD12
VSB5V
44
PWOK
OD16
VSB5V
Power Good output signal.
46
TURBO#
INts
VSB5V
Enable adjustable power signal.
47
FAULT#
INts
VSB5V
Error input signal for power off.
48
PWOKIN
INts
VSB5V
As VSB arrives at 3.3V, this pin will generate RSMRST# signal output after
66ms.
Power Good Schmitt Trigger input signal. Typically, connected to ATX power
Good.
Switching Signal & Linear/PWM Controller
PIN NO
PIN NAME
TYPE
PWR
DESCRIPTION
13
VTT_PWM
OUT5
VSB5V
External buffer PWM control output signal
14
VTT_FB
AIN
VSB5V
External buffer PWM feedback signal
15
COMP
AOUT
VSB5V
Output of the error amplifier used to compensate the feedback loop of
the PWM controller.
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F72569
16
VRAM_FB
AIN
VSB5V
VRAM PWM feedback signal
17
VRAM_OPS
AOUT/AIN
VSB5V
VRAM PWM current protection signal
19
VRAM_LGATE
O
VCC_PWM
VRAM PWM low gate control signal
20
VRAM_UGATE
O
VCC_PWM
VRAM PWM up gate control signal
22
VTT_OPS
AOUT/AIN
VSB9V
24
VLDT_SEN
AIN
VSB5V
External buffer PWM current protection signal
Sense the voltage of the linear regulator. VLDT_SEN and VLDT_DRV
act as a linear regulator and generate voltage for S0 state power.
Connect this pin to the gate of a suitable N-channel MOSFET.
25
VLDT_DRV
AOUT
VSB9V
VLDT_SEN and VLDT_DRV act as a linear regulator and generate
voltage for S0 state power.
Connect this pin to the gate of a suitable N-channel MOSFET.
26
VDDA_DRV
AOUT
VSB9V
VDDA_SEN and VDDA_DRV act as a linear regulator and generate
voltage and generate voltage for S0 sate power.
Sense the voltage of the linear regulator. VDDA_SEN and VDDA_DRV
27
VDDA_SEN
AIN
VSB5V
act as a linear regulator and generate voltage and generate voltage for
S0 sate power.
Sense the voltage of the linear regulator. LR1_SEN and LR1_DRV act
33
LR1_SEN
AIN
VSB5V
as a linear regulator and generate voltage for standby or STR power.
The default is for standby power. If VIN is main power, it can generate
voltage for S0 sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
34
LR1_DRV
AOUT
VSB9V
LR1_SEN and LR1_DRV act as a linear regulator and generate voltage
for standby or STR power. The default is for standby power. If VIN is
main power, it can generate voltage for S0 sate power.
Connect this pin to the gate of a suitable N-channel MOSFET.
LR2_SEN and LR2_DRV act as a linear regulator and generate voltage
35
LR2_DRV
AOUT
VSB9V
for standby or STR power. The default is for standby power. If VIN is
main power, it can generate voltage for S0 sate power.
Sense the voltage of the linear regulator. LR2_SEN and LR2_DRV act
36
LR2_SEN
AIN
VSB5V
as a linear regulator and generate voltage for standby or STR power.
The default is for standby power. If VIN is main power, it can generate
voltage for S0 sate power.
Sense the voltage of the linear regulator. VDUAL3V_SEN and
37
DAUL3V_SEN
AIN
VSB5V
VDUAL3V_DRV act as an adjustable linear regulator and this regulator
is typically incorporated with VCCGATE to generate dual voltage.
Connect this pin to the gate of a suitable N-channel MOSFET.
38
DUAL3V_DRV
AOUT
VSB9V
VDUAL3V_SEN and VDUAL3V_DRV act as an adjustable linear
regulator and this regulator is typically incorporated with VCCGATE to
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F72569
generate dual voltage.
Connect this pin to the gate of a suitable N-channel MOSFET.
Generate dual 3.3V voltage with VDUAL3V_DRV and
39
VCCGATE
AOUT
VSB9V
VDUAL3V_SEN. Generate USB voltage with USBGATE. Generate
dual 5V voltage with DUALGATE.
Connect this pin to the gate of a suitable N-channel MOSFET.
40
USBGATE
AOUT
VSB9V
Generate USB voltage with VCCGATE.
Connect this pin to the gate of a suitable N-channel MOSFET.
41
DUALGATE
AOUT
VSB9V
Generate dual 5V voltage with VCCGATE.
Charge Pump
PIN NO
PIN NAME
TYPE
PWR
28
CP
P
VSB9V
DESCRIPTION
Charge pump output (9V nominal). Decouple this pin with 1uF ceramic
capacitor. VSB9V power output.
29
C2
AOUT
VSB9V
31
C1
AOUT
VSB5V
Positive end of charge pump capacitor
Negative end of charge pump capacitor. Connect a 1uF ceramic capacitor
between C1 and C2
Power LED
PIN NO
PIN NAME
TYPE
PWR
6
PLED
OD24
VSB5V
Power LED. Can be programmed by setting register
7
SLED
OD24
VSB5V
Suspend LED. Can be programmed by setting register
PIN NAME
TYPE
PWR
DESCRIPTION
4
SCLK
INts
VSB5V
I2C serial bus clock
5
SDATA
I/OD12ts
VSB5V
I2C serial bus data
9
VREF
AOUT
VSB5V
Provide 1.25V reference voltage
23
SS
AIN
VSB5V
DESCRIPTION
Others
PIN NO
Soft-Start. Connect this pin to a small ceramic capacitor to determine the
soft-start rate. The value of capacitor is bigger, and the slew rate is slower.
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F72569
5 Electrical Characteristic
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATINGS
UNIT
IC supply voltage
VCC
V
ESD classification
HBM
kV
Tj
°C
TSTO
°C
※ Maximum junction temperature (plastic package)
※ Maximum storage temperature
※ Maximum lead temperature (soldering 10s)
°C
Note: If ICs are stressed beyond the limits listed in the “absolute maximum ratings”, they may be permanently destroyed. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DC and AC electrical characteristics (VCC = 12V, TA = 25°C)
PARAMETER
SYMBOL TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
6
15
mA
VCC SUPPLY CURRENT/Regulated Voltage
Nominal supply current 5VCC
ICC
UGATE, LGATE and DRIVE2 open
POWER-ON RESET
Rising VCC threshold
3.0
3.3
3.6
V
Falling VCC threshold
2.7
3.0
3.3
V
200
250
300
kHz
OSCILLATOR AND Soft-start
Free running frequency
※ Ramp Amplitude
FOSC
1.5
△VOSC
VP-P
Soft-start interval
TSS
Css=0.1u
8.4
12.4
17.4
ms
Dead time
TDT
2V to 2V
20
30
50
ns
VREF
VCC=5V, T= 25
0.784
0.8
0.816
V
REFERENCE VOLTAGE
Reference voltage
PWM CONTROLLER GATE DRIVERS
Upper Drive Source
RUGATE
VDS = 1V, VGS = 12V,
7
14
Ω
Upper Drive Sink
RUGATE
VDS = 1V, VGS = 12V
5
10
Ω
Lower Drive Source
RLGATE
VDS = 1V, VGS = 12V
7
14
Ω
Lower Drive Sink
RLGATE
VDS = 1V, VGS = 12V
5
10
Ω
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F72569
PARAMETER
SYMBOL TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Error Amplifier
Slew Rate
SR
4.5
V/us
※ DC Gain
A0
34
dB
70
dB
1.86
MHz
Slew Rate
38
V/us
Drive High Output Voltage
12
V
Drive Low Output Voltage
0
V
Linear Regulator
DC Gain
Gain Bandwidth Product
Drive High Output Source Current
Vo=9V; VDDA=10V
Drive Low Output Sink Current
Vo=1V; VDDA=10V
-0.54
mA
0.52
mA
40
uA
Protection
OCSET Current Source
FB Under Voltage Trip
IOCSET
FB Falling
0.4
0.5
0.6
V
VRAM(VDDQ) UV Level
0.4
0.5
0.6
V
VTT_PWM (VGMCH) UV Level
0.4
0.5
0.6
V
Charge Pump
Charge Pump Frequency
250
KHz
Charge Pump Voltage
9.5
V
9.5
V
Switch Controller
DUALGATE Output High Voltage
VCCGATE Output High Voltage
10.8
12
13.2
V
USBGATE SS Source Current
10.8
12
13.2
V
※: Design Guarantee
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F72569
6 Block Diagram
PLED SLED S5# SS
PWOK
PWOKIN
FAULT#
TURBO#
PS_ONIN#
PS_ONOUT#
RSMRST#
VCORE_EN
VCORE_GD
1.25VREF
SCLK
SDATA
I2C
Interface
VREF
Control
Logic
VTT PWM
Regulator
VRAM PWM
Controller
F72569DG
DUAL3V_DRV
DUAL3V_SEN
VSB5V VCC3V
Linear
Controller 1
VRAM_UGATE
VRAM_LGATE
VRAM_OPS
VRAM_FB
LR1_DRV
LR1_SEN
3VDUAL
Linear
LR Controller
Controller 2
VCCGATE
USBGATE
DUALGATE
VTT_PWM
VTT_COMP
VTT_OPS
VTT_FB
5VDUAL
5VUSB
LR3_SEN
VLDT
VDDA
LR Controller
LR Controller
Charge
Pump
LR3_DRV VDDA_DRV VDDA_SEN CP
8
LR2_DRV
LR2_SEN
GND
C1 C2
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7 Simplified Power System Diagram
VCORE
12V
Multi-Phase
PWM
VCORE_EN
MOSFET
Driver
AMD
CPU
VCORE_GD
VDDA (2.5V/200mA)
VLDT (1.2V)
5VSB
3V
Fintek
F72569
VTT_PWM
PCIE x 16
Chipset
MOSFET
Driver
PCIE x 1
PCIE_PWR(1.5V)
USB_DUAL(5V)
USB Device
DUAL_3V
Other Device
ATX
Power
VRAM_UGATE
VDDQ
VRAM_LGATE
DRAM
2.5V/1.8V
DUAL_5V
8 Functional Description
8.1 ACPI state
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the usage of power in a
computer. It lets computer manufacturers and users to determine the power usage of computer dynamically.
There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3
and S5. S0 is a full-power state and the computer is being actively used in this state. The other two are called sleep
states and reflect different power consumption when power-down. S3 is a state the processor is powered down but
the last state is being stored in memory which is still active. S5 is a state that memory is off and the last state of the
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processor has been stored to the hard disk. Take S3 and S5 as a comparison, the computer can come back more
quickly to full-power state in S3 than S5 due to data restored from the memory is faster than from the hard disk.
However, S5 draws the minimal power compared to S0 and S3 because of powering off the memory.
It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and S3→
S5. Among them, S3→S5 is an illegal transition and won’t be allowed by state machine. In order to enter to S5 from
S3, it is necessary to come back to S0 first. The transition S5→S3 will occur only as an immediate state during
state transition from S5→S0. It isn’t allowed in the normal state transition.
8.2 Charge pump
The F72569 is incorporated with an embedded charge pump to provide higher driving voltage. Pin 29(CP) supports
10mA driving current and ensures 9V output voltage or above. In main operation, the VSB9V signals of the F72569
are run from the +12V supplied by ATX power which also supplies to other MOSFET gates. However, during
standby state, the +12V will be off and it needs to provide power to the chip and the appropriate gates. Therefore,
the F72567 is incorporated with a free running charge pump. As shown in the schematic, there is a capacitor
connected between C1 and C2 of the F72569 act as a charge pump with internal diodes. There must be a serial
diode in the 12V input to prevent back-feeding the charge pump to the +12V main in standby. It also needs a
bypass capacitor connected with 12V input line to filter high-frequency noise.
8.3 Soft-start
SS of the F72569 acts as a soft-start function. As shown in the schematic, a ceramic capacitor is attached between this pin and
the ground. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly
ramping up the voltage. This ramp in turn controls the internal reference of the F72569 which provides a soft-start for the linear
regulator. Switches must be either on or off in the system to avoid the effect on them from the soft-start. It is important to know
soft-start is not an enable signal, pulling it low will not be sure to turn off all outputs. If there are appropriate signals asserted, the
switches will be turned on at once. The actual state of the F72569 in power up will be determined by the controlled input signal
and the soft-start is effective only during power on.
8.4 Reference voltage
The pin10 (VREF) is an output pin that is driven by a small output buffer to provide the 1.25V reference voltage to other devices
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in the system.
8.5 Over-current Protection
To sense the low-side MOSFET’s RDS (ON) to set over-current trip point. Connecting a resistor (ROCSET) from this pin to
PHASE to set the over-current trip point, ROCSET, an internal 40µA current source, and the lower MOSFET on resistance, RDS
(ON), sets the converter over-current trip point (IOCSET) according to the following equation:
8.6 Access interface
The F72569 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device
under the control of the master device, using two device terminals SCL and SDA. The controller can provide a clock
signal to the device SCL pin and read/write data from/to the device through the device SDA pin. The default
address is 0x5E(0101_1110) and the operation of the device to the bus is described with details in the following
sections.
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(a) SMBus write to internal address register followed by the data byte
0
7
8
0
7
8
SCLK
SDA
0
1
0
Start By
Master
1
1
1
R/W
1
D7
D6
Ack
by
569
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
569
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Stop
by
Master
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0
7
8
0
7
8
SCL
SDA
0
1
Start By
Master
0
1
1
1
1
R/W
D7
D6
Ack
by
569
Frame 1
Serial Bus Address Byte
D5
D4
D3
D2
D1
D0
Ack
by
569
Frame 2
Internal Index Register Byte
Stop by
Master
0
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
7
8
0
7
8
SCL
SDA
0
Start By
Master
1
0
1
1
1
1
R/W
D7
Ack
by
569
Frame 1
Serial Bus Address Byte
D6
D5
D4
D3
D2
Frame 2
Internal Index Register Byte
D1
D0
Ack
Stop by
by
Master Master
1
Figure 3. Serial Bus Read from Internal Address Register
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9 Register Description
9.1
Register Index 01h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.2
Bit
PWM_VRAM_11, PWM_VRAM_10 Fine Tune Voltage Register Index 02h
Name
R/W
Default
7:4
PWMVRAM_11
R/W
3
3:0
PWMVRAM_10
R/W
3
9.3
Description
According to Turbo hardware pin setting, to fine tune PWM_VRAM
reference voltage. If Turbo = 1, the PWM_VRAM Voltage table is set by
Register 02h bit 7:4.
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune PWM_VRAM
reference voltage. If Turbo = 0, the PWM_VRAM Voltage table is set by
Register 02h bit 3:0.
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
Register Index 03h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
13
2006 V0.26P
Fintek
9.4
Bit
Feature Integration Technology Inc.
PWM_VTT_10, PWM_VTT_11 Fine Tune Voltage Register Index 04h
Name
R/W
Default
7:4
PWMVTT_11
R/W
3
3:0
PWMVTT_10
R/W
3
9.5
F72569
Description
According to Turbo hardware pin setting to fine tune PWM_VTT reference
voltage. If Turbo = 1, the PWM_VTT Voltage table is set by Register 04h bit
7:4.
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune PWM_VTT reference
voltage. If Turbo = 0, the PWM_VTT Voltage table is set by Register 04h bit
3:0
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
Register Index 05h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.6
Bit
7:4
LR_VDDA_10, LR_VDDA_11 Fine Tune Voltage Register Index 06h
Name
LRVDDA_11
R/W
R/W
Default
Description
3
According to Turbo hardware pin setting to fine tune LR_VDDA reference
voltage. If Turbo = 1, the LR_VDDA Voltage table is set by Register 06h bit
7:4.
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
14
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
3:0
9.7
LR_VDDA_10
R/W
3
According to Turbo hardware pin setting to fine tune LR_VDDA reference
voltage. If Turbo = 0, the LR_VDDA Voltage table is set by Register 06h bit
3:0
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
Register Index 07h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.8
Bit
LRVLDT_10, LRVLDT_11 Fine Tune Voltage Register Index 08h
Name
R/W
Default
7:4
LRVLDT_11
R/W
3
3:0
LRVLDT_10
R/W
3
9.9
Description
According to Turbo hardware pin setting to fine tune LRVLDT reference
voltage. If Turbo = 1, the LRVLDT Voltage table is set by Register 08h bit
7:4.
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
According to Turbo hardware pin setting to fine tune LRVLDT reference
voltage. If Turbo = 0, the LRVLDT Voltage table is set by Register 08h bit
3:0
0000 : 0.74V
1000 : 0.90V
0001 : 0.76V
1001 : 0.92V
0010 : 0.78V
1010 : 0.94V
0011 : 0.80V
1011 : 0.96V
0100 : 0.82V
1100 : 0.98V
0101 : 0.84V
1101 : 1.00V
0110 : 0.86V
1110 : 1.02V
0111 : 0.88V
1111 : 1.04V
The function must be enable by Register 09 Bit3 and Register 0A bit 3
LRVDDA, LRVLDT Fine Tune Voltage Register Index 09h
Bit
Name
R/W
Default
Description
7-6
USBMODE
R/W
1
USB Power mode select, 00:DUAL 01:STR 10:OFF 11:OFF
5
Reserved
R/W
1
Reserved
4
Reserved
R/W
0
Reserved
3
TURBO_EN
R/W
0
TURBO function Enable, if set to 1 the register 01~08h will enable fine
tune function when the fine tune setting is Turbo mode (Register 0A bit 3)
15
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
2
TURBO_INV
R/W
0
1
Reserved
R/W
0
0
FAULT_EN
R/W
0
9.10
Bit
TURBO function sequence inverter.
TURBO_INV=0: If TURBO value changes from 0 to 1, it will fine tune
directly, Otherwise, it will delay 20ms to fine tune reference voltage.
TURBO_INV=1: If TURBO value changes from 1 to 0, it will fine tune
directly. Otherwise, it will delay 20ms to fine tune reference voltage
Reserved
When register 09H bit 1 is set to FAULT_N mode, Set this bit to 1 to
enable FAULT Function, When FAULT_N is low in S0 State, it will Shut
down PWM_VRAM, PWM_VTT, LR_PCIE, LR_VID directly,.
LED ACPI Frequency setting Register Index 0Ah
Name
R/W
Default
Description
5-4
SLED_SET[9:8]
R/W
3
VFB_SEL
R/W
0
2
LED_INV
R/W
1
PLED frequency setting, When PLED_SET[9:8] set equal to S3_N, S5_N,
the PLED pin will be tri-state (OD)
*note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent
S5 State, {1,0} the state is reserved
SLED frequency setting, When SLED_SET[9:8] set equal to S3_N, S5_N,
the PLED pin will be tri-state (OD)
*note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent
S5 State, {1,0} the state is reserved
Manual mode or Turbo mode selection, 0:turbo 1:Manual
If the setting is Turbo mode, set register 09H bit 3 to enable the fine tune
function.
If the setting is Manual mode, Write Register 02/04/06/08 Bit [7:4] to fine
tune voltage.
Set to 1 , the PLED and SLED CLK is inverted
1
VRAM_OCEN
R/W
1
PWM_VRAM Over current enable
0
VTT_OCEN
R/W
1
PWM_VTT Over current enable
7-6
PLED_SET[9:8]
R/W
0
3
9.11
Bit
7-0
PLED ACPI Frequency setting Register Index 0Bh
Name
PLED_SET[7:0]
R/W
R/W
Default
9B
Description
PLED frequency setting, When the
PLED_SET[7:6] = S3_N, S5_N, PLED will be 1HZ toggle pulse with 50
duty cycle
PLED_SET[5:4] = S3_N, S5_N, PLED will be 1/2 HZ toggle pulse with 50
duty cycle
PLED_SET[3:2] = S3_N, S5_N, PLED will be 1/4HZ toggle pulse with 50
duty cycle
PLED_SET[1:0] = S3_N, S5_N, PLED will drive low
*note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent
S5 State, {1,0} the state is reserved
16
2006 V0.26P
Fintek
9.12
Bit
7-0
9.13
Feature Integration Technology Inc.
SLED ACPI Frequency setting Register Index 0Ch
Name
SLED_SET[7:0]
R/W
R/W
Default
98
Description
SLED frequency setting, When the
SLED_SET[7:6] = S3_N, S5_N, SLED will be 1HZ toggle pulse with 50
duty cycle
SLED_SET[5:4] = S3_N, S5_N, SLED will be 1/2 HZ toggle pulse with 50
duty cycle
SLED_SET[3:2] = S3_N, S5_N, SLED will be 1/4HZ toggle pulse with 50
duty cycle
SLED_SET[1:0] = S3_N, S5_N, SLED will drive low
*note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent
S5 State, {1,0} the state is reserved
Under Voltage, Over Current Enable Protection Register Index 10h
Bit
Name
R/W
Default
7
VDDA_UVEN
R/W
1
VDDA Under voltage enable
6
VLDT_UVEN
R/W
1
VLDT Under voltage enable
5
VDUAL3V_UVEN
R/W
1
VDUAL3V Under voltage enable
4
LR1_UVEN
R/W
1
LR1 Under voltage enable
3
LR2_UVEN
R/W
1
LR2 Under voltage enable
2
Reserved
R/W
1
Reserved
1
PWM_VTT_UVEN
R/W
1
PWM_VTT Under voltage enable
PWM_VRAM_UVEN R/W
1
PWM_VRAM Under voltage enable
0
9.14
Bit
7
6
5
F72569
Description
Register Index 11h
Name
DUAL[1:0]
Delay[1:0]
4
R/W
Default
R/W
0
R/W
1
R/W
1
R/W
1
Description
DUAL3V selection 00:3.21V, 01 : 3.3V, 10 :3.38V, 11: 3.456v,
V3VOK delay timer, 00: 100ms, 01: 200ms, 10 : 300ms, 11 : 400ms
3
Reserved
R/W
0
Reserved
2
Reserved
R/W
0
Reserved
0
Reserved Function: when set to 1, it can decrease regulators VFB
voltage, it must fix the related fine tune register bit2, bit 3 to zero, for
example 100XX, It provide 4 kinds decrease voltage
10000 : 0.72V
10001 : 0.70V
10010 : 0.68V
10011 : 0.66V
Set to 1 can toggle S5_N to recovery, if VRAM, VTT, LR_PCIE, LR_VID
Shut down by Over current or Under voltage or Fault_N SD , Set to 0,
must power off to recovery.
1
DEC_VFB
R/W
0
PROTECTION_SEL
R/W
0
9.15
Bit
7
Register Index 12h
Name
R/W
PROG_PSN_OUT_S
R/W
ET
Default
0
Description
If Register 12H bit 4 set to 1, write this bit to1 can set PSON_OUT to high.
17
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
6
SAME_UV
R/W
1
5
PSON_OUT_UV
R/W
0
4
SOFT_PSON_OUT
R/W
0
Set to 1 will Set the VRAM, VDDA, VTT, VLDT Shut down when each
power occurs fault event
Set to 1 will Set the PSON_OUT to high when VRAM, VDDA, VTT, VLDT
power fault event occurs
Set to 1 can program PSON_OUT to HIGH
3
Reserved
R/W
0
Reserved
2
Reserved
R/W
0
Reserved
1
Reserved
R/W
0
Reserved
0
Reserved
R/W
0
Reserved
10 Ordering Information
Part Number
Package Type
Production Flow
F72569DG
48-LQFP (Green Package)
Commercial, 0°C to +70°C
18
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
11 Package Dimensions (48LQFP)
HD
D
25
36
Dimension in inch
Symbol
E
48
HE
13
1
e
b
Nom.
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
Min.
12
0
Max.
Dimension in mm
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
7.00
7.00
0.50
9.00
9.00
0.45
0.60
0.75
1.00
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A
A1
y
L
L1
Detail F
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Feature Integration Technology Inc.
Headquaters
Taipei Office
7F, No 31, Shintai Rd.,
Bldg. K4, 7F, No.700, Jungjeng Rd.,
Jubei City, Hsinchu 302, Taiwan, R.O.C.
Junghe City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-6562727
TEL : 866-2-8227-8027
FAX : 886-3-6560537
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
19
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
12 Application Circuit
VBS5V
VSB5V
VCC12V
VSB5V
1u
C1
470u
470u
1u
VCC12V VSB5V
C9 C10
C11
470u
470u
1u
DUAL3V
VCC3V
VRAM_OPS
C14
1u
470u*2
VCC12V
4.7k
10K
R11
R12 20k
R8
R9
Q6
MOSFET_EN_GDS
RSMRST#
VRAM
L2
Q9
MOSFET_EN_GDS
4.7u
D3
SCHOTTKY
VRAM_LGATE
C21
C22
1u
470u*2
VDUAL3V_SEN
VDUAL3V_DRV
VCCGATE
USBGATE
DUALGATE
PWOK
C18
R10 2.2
VRAM_UGATE
C13
1u
1u
3.9K
L1
TURBO#
FAULT#
VCC3V
VCC5V
R15
4.7k
R18
4.7k
R24
VRAM_FB
R25
R
R
R20
4.7k
R21
4.7k
VDUAL3V_SEN
VDUAL3V_DRV
VCCGATE
USBGATE
DUALGATE
GND
RSMRST#
PWOK
VCC3V
TURBO#
FAULT#
PWOKIN
R22
VSB5V
PSON_IN#
C25 10n
4.7k
MOSFET_EN_GDS
Q3
DUALGATE
Q4
DUAL5V
C7
C8
220u
220u
USB
24
23
22
21
20
19
18
17
16
15
14
13
VLDT_SEN
SS
VTT_OPS
GND
VRAM_UGATE
VRAM_LGATE
VCC_PWM
VRAM_OPS
VRAM_FB
COMP
VTT_FB
VTT_PWM
F72569
DUAL5V
R28
330
D4
R29
330
D5
VLDT_SEN
C12 0.1u
VTT_OPS
VRAM_OPS
VRAM_FB
COMP
VTT_FB
VTT_PWM
R23
C27
1u
1u
Vsb/Vcc/Vdual
VDDA_DRV
VLDT_DRV
R4
6.8k
C17
C19
470p
1u
VDDA_SEN
R5
2.2
R13
R
C15
220u
R6
6.8k
Q7
MOSFET_EN_GDS
C20
470p
VDDA
R14
VLDT_SEN
C23
C16
R7
2.2
220u
Q8
MOSFET_EN_GDS
R
VLDT
R17
R
220u
C24
220u
2.2
VSB5V
VCC3V
C26
Vsb/Vcc/Vdual
VRAM_UGATE
VRAM_LGATE
R16
R
R26
4.7k
VDDA
VLDT
R27
4.7k
VCC5V
VCORE_GD
VCORE_EN
VSB5V
Vsb/Vcc/Vdual
Vsb/Vcc/Vdual
LR1_DRV
VCC5V
C33 0.1u
L3
1
2
3
4
UGATE
BOOT
PWM
GND
PHASE
PVCC
VCC
LGATE
HIP6601
VTT_OPS
C32
1u
1u
470u*2
R34 2.2
Q12
MOSFET_EN_GDS
220u
VDUAL3V_DRV
L4
4.7u
C39
D6
SCHOTTKY 1u
C40
470u*2
R41
VTT_FB
1u
C44 1.2n
R43 10
Q13
MOSFET_EN_GDS
VDUAL3A_SEN
C34
470p
LR1_SEN
R31
2.2
R35
R
C28
220u
R32
6.8k
Q10
MOSFET_EN_GDS
C35
470p
LR1
C29
R33
2.2
R36
LR2_SEN
R
220u
Q11
MOSFET_EN_GDS
LR2
VCCGATE
R37
R
Q14
MOSFET_EN_GDS
DUAL3V
C37
R38
R
220u
LR1
C38
220u
LR2
C41
R
DUAL3V
R42
R
VCC3V
C36
20k
C42
COMP
VSB5V
VTT
Q15
MOSFET_EN_GDS
R39 2.2
LR2_DRV
R30
6.8k
C31
8
7
6
5
R40
1u
VCC12V
C30
U3
VTT_PWM
Q5
USB
1u
PS_ON#
S5#
SCLK
SDATA
VRAM
37
38
39
40
41
42
43
44
45
46
47
48
PWROK
VCC3V
R19 2.2
1u
PS_ONIN#
PS_ONOUT#
S5#
SCLK
SDATA
PLED
SLED
GND
VREF
VCORE_EN
VCORE_GD
VSB5V
R3
4.7k
DUAL5V
VCCGATE
LR2_SEN
LR2_DRV
LR1_DRV
LR1_SEN
VSB5V
C1
GND
C2
CP
VDDA_SEN
VDDA_DRV
VLDT_DRV
U2
ATX power connector
VCCGATE
Q2
MOSFET_EN_GDS
C4
C5
PWROK
ATX
D2
C3
VDDA_SEN
VDDA_DRV
VLDT_DRV
C6
C2
1
2
3
4
5
6
7
8
9
10
LR2_SEN
LR2_DRV
LR1_DRV
LR1_SEN
PS_ON#
3.3V
3.3V
COM
5V
COM
5V
COM
PWR_OK
5VSB
12V
VSB5V VCC5V
36
35
34
33
32
31
30
29
28
27
26
25
PS_ON
3.3V
-12V
COM
PS_ON
COM
COM
COM
-5V
5V
5V
1
2
3
4
5
6
7
8
9
10
11
12
11
12
13
14
15
16
17
18
19
20
MOSFET_EN_GDS
Q1
USBGATE
D1
U1
R2
4.7k
VCC5V
R1
2.2
VCC3V VCC5V
1000u
C43 47n
Title
R44 10.7k C45 47n
ACPI controller for AMD
VTT
Size
Document Number
Custom
Rev
0.4
F72569
Date:
20
2006 V0.26P
Friday , September 15, 2006
Sheet
1
of
1