C2901 4-bit Microprocessor Slice Megafunction General Description The C2901 four-bit microprocessor slice megafunction is a cascadable ALU intended for use in CPUs, peripheral controllers, and programmable microprocessors. The megafunction includes a dual port RAM, ALU, shifter, register and multiplexer. The microinstructions of the C2901 allow for easy modeling of various microcontrollers. Features • Independent and simultaneous access to two registers save machine cycles • Eight function ALU • Expandable – Any number of devices can be connected for wider bus structures • Four status flags for Carry, Overflow, Zero and Negative • Microprogrammable • The C2901 was developed in HDL and synthesizes to approximately 1,300 gates depending on the technology used. • Functionality based on the Advanced Micro Devices AM2901 Symbol Y[3:0] CN4 GN I[8:0] PN A[3:0] OVR B[3:0] F0 D[3:0] FEQ3 CP RAM0OUT CN RAM3OUT RAM0IN Q0OUT RAM3IN Q3OUT Q0IN RAM0EN Q3IN RAM3EN Q0EN Q3EN C2901 FEQEN CAST, Inc. March 2004 Page 1 CAST C2901 Megafuction Datasheet Pin Description Name CP I[8:0] D[3:0] A[3:0] B[3:0] CN Q0IN RAM0IN Q3IN RAM3IN Y[3:0] GN PN OVR F0 F3 CNP4 Q0OUT RAM0OUT Q3OUT RAM3OUT FEQEN Q0EN Q3EN RAM0EN RAM3EN Type Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Description Clock Instruction/Microcode Data Input A-port Address B-port Address Carry In Shift Line – Q Register Shift Line – RAM Stack Shift Line – Q Register Shift Line – RAM Stack Data Output Carry Generate Carry Propagate Overflow ALU outputs are zero ALU MSB Carry out Shift Line – Q Register Shift Line – RAM Stack Shift Line – Q Register Shift Line – RAM Stack ALU outputs are zero (control for Open Collector Output) Enable for Q0 Tristate Output Enable for Q3 Tristate Output Enable for RAM0 Tristate Output Enable for RAM3 Tristate Output Functional Description This section describes the Block Diagram below. A description of each of the blocks in the diagram is given here. Dual Port RAM The internal memory is a 4 bit by 16 Dual Port RAM. It is addressed for writing by the B Port and for reading by both the A and B Ports. The input data is defined by a microinstruction decoded from 3 bits of the 9-bit I Port. RAM Latch These latches store the outputs of the Dual Port RAM. They are clocked using the CP input. Q Register This section describes the internal register. It is selected using the Instruction input (I) and clocked with the CP input. CAST, Inc. Page 2 CAST C2901 Megafunction Datasheet Block Diagram RAM3IN RAM0IN RAMSEL QSEL MUX3 MUX3 QDIN RAMDATAIN RAMEN A[3:0] B[3:0] CP Dual Port RAM CP RAM LATCH Q Register QREG DPRAM_16_4 ARAMOUT Q3IN Q0IN Q QEN RAMEN BRAMOUT OSEL RAM LATCH ODECODE BRAMDATALATCH ARAMDATALATCH e n g e n I[5:3] CN D[3:0] FEQEN R S I[8:6] QSEL RAMSEL Q0EN Q3EN RAM0EN RAM3EN GN PN CN4 OVR ALU F D OSEL YOUT[3:0] Q ARAMDATALATCH BRAMDATALATCH R RSDECODE I[2:0] S MicroInstructions The I Port is internally decoded to define the flow of data to the above sections. ALU The ALU accepts input from either RAM Port, the Q Register and cascaded inputs from previous stages. It has basic functions including most logic and arithmetic operations including such functions as shifting, adding and subtracting. ODecode The ODecode block takes bits 6 – 8 of the MicroInstruction Bus and uses them to control the internal output enables and selects of the other blocks. CAST, Inc. Page 3 CAST C2901 Megafunction Datasheet RSDecode The RSDecode block takes bits 0 – 2 of the MicroInstruction Bus and uses them to control the 4bit R and S buses. These buses get loaded with the outputs of the other blocks, routing various results back through the ALU block ENGEN This block takes the select bits for the ram and q register and decodes the enable pins for the bidirectional RAM and Q bits. MicroInstructions The I Port is internally decoded to define the flow of data to the above sections. Device Utilization & Performance Supported Family Cyclone Stratix Stratix-II Device Tested EP1C20-6 EP1S20-5 EP2S60-3 LEs 273 273 206 Utilization Memory Memory bits 0 0 0 0 0 0 Performance Fmax 28 MHz 30 MHz 41 MHz Deliverables Encrypted Netlist License HDL Source License • Post synthesis EDIF netlist • VHDL or Verilog RTL source code • Assignment & Configuration • Testbenches • Symbol & Include files • Vectors for testing functionality • Testbench • Expected results • Vectors for testing the functionality of the megafunction • Synthesis scripts • Place & Route Scripts • Simulation scripts • Documentation • Documentation Contact Information CAST, Inc. 11 Stonewall Court Woodcliff Lake, New Jersey 07677 USA Phone: +1 201-391-8300 Fax: +1 201-391-8694 E-Mail: [email protected] URL: www.cast-inc.com Copyright © CAST, Inc. 2004, All Rights Reserved. Contents subject to change without notice. CAST, Inc. Page 4