TI SN65HVD75

SN65HVD72
SN65HVD75
SN65HVD78
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
3.3V-Supply RS-485 with IEC ESD Protection
Check for Samples: SN65HVD72, SN65HVD75, SN65HVD78
FEATURES
APPLICATIONS
•
•
•
•
1
•
•
•
•
•
•
•
Small-size MSOP Packages Save Board Space,
or SOIC for Drop-in Compatibility
Bus I/O Protection
– > ±15kV HBM protection
– > ±12kV IEC61000-4-2 Contact Discharge
– > ±12kV IEC61000-4-2 Air-Gap Discharge
Extended Industrial Temperature Range
–40°C to 125°C
Large Receiver Hysteresis (80 mV) for Noise
Rejection
Low Unit-loading allows over 200 connected
nodes
Low Power Consumption
– Low Standby Supply Current: < 2 µA
– ICC <1 mA Quiescent During Operation
5V-Tolerant Logic Inputs Compatible With
3.3 V or 5 V Controllers
Signaling Rate Options Optimized for:
250 kbps, 20 Mbps, 50 Mbps
Factory Automation
Telecomm Infrastructure
Motion Control
DESCRIPTION
These devices have robust 3.3V drivers and receivers
in a small package for demanding industrial
applications. The bus pins are robust to ESD events,
with high levels of protection to Human-Body Model
and IEC Contact Discharge specifications.
These devices each combine a differential driver and
a differential receiver, which operate from a single
3.3-V power supply. The driver differential outputs
and the receiver differential inputs are connected
internally to form a bus port suitable for half-duplex
(two-wire bus) communication. These devices all
feature a wide common-mode voltage range making
the devices suitable for multi-point applications over
long cable runs. These devices are characterized
from -40°C to 125°C.
Table 1. Product Selection Guide
Part Number
Signaling Rate
Cable Length
Duplex
Enables
Package
Nodes
256
SN65HVD72
up to 250 kbps
up to 2000 m
Half
DE, RE
MSOP-8
SOIC-8
SON-8
SN65HVD75
up to 20 Mbps
up to 100 m
Half
DE, RE
MSOP-8
SOIC-8
SON-8
256
SN65HVD78
up to 50 Mbps
up to 50 m
Half
DE, RE
MSOP-8
SOIC-8
SON-8
96
SN65HVD72, 75, 78
Logic Diagram (Positive Logic)
R
1
8
VCC
RE
2
7
B
RE
DE
3
6
A
DE
D
4
5
GND
R
D
1
2
3
6 A
7
B
4
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
SN65HVD72
SN65HVD75
SN65HVD78
SLLSE11B – MARCH 2012 – REVISED JUNE 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 2. DRIVER FUNCTION TABLE
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
Actively drive bus High
L
H
L
H
Actively drive bus Low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus High by default
B
Table 3. RECEIVER FUNCTION TABLE
2
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus High
VIT– < VID < VIT+
L
?
Indeterminate bus state
VID < VIT–
L
L
Receive valid bus Low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
fail-safe high output
Idle (terminated) bus
L
H
fail-safe high output
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
MIN
UNIT
MAX
Supply Voltage, VCC
–0.5
5.5
V
Voltage range at A or B Inputs
–13
16.5
V
V
Input voltage range at any logic pin
–0.3
5.7
Voltage input range, transient pulse, A and B, through 100Ω
–100
100
V
Receiver Output Current
–24
24
mA
170
°C
150
°C
Junction Temperature, TJ
Storage Temperature,
-65
Continuous total power dissipation
See the Thermal Characteristics table
IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND
±12
kV
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
±12
kV
IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND
±4
kV
IEC 60749-26 ESD (Human Body Model), bus terminals and GND
±15
kV
JEDEC Standard 22, Test Method A114 (Human Body Model), all pins
±8
kV
JEDEC Standard 22, Test Method C101 (Charged Device Model), all pins
±1.5
kV
JEDEC Standard 22, Test Method A115 (Machine Model), all pins
±300
V
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
VI
Input voltage at any bus terminal (separately or common mode)
VIH
VIL
VID
NOM MAX
V
–7
12
V
High-level input voltage (Driver, driver enable, and receiver enable inputs)
2
VCC
V
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
0
0.8
V
Differential input voltage
–12
12
V
IO
Output current, Driver
–60
60
mA
IO
Output current, Receiver
–8
8
mA
RL
Differential load resistance
54
CL
Differential load capacitance
1/tUI
TA
TJ
(1)
(2)
(2)
(1)
3.3
UNIT
3.6
Signaling rate
3
60
Ω
50
pF
HVD72
250
kbps
HVD75
20
Mbps
HVD78
50
Mbps
Operating free-air temperature (See the application section for thermal information)
–40
125
°C
Junction Temperature
–40
150
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
Copyright © 2012, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
RL = 60 Ω, 375 Ω on each output to
-7 V to 12 V
|VOD|
Driver differential output voltage
magnitude
See
Figure 1
RL = 54 Ω (RS-485)
MIN
TYP
1.5
2
V
1.5
2
V
2
2.5
V
–50
0
50
mV
1
VCC/2
3
V
–50
0
50
mV
RL = 100 Ω (RS-422) TJ ≥ 0°C,
VCC ≥ 3.2V
Δ|VOD|
Change in magnitude of driver
differential output voltage
RL = 54 Ω, CL = 50 pF
See
Figure 2
VOC(SS)
Steady-state common-mode output
voltage
ΔVOC
Change in differential driver output
common-mode voltage
VOC(PP)
Peak-to-peak driver common-mode
output voltage
COD
Differential output capacitance
VIT+
Positive-going receiver differential
input voltage threshold
VIT–
Negative-going receiver differential
input voltage threshold
VHYS
Receiver differential input voltage
threshold hysteresis (VIT+ – VIT–)
VOH
Receiver high-level output voltage
IOH = –8 mA
VOL
Receiver low-level output voltage
IOL = 8 mA
II
Driver input, driver enable, and
receiver enable input current
IOZ
Receiver output high-impedance
current
IOS
Driver short-circuit output current
Center of two 27-Ω load resistors
Bus input current (disabled driver)
VCC = 3 to 3.6 V or
VCC = 0 V, DE at 0 V
HVD78
ICC
Supply current (quiescent)
Supply current (dynamic)
(1)
4
15
pF
–70
–200
–150
50
80
2.4
VCC–0.3
(1)
mV
See
mV
V
–2
2
µA
–1
1
µA
160
mA
150
µA
75
–100
–40
–267
–180
VI = 12 V
240
VI = –7 V
mV
V
VI = 12 V
VI = –7 V
–20
0.4
–160
HVD72, 75
II
mV
0.2
VO = 0 V or VCC, RE at VCC
UNIT
200
(1)
See
MAX
µA
333
µA
µA
Driver and Receiver
enabled
DE=VCC, RE=GND, No
load
750
950
µA
Driver enabled,
receiver disabled
DE=VCC, RE=VCC, No
load
300
500
µA
Driver disabled,
receiver enabled
DE=GND, RE=GND, No
load
600
800
µA
Driver and receiver
disabled
DE=GND, D=open
RE=VCC, No load
0.1
2
µA
See the TYPICAL CHARACTERISTICS section
Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT-.
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
SWITCHING CHARACTERISTICS
250 kbps devices (HVD70, 71, 72) bit time > 4 µs (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.3
0.7
1.2
µs
0.7
1
µs
DRIVER
tr, tf
Driver differential output rise/fall
time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF
Receiver enabled
Driver enable time
See Figure 3
See Figure 4 and
Figure 5
Receiver disabled
0.2
µs
0.1
0.4
µs
0.5
1
µs
3
9
µs
12
30
ns
75
100
ns
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
CL = 15 pF
See Figure 6
3
15
ns
40
100
ns
Driver enabled
See Figure 7
20
50
ns
Driver disabled
See Figure 8
3
8
µs
SWITCHING CHARACTERISTICS
20 Mbps devices (HVD73, 74, 75) bit time > 50 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DRIVER
tr, tf
Driver differential output rise/fall
time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF
Receiver enabled
Driver enable time
See Figure 3
See Figure 4 and
Figure 5
Receiver disabled
2
7
14
ns
7
11
17
ns
0
2
ns
12
50
ns
10
20
ns
3
7
µs
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
Copyright © 2012, Texas Instruments Incorporated
CL = 15 pF
See Figure 6
5
10
ns
60
70
ns
0
6
ns
ns
15
30
Driver enabled
See Figure 7
10
50
ns
Driver disabled
See Figure 8
3
8
µs
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SWITCHING CHARACTERISTICS
50 Mbps devices (HVD76, 77, 78) bit time > 20 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DRIVER
tr, tf
Driver differential output rise/fall
time
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
1
RL = 54 Ω, CL = 50 pF
Receiver enabled
Driver enable time
See Figure 3
See Figure 4 and
Figure 5
3
6
ns
9
15
ns
0
1
ns
10
30
ns
10
30
ns
8
µs
Receiver disabled
RECEIVER
tr, tf
Receiver output rise/fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
1
CL = 15 pF
Receiver enable time
3
See Figure 6
6
ns
35
ns
2.5
ns
8
30
ns
Driver enabled
See Figure 7
10
30
ns
Driver disabled
See Figure 8
3
8
µs
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
375 W ±1%
VCC
DE
0 V or 3 V
D
A
VOD
60 W ±1%
B
+
_
–7 V < V(test) < 12 V
375 W ±1%
S0301-01
Figure 1. Measurement of Driver Differential Output Voltage with Common-Mode Load
0 V or 3 V
VA
B
VB
RL/2
A
D
A
VOD
VOC(PP)
B
RL/2
CL
DVOC(SS)
VOC
VOC
S0302-01
Figure 2. Measurement of Driver Differential and Common-Mode output with RS-485 Load
6
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PARAMETER MEASUREMENT INFORMATION (continued)
50%
50%
A
»
W
B
W
»
Figure 3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
D
3V
50 W
VI
VO
VI
B
CL = 50 pF ±20%
DE
Input
Generator
3V
S1
50%
RL = 110 W
± 1%
CL Includes Fixture
and Instrumentation
Capacitance
50%
0V
0.5 V
tPZH
VOH
90%
VO
50%
»0V
tPHZ
S0304-01
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 4. Measurement of Driver Enable and Disable Times with Active High Output and Pull-Down Load
3V
A
D
3V
S1
VO
»3V
VI
50%
50%
0V
B
DE
Input
Generator
RL = 110 W
±1%
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
S0305-01
D at 0V to test non-inverting output, D at 3V to test inverting output.
Figure 5. Measurement of Driver Enable and Disable Times with Active Low Output and Pull-Up Load
3V
A
Input
Generator
R
VI
50 W
1.5 V
0V
VI
VO
50%
50%
0V
B
RE
tPLH
CL = 15 pF ±20%
VO
CL Includes Fixture
and Instrumentation
Capacitance
tPHL
90% 90%
50%
10%
50%
10%
tr
VOH
VOL
tf
S0306-01
Figure 6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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PARAMETER MEASUREMENT INFORMATION (continued)
3V
VCC
DE
A
0 V or 3 V D
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at 3 V
S1 to GND
»0V
tPZL(1)
tPLZ
VCC
VO
50%
D at 0 V
S1 to VCC
10%
VOL
S0307-01
Figure 7. Measurement of Receiver Enable/Disable Times with Driver Enabled
8
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VCC
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VCC
S0308-01
Figure 8. Measurement of Receiver Enable Times with Driver Disabled
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TYPICAL CHARACTERISTICS
DRIVER OUTPUT VOLTAGE
vs
DRIVER OUTPUT CURRENT
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DRIVER OUTPUT CURRENT
3.5
VCC = 3.3 V,
DE = VCC,
D=0V
VOH
3
VO - Driver Differential Output Voltage - V
VO - Driver Output Voltage - V
3.5
2.5
2
1.5
VOL
1
0.5
0
0
20
40
60
80
IO - Driver Output Current - mA
2
1.5
1
0.5
0
20
40
60
80
IO - Driver Output Current - mA
Figure 9.
Figure 10.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
'HVD78
DRIVER RISE and FALL TIME
vs
TEMPERATURE
100
4
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
30
3.5
Driver Rise and Fall Time - ns
35
25
20
15
10
5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
VCC Supply Voltage - V
3
3.5
0
-40
-20
0
20
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40
60
80
100
120
o
Temperature - C
Figure 11.
10
VCC = 3.3 V,
DE = VCC,
D=0V
60 W
2.5
0
100
40
IO - Driver Output Current - mA
100 W
3
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
'HVD78
DRIVER PROPAGATION DELAY
vs
TEMPERATURE
'HVD72
SUPPLY CURRENT
vs
SIGNAL RATE
70
12
60
50
Icc - Supply Current - mA
Driver Propagation Delay - ns
10
8
6
4
2
40
30
20
10
0
-40
-20
0
20
40
60
80
100
0
50
120
70
90
o
130
150
170
190
210
230
250
40
45
50
Signaling Rate - kbps
Figure 13.
Figure 14.
'HVD75
SUPPLY CURRENT
vs
SIGNAL RATE
'HVD78
SUPPLY CURRENT
vs
SIGNAL RATE
70
70
60
60
50
50
Icc - Supply Current - mA
Icc - Supply Current - mA
Temperature - C
110
40
30
20
10
40
30
20
10
0
0
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
35
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Receiver Output
vs
Input
3.5
Receiver Output (R) V
3
2.5
VIT- (-7V)
2
VIT-(0V)
VIT-(12V)
1.5
VIT+(-7V)
VIT+(0V)
1
VIT+(12V)
0.5
0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
Differential Input Voltage (VID) mV
Figure 17.
SPACER
DEVICE INFORMATION
Table 4. Thermal Information
PARAMETER
D
SOIC-8
DGK
MSOP-8
DRB
SON-8
Units
°C/ W
ΘJA
Junction-to-Ambient Thermal Resistance
110.7
168.7
40.0
ΘJB
Junction-to-Board Thermal Resistance
51.3
89.5
15.5
ΘJC(top)
Junction-to-Case(top) Thermal Resistance
54.7
62.2
49.6
ΘJC(top)
Junction-to-Case(top) Thermal Resistance
n/a
n/a
3.9
ΨJT
Junction-to-Top thermal parameter
9.2
7.4
0.6
ΨJB
Junction-to-Board thermal parameter
50.7
87.9
15.7
TTSD
Thermal Shut-down junction temperature
170
°C
Table 5. Power Dissipation
PARAMETER
TEST CONDITIONS
Unterminated
PD
12
Power Dissipation
driver and receiver enabled,
VCC = 3.6 V, TJ = 150°C
50% duty cycle square-wave signal at
RS-422 load
signaling rate:
•
HVD72 at 250 kbps
•
HVD75 at 20 Mbps
•
HVD78 at 50 Mbps
RS-485 load
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RL = 300 Ω,
CL = 50 pF (driver)
RL = 100 Ω,
CL = 50 pF (driver)
RL = 54 Ω,
CL = 50 pF (driver),
VALUE
HVD72
120
HVD75
160
HVD78
200
HVD72
155
HVD75
195
HVD78
230
HVD72
190
HVD75
230
HVD78
260
UNITS
mW
mW
mW
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD72 SN65HVD75 SN65HVD78
SN65HVD72
SN65HVD75
SN65HVD78
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a High when the differential input VID is more positive than +200 mV, and must output a Low
when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance
are VIT+ and VIT-and VHYS. As seen in the Electrical Characteristics table, differential signals more negative than 200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will
always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
will be High. Only when the differential input is more negative than VIT-will the receiver output transition to a Low
state. So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT-) as well as the value of VIT+.
Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring
no spurious bits.
Low-Power Standby Mode
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode.
This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs
are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode.
In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less
than 100 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
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APPLICATION INFORMATION
Device Configuration
The SN65HVD72, 'HVD75 and 'HVD78 are half-duplex RS-485 transceivers operating from a single 3.3V ±10%
supply. The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
a) Independent driver and
receiver enable signals
D
D
b) Combined enable signals for
use as directional control pin
D
c) Receiver always on
Figure 18. Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening to
the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device
operates as a receiver.
Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only.
In this configuration a node not only receives the data from the bus but also the data it sends and thus can verify
that the correct data have been transmitted.
Bus – Design
An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over
long cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Figure 19. Typical RS-485 network with SN65HVD7x Transceivers
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and
RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
14
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
Noise Immunity
The input sensitivity of a standard RS-485 transceiver is ± 200 mV. When the differential input voltage, VID, is
greater than + 200 mV, the receiver output turns high, for VID < –200 mV the receiver outputs low.
R
VHYS-min
50mV
-70
-20
70
0
VID - mV
Vnoise-max = 140mVpp
Figure 20. SN65HVD7x Noise Immunity
The SN65HVD7x transceiver family implements high receiver noise-immunity by providing a maximum positivegoing input threshold of - 20 mV and a minimum hysteresis of 50 mV. In the case of a noisy input condition
therefore, a differential noise voltage of up to 140 mVPP can be present without causing the receiver output to
change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias
resistors and allows for long haul data transmissions in noisy environments.
Transient Protection
High-Voltage
Pulse
Generator
RC
RD
50M
(1M)
330Ω
(1.5k)
CS
150pF
(100pF)
Device
Under
Test
Current - A
The bus terminals of the SN65HVD7x transceiver family possess on-chip ESD protection against ±15 kV human
body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the
HBM-ESD test. The 50 % higher charge capacitance, CS, and 78 % lower discharge resistance, RD of the IECmodel produce significantly higher discharge currents than the HBM-model.
40
35
30
25
20
15
10
5
0
10kV IEC
10kV HBM
0
50
100
150
200
250
300
Time - ns
Figure 21. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The implementation of IEC-ESD protection on-chip increases the robustness of equipment significantly, which
most likely experience discharge events due to human contact with connectors and cables. Designers may also
want to implement protection against much longer duration transients, typically referred to as surge transients.
Figure 9 therefore suggests two circuit designs providing protection against light and heavy surge transients, in
addition to ESD and EFT transients. Table A1 presents the associated bill of material.
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
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Table 6. Bill of Materials
Device
Function
Order Number
Manufacturer
XCVR
3.3V, 250kbps RS-485 Transceiver
SN65HVD72D
R1, R2
10Ω, Pulse-Proof Thick-Film Resistor
CRCW0603010RJNEAHP
Vishay
TVS
Bidirectional 400W Transient Suppressor
CDSOT23-SM712
Bourns
TBU1, TBU2
Bidirectional.
TBU-CA-065-200-WH
Bourns
MOV1, MOV2
200mA Transient Blocking Unit 200V, MetalOxide Varistor
MOV-10D201K
Bourns
Vcc
Vcc
Vcc
10k
1
R
2
RE
DIR
3
DE
TxD
4
D
RxD
MCU
TI
Vcc
8
A
7
B
6
GND
5
XCVR
0.1μF
Vcc
10k
R1
1
R
2
RE
DIR
3
DE
TxD
4
D
RxD
TVS
MCU
Vcc
8
A
7
B
6
GND
5
XCVR
0.1μF
TBU1
MOV1
TVS
MOV2
R2
10k
R1
R2
10k
TBU2
Figure 22. Transient Protections Against ESD, EFT, and Surge Transients
The left circuit provides surge protection of ≥ 500 V transients, while the right protection circuits can withstand
surge transients of 5 kV.
Design and Layout Considerations For Transient Protection
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
In order for your PCB design to be successful start with the design of the protection circuit in mind.
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
4. Apply 100 nF to 220 nF bypass capacitors as close as possible to the Vcc-pins of transceiver, UART,
controller ICs on the board.
5. Use at least two vias for Vcc and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1k to 10k pull-up/down resistors for enable lines to limit noise currents in theses lines during transient
events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to some 200 mA.
16
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SLLSE11B – MARCH 2012 – REVISED JUNE 2012
Isolated Bus Node Design
Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their
disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to
the bus transceiver via a multi-channel, digital isolator (Figure 23).
0.1μF
2
Vcc D2 3
1:1.33 MBR0520L
SN6501
GND D1
N
3
1
10μF
IN
OUT
1
3.3VISO
TLV70733
10μF 0.1μF
4,5
L1
4
EN
GND
2
10μF
MBR0520L
ISO-BARRIER
3.3V
0.1μF
PSU
0.1μF
PE
0.1μF
4.7k
PE
2
DVcc
5
6
XOUT
XIN
UCA0RXD
P3.0
MSP430
F2132
DVss
P3.1
UCA0TXD
4
16
11
12
15
1
16
Vcc1
Vcc2
7
10
EN1 ISO7241 EN2
6
11
OUTD
IND
3
14
INA
OUTA
4
13
INB
OUTB
5
12
INC
OUTC
GND1
GND2
2,8
0.1μF
4.7k
1
R
8
Vcc
7
B
RE SN65
3
DE HVD72 6
A
4
D GND2
2
5
R1
R2
TVS
9,15
R HV
Short thick Earth wire or Chassis
Protective Earth Ground,
Equipment Safety Ground
Floating RS-485 Common
C HV
PE
island
R1,R2, TVS: see Table 1
RHV = 1MΩ, 2kV high-voltage resistor, TT electronics, HVC 2010 1M0 G T3
CHV = 4.7nF, 2kV high-voltage capacitor, NOVACAP, 1812 B 472 K 202 N T
Figure 23. Isolated Bus Node With Transient Protection
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.
Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are
pulled-up via 4.7k resistors to limit their input currents during transient events.
While the transient protection is similar to the one in Figure 22(left circuit), an additional high-voltage capacitor is
used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground.
This is necessary as noise transients on the bus are usually referred to Earth potential.
RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if it is expected that fast
transients might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
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REVISION HISTORY
Changes from Original (March 2012) to Revision A
Page
•
Changed the Switching Characteristics condition statement From: 15 kbps devices (HVD73, 74, 75) bit time > 65 ns
To: 20 Mbps devices (HVD73, 74, 75) bit time > 50 ns ....................................................................................................... 5
•
Changed the Switching Characteristics condition statement From: 50 kbps devices (HVD76, 77, 78) bit time > 20 ns
To: 50 Mbps devices (HVD76, 77, 78) bit time > 20 ns ....................................................................................................... 6
•
Added Figure 12 to TYPICAL CHARACTERISTICS. ......................................................................................................... 10
•
Added Figure 13 to TYPICAL CHARACTERISTICS. ......................................................................................................... 11
•
Added Figure 14 to TYPICAL CHARACTERISTICS. ......................................................................................................... 11
•
Added Figure 15 to TYPICAL CHARACTERISTICS. ......................................................................................................... 11
•
Added Figure 16 to TYPICAL CHARACTERISTICS. ......................................................................................................... 11
•
Added Figure 17 to TYPICAL CHARACTERISTICS. ......................................................................................................... 12
•
Added VALUEs to the Thermal Characteristics table in the DEVICE INFORMATION section. ......................................... 12
•
Added APPLICATION INFORMATION section to data sheet. ........................................................................................... 14
Changes from Original (May 2012) to Revision B
Page
•
Added the SON-8 package and Nodes column to Table 1, ................................................................................................. 1
•
Changed the SN65HVD72, 75, 78 Logic Diagram ............................................................................................................... 1
•
Changed the Voltage range at A or B Inputs MIN value From: –8 V To: –13 V .................................................................. 3
•
Added foot note for free-air temperature to the RECOMMENDED OPERATING CONDITIONS table ............................... 3
•
Changed the Bus input current (disabled driver) TYP values for HVD78 VI = 12 V From: 150 To: 240 and VI = –7 V
From: –120 To: –180 ............................................................................................................................................................ 4
•
Added TYP values to the SWITCHING CHARACTERISTICS table .................................................................................... 5
•
Added TYP values to the SWITCHING CHARACTERISTICS table .................................................................................... 6
•
Changed Table 4, Thermal Information .............................................................................................................................. 12
•
Changed Table 5, Thermal Characteristics ........................................................................................................................ 12
•
Added section: LOW-POWER STANDBY MODE .............................................................................................................. 13
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
SN65HVD72D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
SN65HVD72DGK
ACTIVE
VSSOP
DGK
8
80
SN65HVD72DGKR
ACTIVE
VSSOP
DGK
8
SN65HVD72DR
ACTIVE
SOIC
D
SN65HVD72DRBR
ACTIVE
SON
SN65HVD72DRBT
ACTIVE
SN65HVD75D
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
(4)
Level-1-260C-UNLIM
-40 to 125
HVD72
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD72
2500
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD72
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HVD72
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD72
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD72
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HVD75
SN65HVD75DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD75
SN65HVD75DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD75
SN65HVD75DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HVD75
SN65HVD75DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD75
SN65HVD75DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD75
SN65HVD78D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HVD78
SN65HVD78DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD78
SN65HVD78DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
HVD78
SN65HVD78DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HVD78
SN65HVD78DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HVD78
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-Apr-2013
Status
(1)
SN65HVD78DRBT
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SON
DRB
8
250
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-2-260C-1 YEAR
(4)
-40 to 125
HVD78
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN65HVD72DGKR
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD72DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD72DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD72DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD75DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD75DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD75DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD75DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD78DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
SN65HVD78DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD78DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
SN65HVD78DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD72DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
SN65HVD72DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD72DRBR
SON
DRB
8
3000
367.0
367.0
35.0
SN65HVD72DRBT
SON
DRB
8
250
210.0
185.0
35.0
SN65HVD75DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
SN65HVD75DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD75DRBR
SON
DRB
8
3000
367.0
367.0
35.0
SN65HVD75DRBT
SON
DRB
8
250
210.0
185.0
35.0
SN65HVD78DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
SN65HVD78DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD78DRBR
SON
DRB
8
3000
367.0
367.0
35.0
SN65HVD78DRBT
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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