HOLTEK HT82D40REW

HT82D40REW
2.4GHz Transceiver USB Interface 8-Bit OTP MCU
Features
· Operating voltage:
· RF Transceiver with 2.4GHz RF frequency
fSYS=6M/12MHz: 3.3V~5.5V
· Integrated 1.5kW resistor between V33O and
· 4096´15 program memory
D- pins for USB applications
· 160´8 data memory RAM
· Fully integrated 6MHz or 12MHz oscillator
· 128´8 EEPROM data memory
· All I/O pins have wake-up functions
· USB 2.0 low speed function
· Power-down function and wake-up feature reduce
power consumption
· 3 endpoints supported - endpoint 0 included
· 8-level subroutine nesting
· PS2 and USB modes supported
· Up to 0.33ms instruction cycle with 12MHz system
· Low voltage reset function
clock at VDD=5V
· 9 bidirectional I/O lines (max.)
· Bit manipulation instruction
· 8-bit programmable timer/event counter with
· 15-bit table read instruction
overflow interrupt
· 63 powerful instructions
· 16-bit programmable timer/event counter and
· All instructions in one or two machine cycles
overflow interrupts
· 40-pin QFN package
· Watchdog Timer
General Description
The HT82D40REW is 8-bit high performance, RISC architecture microcontroller device specifically designed
for multiple I/O control product applications.
Down and wake-up functions, Watchdog timer etc,
make the devices extremely suitable for use in computer peripheral product applications as well as many
other applications such as industrial control, consumer
products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, timer functions, integrated USB interface, Power
Rev. 1.00
1
April 1, 2010
HT82D40REW
Block Diagram
W a tc h d o g
T im e r
8 - b it
R IS C
M C U
C o re
O T P P ro g ra m
M e m o ry
D a ta
M e m o ry
L o w
V o lta g e
R e s e t
S ta c k
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
In te rn a l R C
O s c illa to r
U S B
E E P R O M
D a ta
M e m o ry
I/O
P o rts
8 - b it/1 6 - b it
T im e r s
R F
T r a n s c e iv e r
S P I
In te rfa c e
V 3 3 O
Pin Assignment
V D D _ G R
& V D D _ B
V D D _
X T A L _
X T A L _
V D D _ P L
V D D _ C
V D D _ V C
L O O P _
D B
V D D _ R F
O
G
N
C
P
P
A
1
5
L
R F _ P
R F _ N
V D D _ R F 2
N C
V D D P
S C L
S D A
V S S P
V D D
V 3 3 O
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
1
2
3 0
2 9
2 8
3
4
2 7
5
H T 8 2 D 4 0 R E W
4 0 Q F N -A
6
7
2 6
2 5
2 4
8
2 3
9
1 0
2 2
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
2 1
V D D
V D D
V D D
G P IO
G P IO
G N D
P G IO
P B 7
P A 0
P A 1
_ 3 V
_ 2 V 2
_ D
0
1
& G N D _ G R
2
& G N D _ P L L
P A 2
P A 3
P A 4
P A 5
P A 6 /T M R 0
P A 7 /T M R 1
R E S
V S S
P D P
P D N
Rev. 1.00
2
April 1, 2010
HT82D40REW
Pin Description
Pin Name
I/O
Options
Description
I/O
Bidirectional 8-bit input/output port. Each pin can be configured as
a wake-up input by a configuration option. Software instructions
Pull-high
determine if the pin is an output or Schmitt Trigger input. ConfiguWake-up
ration options determine if the output structures are CMOS, NMOS
NMOS/CMOS/PMOS or PMOS types. Each pin can be configured as an input with or
without a pull-high resistor by a configuration option. TMR0 and
TMR1 are pin-shared with PA6 and PA7, respectively.
PB0/INT
PB1/RST
PB2/WAKE
PB3/SDI
PB4/SDO
PB5/SCK
PB6/SCS
PB7
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each pin can be configured as
a wake-up input by a configuration option. Software instructions
determine if the pin is a CMOS output or Schmitt Trigger input.
Each pin can be configured as an input with or without a pull-high
resistor by a configuration option. PB3~PB6 are pin-shared with
the SPI interface pins named SDI, SDO, SCK and SCS respectively. These pins are not bonded out to the external pins and internally connected to the relevant RF Transceiver lines. PB0~PB2
are also not bonded out to the external pins and internally connected to the corresponding RF Transceiver lines named INT, RST
and WAKE.
PDP/CLK
I/O
¾
USB D+ line. USB function is controlled by software control register. PDP pin is also pin-shared with CLK for PS2.
PDN/DATA
I/O
¾
USB D- line. USB function is controlled by software control register. PDN pin is also pin-shared with DATA for PS2.
SCL
I
¾
Serial Clock Input for EEPROM memory
SDA
I/O
¾
Serial Data Input/Output for EEPROM memory
VDDP
¾
¾
Positive power supply for EEPROM memory (Note 1)
VSSP
¾
¾
Negative power supply for EEPROM memory, ground (Note 1)
VDD_RF2
¾
¾
RF transceiver power supply (Note 2)
RF_P
I/O
¾
Differential RF input/output (+)
RF_N
I/O
¾
Differential RF input/output (-)
VDD_RF1
¾
¾
RF transceiver power supply (Note 2)
GPIO0, GPIO1
I/O
¾
General Purpose digital I/O
It is also used as an external TX/RX switch control.
GPIO2
I/O
¾
General Purpose digital I/O
It is also used as an external Power Amplifier (P.A.) enable control.
VDD_D
¾
¾
RF transceiver digital circuit power supply (+)
PA0~PA5
PA6/TMR0
PA7/TMR1
GND & GND_GR
& GND_PLL
¾
¾
GND is the RF transceiver digital circuit power supply (-).
GND_GR is the RF transceiver Guard-Ring ground. GND_PLL is
the RF transceiver PLL negative power supply (-), ground. These
pins are internally bonded together.
VDD_2V2
O
¾
RF transceiver DC-DC output voltage
It can not be used.
VDD_3V
I
¾
RF transceiver 3V input for the DC-DC regulator
VDD_GR &
VDD_BG
¾
¾
VDD_GR is the RF transceiver Guard-Ring power supply (Note 2)
VDD_BG is the RF transceiver Band-gap power supply (Note 2)
VDD_A
¾
¾
RF transceiver power supply for analog circuit (Note 2)
VDD_PLL
¾
¾
RF transceiver positive power supply for PLL circuit (Note 2)
VDD_CP
¾
¾
RF transceiver Charge pump power supply (Note 2)
Rev. 1.00
3
April 1, 2010
HT82D40REW
Pin Name
I/O
Options
Description
¾
RF transceiver Voltage-Controlled Oscillator pump power supply
(Note 2)
VDD_VCO
LOOP_C
I/O
¾
RF transceiver PLL loop filter external capacitor
It should be connected to the external capacitor.
XTAL_P
I
¾
RF transceiver 32MHz Crystal input (+)
XTAL_N
I
¾
RF transceiver 32MHz Crystal input (-)
DB5
I
¾
Test pin. It should be connected to ground.
RES
I
¾
Schmitt trigger reset input. Active low
VSS
¾
¾
Digital negative power supply, ground
VDD
¾
¾
Digital positive power supply
V33O
O
¾
3.3V regulator output
Note:
(1) VDDP and VSSP should be externally connected to the MCU power supply named VDD and VSS respectively.
(2) Connecting bypass capacitor(s) as close to the pin as possible.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Operating Voltage
(Integrated oscillator)
¾
IDD
Operating Current
5V
Standby Current
(WDT Enabled)
Standby Current
(WDT Disabled)
5V
Standby Current
(WDT Enabled)
VIL
Input low voltage for I/O ports
5V
Input Low Voltage for RES pin
VIH
Input High Voltage for PA, PC
5V
Input High Voltage for RES pin
Rev. 1.00
Typ.
Max.
Unit
fSYS=6MHz or 12MHz
3.3
¾
5.5
V
No load, fSYS=6MHz
¾
6.5
12
mA
No load, fSYS=12MHz
¾
7.5
16
mA
NO load,
system USB suspend
¾
¾
250
mA
NO load,
system USB suspend
¾
¾
230
mA
No load, system HALT,
input/output mode,
set SUSPEND2 [1CH]
¾
¾
15
mA
0
¾
0.8
V
0
¾
0.4VDD
V
2
¾
5
V
0.9VDD
¾
VDD
V
Conditions
VDD
ISTB
Min.
VDD
¾
¾
4
April 1, 2010
HT82D40REW
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VLVR
Low voltage detecting voltage
5V
¾
2.0
2.6
3.2
V
VV33O
3.3V Regulator Output for USB SIE
5V
IV33O=70mA
3.0
3.3
3.6
V
IOL1
Output sink current for PA, PB7
5V
VOL=0.4V
2
¾
¾
mA
IOH1
Output source current for PA, PB7
5V
VOH=3.4V
-2
¾
¾
mA
IOL2
Output sink current for PB0~PB6
5V
VOL=0.4V
6
¾
¾
mA
IOH2
Output source current for PB0~PB6
5V
VOH=3.4V
-6
¾
¾
mA
RPH1
Pull-high resistor for CLK, DATA
¾
4.7
¾
kW
RPH2
Pull-high resistor for PA, PB7
25
50
80
kW
RPH3
Pull-high resistor for PB0~PB6
10
30
50
kW
¾
5V
EEPROM Memory D.C. Characteristics
Ta=-40°C~85°C
Test Conditions
Symbol
Parameter
VDDP
Conditions
¾
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
VCC
Operating Voltage
¾
ICC1*
Operating Current
5V
Read at 100kHz
¾
¾
2
mA
ICC2*
Operating Current
5V
Write at 100kHz
¾
¾
5
mA
ISTB1*
Standby Current
5V
VIN=0 or VDDP
¾
¾
4
mA
ISTB2*
Standby Current
2.4V VIN=0 or VDDP
¾
¾
3
mA
VIL
Input Low Voltage
¾
¾
-1
¾
0.3VDDP
V
VIH
Input High Voltage
¾
¾
0.7VDDP
¾
VDDP+0.5
V
VOL
Output Low Voltage
¾
¾
0.4
V
ILI
Input Leakage Current
5V
VIN=0 or VDDP
¾
¾
1
mA
ILO
Output Leakage Current
5V
VOUT=0 or VDDP
¾
¾
1
mA
Note:
2.4V IOL=2.1mA
*: The operating current ICC1 and ICC2 listed here are the additional currents consumed when the EEPROM
Memory operates in Read Operation and Write Operation respectively. If the EEPROM is operating, the ICC1 or
ICC2 should be added to calculate the relevant operating current of the device for different conditions. To calculate the standby current for the whole device, the standby current shown above should also be taken into account.
Rev. 1.00
5
April 1, 2010
HT82D40REW
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
fSYS
Parameter
System Clock
VDD
Conditions
5V
¾
Min.
Typ.
Max.
Unit
¾
6
¾
MHz
¾
12
¾
MHz
fRCSYS
RC Clock with 8-bit Prescaler Register
¾
¾
¾
32
¾
kHz
tconfigure
Watchdog Time-out Period
¾
¾
1024
¾
¾
1/fRCSYS
USBD+, USBD- Rising & Falling Time
¾
¾
75
¾
300
ns
Oscillation Start-up Timer Period
¾
¾
¾
1024
¾
1/fSYS
tOST
Note:
Power_on period = tconfigure + tOST
WDT Time_out in Normal Mode = 1/ fRCSYS ´ 256 ´ WDTS + tconfigure
WDT Time_out in Power Down Mode = 1/ fRCSYS ´ 256 ´ WDTS + tOST
EEPROM Memory A.C. Characteristics
Ta=-40°C~85°C
Standard Mode*
Symbol
Parameter
Remark
VDDP=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
SCL Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the
first clock pulse is
generated
4000
¾
600
¾
ns
tSU:STA
Only relevant for
START Condition Setup Time repeated START
condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
ns
tBUF
Bus Free Time
Time in which the bus
must be free before a new
transmission can start
4700
¾
1200
¾
ns
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
¾
100
¾
50
ns
tWR
Write Cycle Time
¾
¾
5
¾
5
ms
Note:
* The standard mode means VDDP=2.2V to 5.5V
For relative timing, refer to the timing diagrams in EEPROM Data Memory section.
Rev. 1.00
6
April 1, 2010
HT82D40REW
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
functions. In this way, one T1~T4 clock cycle forms one
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
Clocking and Pipelining
The system clock is derived from an internal oscillator
and is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.00
7
April 1, 2010
HT82D40REW
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register.
By transferring data directly into this register, a short program jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 locations. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted.
P ro g ra m
S ta c k L e v e l 1
T o p o f S ta c k
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
Mode
C o u n te r
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Program Counter Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
SPI Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
@3
@2
@1
@0
Skip
Program Counter + 2
Loading PCL
PC11 PC10 PC9
PC8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
#11~#0: Instruction code address bits
Rev. 1.00
@[email protected]: PCL bits
S11~S0: Stack register bits
8
April 1, 2010
HT82D40REW
0 0 0 H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
In itia lis a tio n
V e c to r
RLC
0 0 4 H
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
0 0 8 H
SIZA, SDZA, CALL, RET, RETI
0 0 C H
Program Memory
The Program Memory is the location where the user
code or program is stored. The HT82D40REW is a
One-Time Programmable, OTP, memory type device
where users can program their application code into the
device. By using the appropriate programming tools,
OTP devices offer users the flexibility to freely develop
their applications which may be useful during debug or
for products requiring frequent upgrades or program
changes. OTP devices are also applicable for use in applications that require low or medium volume production
runs.
T im e r /E v e n t 0 C o u n te r
In te rru p t V e c to r
T im e r /E v e n t 1 C o u n te r
In te rru p t V e c to r
0 1 0 H
S P I
In te rru p t V e c to r
F F F H
1 5 b its
Program Memory Structure
· Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
jumps to this location and begins execution.
Structure
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by
separate table pointer registers.
· Location 010H
This vector is used by serial interface. When 8-bits of
data have been received or transmitted successfully
from serial interface. The program will jump to this location and begin execution if the interrupt is enabled
and the stack is not full.
· Table location
Special Vectors
Any location in the program memory can be used as
look-up tables. There are three methods to read the
Program Memory data using two table read instructions: ²TABRDC² and ²TABRDL², transfer the contents of the lower-order byte to the specified data
memory, and the higher-order byte to TBLH (08H).
The three methods are shown as follows:
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
¨
Using the instruction ²TABRDC [m]² for the current
Program Memory page, where one page=
256words, where the table location is defined by
TBLP in the current page. This is where the configuration option has disabled the TBHP register.
¨
Using the instruction ²TABRDC [m]², where the table location is defined by registers TBLP and TBHP.
Here the configuration option has enabled the
TBHP register.
¨
Using the instruction ²TABRDL [m]², where the table location is defined by registers TBLP in the last
page which has the address range 0F00H~0FFFH.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program jumps
to this location and begins execution.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
jumps to this location and begins execution.
Instruction
U S B
In te rru p t V e c to r
Table Location Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits when TBHP register is disabled.
TBHP register Bit 3 ~ Bit 0 when TBHP is enabled.
@[email protected]: Table Pointer TBLP bits
Rev. 1.00
9
April 1, 2010
HT82D40REW
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointers, TBLP and TBHP, are read/write registers, which indicate the table location. Before
accessing the the table, the locations must be placed
in the TBLP and TBHP registers (if the configuration
option has disabled TBHP then the value in TBHP has
no effect). TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR
and errors can occur. Using the table read instruction
in the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the ISR, the
interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
on the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the Program Memory data as defined by the
TBLP and TBHP values. If the Program Memory code
option has disabled TBHP, the instruction ²TABRDC
[m]² reads the Program Memory data as defined by
TBLP only in the current Program Memory page.
registers define the full address of the look-up table.
Using the TBHP must be selected by configuration option, if not used table data can still be accessed but only
the lower byte address in the current page or last page
can be defined.
After setting up the table pointers, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² instruction is executed.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the TBLP register and the
higher order address in the TBHP register. These two
P ro g ra m C o u n te r
H ig h B y te
T B H P
P ro g ra m
M e m o ry
T B L P
P ro g ra m
M e m o ry
T B L P
T B L H
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
T a b le C o n te n ts L o w
H ig h B y te o f T a b le C o n te n ts
B y te
S p e c ifie d b y [m ]
L o w
B y te o f T a b le C o n te n ts
Table Read - TBLP/TBHP
Table Read - TBLP only
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
Register
Bits
Read/Write
TBHP (1FH)
3~0
R/W
Rev. 1.00
Functions
Store current table location bit11~bit8 value
10
April 1, 2010
HT82D40REW
tempreg1
tempreg2
db
db
:
:
mov
a,06h
; initialise table pointer - note that this address is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address ²F06H² transferred to tempreg1 and TBLH
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
; transfers value in table referenced by table pointer to tempreg2
; data at prog.memory address ²F05H² transferred to tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte register TBLH
:
:
?
?
; temporary register #1
; temporary register #2
org
F00h
; sets initial address of last page
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
mon to all microcontrollers, such as ACC, PCL, etc.,
have the same Data Memory address.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
0 0 H
Data Memory
S p e c
P u rp o
D a
M e m o
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
3 F H
4 0 H
G e n e ra l
P u rp o s e
D a ta
M e m o ry
D F H
Data Memory Structure
Note:
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are
8 bits wide. The start address of the Data Memory for all
devices is the address ²00H². Registers which are comRev. 1.00
ia l
s e
ta
ry
11
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer register MP.
April 1, 2010
HT82D40REW
Special Purpose Data Memory
Special Function Registers
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. It is divided into two banks, Bank 0 and Bank1.
Most of the registers are both readable and writeable
but some are protected and are readable only, the details of which are located under the relevant Special
Function Register section. Note that for locations that
are unused, any read instruction to these addresses will
return the value ²00H².
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the
point where the General Purpose Memory begins is reserved and attempting to read data from these locations
will return a value of 00H.
The Special Purpose Registers for the USB interface
are stored in Bank 1 which can only be accessed by first
setting the Bank Pointer to a value of 01H and then using Indirect Addressing Register IAR1 and Memory
Pointer MP1. Bank 1 can only be accessed indirectly using the MP1 Memory Pointer, direct addressing is not
possible.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
3 F H
B a
IA
M
IA
M
n k 0
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
4 0 H
4 1 H
4 2 H
4 3 H
4 4 H
4 5 H
4 6 H
4 7 H
4 8 H
4 9 H
4 A H
Indirect Addressing Register - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
B a n k 1
U S B _ S T A T
P IP E _ C T R L
A W R
S T A L L
P IP E
S IE S
M IS C
E N D P T _ E N
F IF O 0
F IF O 1
F IF O 2
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers providing a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access both banks.
S P IR
IN T C
T B H
U S C
U S R
S C C
S B C
S B D
1
P
R
R
: U n u s e d re a d a s "0 "
Special Purpose Data Memory
Rev. 1.00
12
April 1, 2010
HT82D40REW
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; setup size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
loop:
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.
Accumulator - ACC
data pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table read
data instruction has been executed.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Look-up Table Registers - TBLP, TBLH, TBHP
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and
indicate the location where the table data is located. Their
value must be setup before any table read commands are
executed. Their values can be changed, for example using
the ²INC² or ²DEC² instructions, allowing for easy table
Rev. 1.00
13
April 1, 2010
HT82D40REW
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Timer/Event Counter Registers TMR0, TMR0C, TMR1H, TMR1L, TMR1C
· C is set if an operation results in a carry during an ad-
Both devices possess a single internal 8-bit count-up
timer. An associated register known as TMR0 is the location where the timers 8-bit value is located. This register can also be preloaded with fixed data to allow
different time intervals to be setup. An associated control register, known as TMR0C, contains the setup information for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
All devices possess one internal 16-bit count-up timer.
An associated register pair known as TMR1L/TMR1H is
the location where the timer 16-bit value is located. This
register can also be preloaded with fixed data to allow
different time intervals to be setup. An associated control register, known as TMR1C, contains the setup information for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
Input/Output Ports and Control Registers
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it.
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA and PB. These labeled
I/O registers are mapped to specific addresses within
the Data Memory as shown in the Data Memory table,
which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC and PBC also
mapped to specific addresses with the Data Memory.
Interrupt Control Registers - INTC, INTC1
The microcontrollers provide two internal timer/event
counter overflow interrupts, one USB interrupt and one
SPI interrupt. By setting various bits within this register
using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this
register, the EMI bit, acts like a global enable/disable
and is used to set all of the interrupt enable bits on or off.
This bit is cleared when an interrupt routine is entered to
disable further interrupt and is set by executing the
²RETI² instruction.
Rev. 1.00
The control register specifies which pins of that port are
set as inputs and which are set as outputs. To setup a
pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low.
During program initialisation, it is important to first setup
the control registers to specify which pins are outputs
and which are inputs before reading data from or writing
data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the
²SET [m].i² and ²CLR [m].i² instructions. The ability to
14
April 1, 2010
HT82D40REW
Port Pin Wake-up
change I/O pins from output to input and vice versa by
manipulating specific bits of the I/O control registers during normal program operation is a useful feature of
these devices.
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the port pins from high to low. After a HALT instruction
forces the microcontroller into entering the Power Down
Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the
port pin changes from high to low. This function is especially suitable for applications that can be woken up via
external switches. Each pin on Port A and PB7 has the
capability to wake-up the device on an external falling
edge. Note that some pins can only be setup nibble wide
whereas other can be bit selected to have a wake-up
function.
Bank Pointer - BP
The Special Purpose Data Memory is divided into two
Banks, Bank 0 and Bank 1. The USB control registers
are located in Bank 1, while all other registers are located in Bank 0. The Bank Pointer selects which bank
data is to be accessed from. If Bank 0 is to be accessed,
then BP must be set to a value of 00H, while if Bank 1 is
to be accessed, then BP must be set to a value of 01H.
b 7
b 0
B P 0
B a n k P o in te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer
I/O Port Control Registers
Each I/O port has its own control register named PAC
and PBC to control the input/output configuration. With
this control register, each CMOS output or input with or
without pull-high resistor structures can be reconfigured
dynamically under software control. Each of the I/O ports
is directly mapped to a bit in its associated port control
register. Note that several pins can be setup to have
NMOS or PMOS outputs using configuration options.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high and
wake-up options for all ports, the user is provided with
an I/O structure to meet the needs of a wide range of application possibilities.
The microcontroller provides up to 9 bidirectional input/output lines labeled with port names PA and PB7.
These I/O ports are mapped to the Data Memory with
addresses as shown in the Special Purpose Data Memory table. For input operation, these ports are non-latching, which means the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data
is latched and remains unchanged until the output latch
is rewritten.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a ²1². This
will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will
be setup as an output. If the pin is currently setup as an
output, instructions can still be used to read the output
register. However, it should be noted that the program
will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
Pull-high Resistors
Pin-shared Functions
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the
capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS
transistors. A configuration option on each I/O port pin
can be selected to select pull-high resistor.
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
· External Timer0 Clock Input
Port A CMOS/NMOS/PMOS Structure
The external timer pin TMR0 is pin-shared with the I/O
pin PA6. To configure this pin to operate as timer input,
the corresponding control bits in the timer control register must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
The pins on Port A can be setup via configuration option
to be either CMOS, NMOS or PMOS types.
Rev. 1.00
15
April 1, 2010
HT82D40REW
Programming Considerations
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and
port control register will be set high. This means that all
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the PAC and
PBC port control registers are then programmed to
setup some pins as outputs, these output pins will have
an initial high output value unless the associated PA and
PB port data registers are first programmed. Selecting
which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct value into the
port control register or by programming individual bits in
the port control register using the ²SET [m].i² and ²CLR
[m].i² instructions. Note that when using these bit control
instructions, a read-modify-write operation takes place.
The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then
rewrite this data back to the output ports.
· SPI interface pins
The SPI interface pins known as SDI, SDO, SCK and
SCS are pin-shared with the I/O lines PB3~PB6 respectively. To configure these pins to operate as input
or output, the corresponding control bit in the SPI control register must be correctly set. However, these pins
are not bonded out to external pins and used as the
master SPI pins to be internally connect to the RF
Transceiver slave SPI interface to control the overall
RF Transceiver functions.
· External Timer1 Clock Input
The external timer pin TMR1 is pin-shared with the I/O
pin PA7. To configure this pin to operate as timer input,
the corresponding control bits in the timer control register must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation
All pins have the additional capability of providing
wake-up functions. When the device is in the Power
Down Mode, various methods are available to wake the
device up. One of these is a high to low transition of any
of the Port pins. Single or multiple pins can be setup to
have this function.
I/O Pin Structures
The diagram illustrates a generic I/O pin internal structures. As the exact logical construction of the I/O pin will
differ and as the pin-shared structures are not illustrated
this diagram is supplied as a guide only to assist with the
functional understanding of the I/O pins.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
W r ite D a ta R e g is te r
S
I/O
S y s te m
p in
D a ta B it
Q
D
C K
Q
S
R e a d D a ta R e g is te r
W e a k
P u ll- u p
Q
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D D
M
U
X
W a k e -u p
W a k e - u p O p tio n
Input/Output Ports
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HT82D40REW
Timer/Event Counters
TMR0. For 16-bit Timer/Event Counter 1, the timer registers are known as TMR1L and TMR1H. The value in
the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from
the initial value loaded by the preload register to the full
count of FFH for the 8-bit timer or FFFFH for the 16-bit
timer at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. This device contains two
count-up timers of 8-bit and 16-bit capacities respectively. As each timer has three different operating
modes, they can be configured to operate as a general
timer, an external event counter or as a pulse width
measurement device.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the Timer/Event Counter and
into which an initial value can be preloaded, and is
known as TMR0, TMR1H or TMR1L. Reading from this
register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer
Control Register, which defines the timer options and
determines how the Timer/Event Counter is to be used,
and has the name TMR0C or TMR1C. This device can
have the timer clocks configured to come from the internal clock sources. In addition, the timer clock source can
also be configured to come from the external timer pins.
To achieve a maximum full range count of FFH for the
8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be
noted that after power-on, the preload register will be in
an unknown condition. Note that if the Timer/Event
Counter is switched off and data is written to its preload
registers, this data will be immediately written into the
actual timer registers. However, if the Timer/Event
Counter is enabled and counting, any new data written
into the preload data registers during this period will remain in the preload registers and will only be written into
the timer registers the next time an overflow occurs.
The external clock source is used when the Timer/Event
Counter is in the event counting mode, the clock source
being provided on the external timer pin. The pin has the
name TMR0 or TMR1 and is pin-shared with an I/O pin.
Depending upon the condition of the T0E or T1E bit in
the Timer Control Register, each high to low, or low to
high transition on the external timer input pin will increment the Timer/Event Counter by one.
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note
when using instructions to preload data into the low byte
timer register, namely TMR1L, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register
should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
Configuring the Timer/Event Counter Input Clock
Source
The Timer/Event Counter¢s clock can originate from various sources. The instruction clock source (system
clock source divided by 4) is used when the Timer/Event
Counter 0 or Timer/Event Counter 1 is in the timer mode
or in the pulse width measurement mode. The external
clock source is used when the Timer/Event Counter is in
the event counting mode, the clock source being provided on the external timer pin, TMR0 or TMR1. Depending upon the condition of the T0E or T1E bit, each
high to low, or low to high transition on the external timer
pin will increment the counter by one.
Timer Register - TMR0, TMR1L/TMR1H
The timer registers are special function registers located
in the Special Purpose RAM Data Memory and are the
places where the actual timer values are stored. For
8-bit Timer/Event Counter 0, this register is known as
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HT82D40REW
D a ta B u s
P r e lo a d R e g is te r
T 0 M 1
fS
T M R 0
Y S
/4
R e lo a d
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 E
T im e r /E v e n t
C o u n te r
T 0 O N
O v e r flo w
to In te rru p t
8 - B it T im e r /E v e n t C o u n te r
8-bit Timer/Event Counter 0 Structure
D a ta B u s
L o w B y te
B u ffe r
T 1 M 1
fS
T M R 1
Y S
/4
1 6 - B it
P r e lo a d R e g is te r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 1 E
H ig h B y te
T 1 O N
L o w
R e lo a d
B y te
1 6 - B it T im e r /E v e n t C o u n te r
O v e r flo w
to In te rru p t
16-bit Timer/Event Counter 1 Structure
b 7
T 0 M 1
b 0
T 0 M 0
T 0 O N
T 0 E
T M R 0 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
T im e r /E v e n t C o u n te r 0 a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
T im e r /E v e n t C o u n te r 0 C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 0 M 0
T 0 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b 7
T 1 M 1
b 0
T 1 M 0
T 1 O N
T 1 E
T M R 1 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
T im e r /E v e n t C o u n te r 1 a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
T im e r /E v e n t C o u n te r 1 c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g m o d e s e le c
T 1 M 0
T 1 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
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Timer Control Register - TMR0C/TMR1C
Control Register Operating Mode
Select Bits for the Timer Mode
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register. For devices are two timer control registers known as TMR0C,
TMR1C . It is the timer control register together with its
corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can
be used, it is essential that the appropriate timer control
register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried
out during program initialization.
0
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, T0M1/T0M0
or T1M1/T1M0, in the Timer Control Register must be
set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7 Bit6
0
1
In this mode, the external timer pin, TMR0 or TMR1, is
used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other
bits in the Timer Control Register have been setup, the
enable bit T0ON or T1ON, which is bit 4 of the Timer
Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit
T0E or T1E, which is bit 3 of the Timer Control Register,
is low, the Timer/Event Counter will increment each time
the external timer pin receives a low to high transition. If
the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to
low transition. When it is full and overflows, an interrupt
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer
Control Register must be set to the correct value as
shown.
Y S
1
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the
other bits in the Timer Control Register have been
setup, the enable bit T0ON or T1ON, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer/Event Counter to run.Each time an internal clock
cycle occurs, the Timer/Event Counter increments by
one. When it is full and overflows, an interrupt signal is
generated and the Timer/Event Counter will reload the
value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in
the Interrupt Control Register, INTC, is reset to zero.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. If
the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control
Register which is known as T0E or T1E, depending
upon which timer is used.
fS
Bit7 Bit6
/4
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
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HT82D40REW
counting until the external timer pin returns to its original
high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop
counting. If the Active Edge Select bit is high, the
Timer/Event Counter will begin counting once a low to
high transition has been received on the external timer
pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit
will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in
the Pulse Width Measurement Mode, the enable bit is
automatically reset to zero when the external control
signal on the external timer pin returns to its original
level, whereas in the other two modes the enable bit can
only be reset to zero under program control.
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the
Timer Control Register must be set to the correct
valueas shown.
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
Bit7 Bit6
1
1
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the
other bits in the Timer Control Register have been
setup, the enable bit T0ON or T1ON, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer/Event Counter, however it will not actually start
counting until an active edge is received on the external
timer pin.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse
width measurement pin, two things have to happen. The
first is to ensure that the Operating Mode Select bits in
the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode and the second is to ensure that the port control register configures
the pin as an input.
If the Active Edge Select bit T0E or T1E, which is bit 3 of
the Timer Control Register, is low, once a high to low
transition has been received on the external timer pin,
TMR0 or TMR1, the Timer/Event Counter will start
E x te r n a l T im e r
P in In p u t
T 0 O N o r T 1 O N
( w ith T 0 E o r T 1 E = 0 )
fS
Y S
/4
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
fS
Y S
+ 2
+ 3
+ 4
/4 is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
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HT82D40REW
I/O Interfacing
tive. The edge select, timer mode and clock source
control bits in timer control register must also be correctly set to ensure the timer is properly configured for
the required application. It is also important to ensure
that an initial value is first loaded into the timer registers
before the timer is switched on; this is because after
power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can
be turned on and off by controlling the enable bit in the
timer control register. Note that setting the timer enable
bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit
modification, may lead to improper timer operation if executed as a single timer control register byte write instruction.
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, require the use of the external TMR0 and TMR1 pins for
correct operation. As these pins are shared pins they
must be configured correctly to ensure they are setup
for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the
mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register
bits for these pins must be set high to ensure that the pin
is setup as an input. Any pull-high resistor configuration
option on these pins will remain valid even if the pin is
used as a Timer/Event Counter input.
Programming Considerations
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up signal from occurring, the timer interrupt
request flag should first be set high before issuing the
²HALT² instruction to enter the Power Down Mode.
When configured to run in the timer mode, the internal instruction clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
counter is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width
measurement mode, the internal instruction clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not synchronised with the internal timer clock, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
small differences in measured values requiring programmers to take this into account during programming. The
same applies if the timer is configured to be in the event
counting mode, which again is an external event and not
synchronised with the internal system or timer clock.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter to
be in the timer mode, which uses the internal system
clock as the clock source.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error,
this should be taken into account by the programmer.
Care must be taken to ensure that the timers are properly initialised before using them for the first time. The
associated timer interrupt enable bits in the interrupt
control register must be properly set otherwise the internal interrupt associated with the timer will remain inac-
Rev. 1.00
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HT82D40REW
org 04h
; USB interrupt vector
reti
org 08h
; Timer/Event Counter interrupt vector
jmp tmr0int
; jump here when Timer0 overflows
:
org 20h
; main program
;internal Timer/Event Counter 0 interrupt routine
Tmr0int:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh
; setup Timer preload value
mov tmr0,a;
mov a,080h
; setup Timer control register
mov tmr0c,a
; timer mode
; setup interrupt register
mov a,005h
; enable master interrupt and timer interrupt
mov intc,a
set tmr0c.4
; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a JMP statement which will jump to another section of program which is known as the interrupt
service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must
be terminated with a RETI statement, which retrieves
the original Program Counter address from the stack
and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
Interrupts are an important part of any microcontroller
system. When an internal function such as a
Timer/Event Counter overflow or a USB interrupt occur,
their corresponding interrupt will enforce a temporary
suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. The device contains several interrupts generated by the Timer/Event Counters overflow, USB interrupt and SPI interrupt.
Interrupt Register - INTC, INTC1
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the interrupt
control registers named INTC and INTC1. By controlling
the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when
an interrupt occurs, the corresponding request flag will
be set by the microcontroller. The global enable flag if
cleared to zero will disable all interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
When a USB or SPI interrupt occurs or one of the
Timer/Event Counters overflow, if their appropriate interrupt enable bit is set, the Program Counter, which
stores the address of the next instruction to be executed, will be transferred onto the stack. The Program
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
Rev. 1.00
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HT82D40REW
b 7
b 0
T 1 F
T 0 F
U S B F
E T 1 I
E T 0 I
E U I
IN T C
E M I
R e g is te r
M a s te r in te r r u p t g lo b a l e n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
U S B in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
U S B in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
INTC Register
b 7
b 0
S IF
E S II
IN T C 1 R e g is te r
S e r ia l in te r fa c e in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
S e r ia l in te r fa c e in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
INTC1 Register
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
U S B In te rru p t
R e q u e s t F la g U S B F
F IF O
T im e r /E v e n t C o u n te r 0 O v e r flo w
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1 O v e r flo w
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
S e r ia l In te r fa c e ( S P I)
In te r r u p t R e q u e s t F la g S IF
E S II
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
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HT82D40REW
Interrupt Priority
When the PC Host accesses the FIFO of the device, the
corresponding request bit, USR, is set, and a USB interrupt is triggered. So the user can easy determine which
FIFO has been accessed. When the interrupt has been
served, the corresponding bit should be cleared by firmware. When the device receive a USB Suspend signal
from Host PC, the suspend line (bit0 of USC) is set and a
USB interrupt is also triggered.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB Interrupt
1
004H
Timer/Event Counter 0 Overflow
Interrupt
2
008H
Timer/Event Counter 1 Overflow
Interrupt
3
00CH
Serial Interface (SPI) Interrupt
4
010H
Also when device receive a Resume signal from Host
PC, the resume line (bit3 of USC) is set and a USB interrupt is triggered.
Serial Interface (SPI) Interrupt
For a Serial Interface (SPI) interrupt to occur the global
interrupt enable bit EMI and the corresponding interrupt
enable bit, ESII, must first be set. An actual SPI interrupt
will take place when the SPI interrupt request flag SIF is
set, a situation that will occur when the SPI interrupt
event occurs. When the interrupt is enabled, the stack is
not full and a SPI interrupt event occurs a subroutine call
to SPI vector will take place. When the interrupt is serviced, the SPI interrupt flag SIF will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
In cases where the USB interrupt, Timer/Event Counters overflow interrupts and the SPI interrupt are enabled and where these interrupts occur simultaneously,
the USB interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual
interrupts using the interrupt registers can prevent simultaneous occurrences.
Timer/Event Counter Interrupt
Programming Considerations
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I/ET1I, must first be set. An actual Timer/Event Counter interrupt will take place when
the Timer/Event Counter interrupt request flag,
T0F/T1F, is set, a situation that will occur when the
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 08H/0CH, will take place. When the interrupt is serviced, the timer interrupt request flag,
T0F/T1F, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
USB Interrupt
The USB interrupts are triggered by the following USB
events causing the related interrupt request flag, USBF,
to be set.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
· Access of the corresponding USB FIFO from PC
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents
should be saved in advance.
· A USB suspend signal from the PC
· A USB resume signal from the PC
· A USB Reset signal
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag, USBF, and the
EMI bit will be cleared to disable other interrupts.
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HT82D40REW
Reset and Initialisation
proper reset operation. In such cases it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
V D D
1 0 0 k W
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
R E S
0 .1 m F
V S S
Basic Reset Circuit
Reset Functions
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
0 .0 1 m F
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing a
Rev. 1.00
V D D
1 0 0 k W
R E S
1 0 k W
0 .1 m F
V S S
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
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HT82D40REW
· RES Pin Reset
· Watchdog Time-out Reset during Normal Operation
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tS
D D
WDT Time-out Reset during Power Down
Timing Chart
D D
tR
S T
S S T T im e - o u t
S T D
S S T T im e - o u t
· Watchdog Time-out Reset during Power Down
In te rn a l R e s e t
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
RES Reset Timing Chart
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
L V R
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
Low Voltage Reset Timing Chart
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HT82D40REW
Reset Initial Conditions
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled by
various microcontroller operations, such as the Power
Down function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF
Item
RESET Conditions
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer Counter will be turned off
0
0
RES reset during power-on
0
0
RES wake-up during Power Down
Timer/Event
Counter
0
0
RES or LVR reset during normal operation
Input/Output Ports I/O ports will be setup as inputs
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Stack Pointer
Stack Pointer will point to the top
of the stack
Note: ²u² stands for unchanged
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers.
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
---- ---0
---- ---0
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000H
0000H
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
BP
USB Reset USB Reset
(Normal)
(HALT)
TBHP
---- xxxx
---- uuuu
---- uuuu
---- uuuu
---- uuuu
---- uuuu
---- uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
STATUS
--00 xxxx
--1u uuuu
--00 uuuu
--00 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
uu-u u---
uu-u u---
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
uu-u u---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
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HT82D40REW
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
SPIR
0000 0000
0000 0000
0000 0000
0000 0000
0000 uuuu
0000 0000
0000 0000
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
---0 ---0
---0 ---0
USC
11xx 0000
uuxx uuuu
11xx 0000
11xx 0000
uuxx uuuu
uu00 0u00
uu00 0u00
USR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
u1uu 0000
u1uu 0000
SCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0uu0 u000
0uu0 u000
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
0110 0000
0110 0000
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
USB_STAT
---x xxxx
---x xxxx
---x xxxx
---x xxxx
---x xxxx
---x xxxx
---x xxxx
PIPE_CTRL
0000 0110
0000 0uuu
0000 0110
0000 0110
0000 0uuu
0000 0110
0000 0110
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0110
0000 0uuu
0000 0110
0000 0110
0000 0uuu
0000 0110
0000 0110
PIPE
0000 0000
xxxx xxxx
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
SIES
0100 0000
uxux xuuu
0100 0000
0100 0000
uxux xuuu
0100 0000
0100 0000
MISC
0x00 0000
uxuu uuuu
0x00 0000
0x00 0000
uxuu uuuu
0x00 0000
0x00 0000
ENDPT_EN
0000 0111
0000 0uuu
0000 0111
0000 0111
0000 0uuu
0000 0111
0000 0111
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
Register
Note:
²*² means ²warm reset²
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Oscillator
The clock source for these devices is provided by an integrated oscillator requiring no external components.
This oscillator has two fixed frequencies of either 6MHz,
or 12MHz, the selection of which is made by the
SCLKSEL bit in the SCC register.
Rev. 1.00
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 31.2ms at
5V requiring no external components. When the device
enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
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HT82D40REW
Power Down Mode and Wake-up
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer.
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode. When the device enters this mode,
the normal operating current, will be reduced to an extremely low standby current level. This occurs because
when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring
a full reset. This feature is extremely important in application areas where the microcontroller must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on each port pin
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or RTC oscillator. The WDT will stop if its clock source
originates from the system clock.
Each pin on the I/O ports can be setup via an individual
configuration option to permit a negative transition on
the pin to wake-up the system. When a port pin wake-up
occurs, the program will resume execution at the instruction following the ²HALT² instruction.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the microcontroller
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit designer if the power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
Rev. 1.00
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HT82D40REW
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Once the internal WDT oscillator (RC oscillator normally
with a period of 31.2ms) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of approximately 8ms. This time-out period may vary with
temperature, VDD and process variations. By using the
WDT prescaler, longer time-out periods can be realized.
Writing data to WDTS2, WDTS1, WDTS0 (bit 2, 1, 0 of
the WDTS) can give different time-out periods. If
WDTS2, WDTS1, WDTS0 are all equal to ²1², the division ratio is up to 1:128, and the maximum time-out period is 1s.
Watchdog Timer
If the WDT oscillator is disabled, the WDT clock source
may still come from the instruction clock and operate in
the same manner except that in the Power down Mode
state the WDT may stop counting and lose its protecting
purpose. In this situation the WDT logic can be restarted
by external logic. The high nibble and bit 3 of the WDTS
are reserved for user defined flags, which can be used
to indicate some specified status.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), enabled using a configuration
option. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location
with unpredictable results. If the Watchdog Timer is disabled, all the executions related to the WDT results in no
operation.
C L R
W D T 1 F la g
C L R
W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
8 - b it C o u n te r
(¸ 2 5 6 )
W D T C lo c k S o u r c e
C L R
7 - b it P r e s c a le r
8 -to -1 M U X
W D T S 0 ~ W D T S 2
W D T T im e - o u t
Watchdog Timer
Bit No.
Label
Function
0
1
2
WDTS0
WDTS1
WDTS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, division ratio = 1:1
Bit 2,1,0 = 001, division ratio = 1:2
Bit 2,1,0 = 010, division ratio = 1:4
Bit 2,1,0 = 011, division ratio = 1:8
Bit 2,1,0 = 100, division ratio = 1:16
Bit 2,1,0 = 101, division ratio = 1:32
Bit 2,1,0 = 110, division ratio = 1:64
Bit 2,1,0 = 111, division ratio = 1:128
3
WDTS3
Bit3=1, PDP, and PDN connected to 300kW pull-high resistor
Bit3=0, No pull-high - default at MCU reset
4~6
7
¾
Not used
WDTS7
Bit7=1, USB reset signal can reset MCU and set URST_FLAG (bit 2 of USC register)
(default state after a MCU reset)
Bit7=0, USB reset signal cannot reset MCU
WDTS Register
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HT82D40REW
Suspend Wake-Up and Remote Wake-Up
To Configure as PS2 Device
If there is no signal on the USB bus for over 3ms, the device will go into a suspend mode. The Suspend line (bit
0 of the USC register) will be set to ²1² and a USB interrupt is triggered to indicate that the devices should jump
to the suspend state to meet the 500mA USB suspend
current spec.
The devices can also be configured as a USB interface
or PS2 interface device, by configuring the mode control
bits named MODE_CTRL1 and MODE_CTRL0 bits (bit
5~4 of the USR register). If the MODE_CTRL1 and
MODE_CTRL0 bits are equal to ²1² and ²0² respectively, the device will be configured as a PS2 interface,
pin USB D- is configured as a PS2 DATA pin and USB
D+ is configured as a PS2 CLK pin. The user can read or
write to the PS2 DATA or PS2 CLK pin by accessing the
corresponding bit PS2_DAI (bit 4 of the USC register),
PS2_CKI (bit 5 of the USC register), PS2_DAO (bit 6 of
the USC register) and PS2_CKO (bit 7 of the USC register) respectively.
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the
USBCKEN bit which is bit3 of the SCC register to ²0².
The suspend current is 400mA.
The user can further decrease the suspend current to
250mA by setting the BGOFF bit which is bit4 of the SCC
register. If this bit is necessary to be set when the USB
entering the suspend mode, the LVR function must be
disabled by a configuration option.
The user should make sure that in order to read the data
properly, the corresponding output bit must be set to ²1².
For example, if it is desired to read the PS2 Data by
reading PS2_DAI, then PS2_DAO should set to ²1².
Otherwise it is always read as ²0².
When the resume signal is sent out by the host, the devices will wake up the MCU with a USB interrupt and the
Resume line (bit 3 of the USC register) is set. In order to
make the device function properly, the firmware must
set the USBCKEN (bit 3 of the SCC register) to 1 and
clear the BGOFF (bit4 of the SCC register). Since the
Resume signal will be cleared before the Idle signal is
sent out by the host, the Suspend line (bit 0 of the USC
register) will be set to ²0². So when the MCU is detecting
the Suspend line (bit0 of USC register), the Resume line
condition should be noted and taken into consideration.
If the MODE_CTRL1 and MODE_CTRL0 bits are equal
to ²0² and ²1² respectively, the device is configured as a
USB interface. Both the USB PDN and USB PDP are
driven by the SIE. The user can only write or read the
USB data through the corresponding FIFO. Both the default value of the MODE_CTRL1 and MODE_CTRL0
bits is ²00B².
USB Interface
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt will be triggered. The following is the timing diagram.
There are eleven registers used for the USB function.
The AWR register contains the current address and a
remote wake up function control bit. The initial value of
AWR is ²00H². The address value extracted from the
USB command is not to be loaded into this register until
the SETUP stage is completed.
S U S P E N D
U S B R e s u m e S ig n a l
Bit No.
U S B _ IN T
As the device has a remote wake up function it can
wake-up the USB Host by sending a wake-up pulse
through RMWK (bit 1 of the USC register). Once the
USB Host receives a wake-up signal from the devices, it
will send a Resume signal to the device. The timing is as
follows:
Label
R/W
Function
0
WKEN
W
Remote wake-up
enable/disable
7~1
AD6~AD0
W
USB device address
AWR (42H) Register
S U S P E N D
M in . 1
U S B C L K
R M O T _ W K
U S B R e s u m e S ig n a l
M in . 2 .5 m s
U S B _ IN T
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HT82D40REW
Bit No.
Label
R/W
Function
0
SUSPEND
R
Read only, USB suspend indication. When this bit is set to ²1² (set by the SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also
triggered on any change of this bit.
1
RMOT_ WK
W
USB remote wake up command. Set by the MCU to force the USB host to leave the
suspend mode. When this bit is set to ²1², a 2ms delay for clearing this bit to ²0² is
needed to insure the RMWK command is accepted by SIE.
2
URST_ FLAG
USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect which bus (PS2 or USB) is attached. When the URST is set to ²1², this indiR/W
cates that a USB reset has occurred (the attached bus is USB) and a USB interrupt
will be initialised.
3
RESUME_O
R
USB resume indication. When the USB leaves the suspend mode, this bit is set to
²1² (set by the SIE). This bit will appear for 20ms waiting for the MCU to detect.
When the RESUME is set by the SIE, an interrupt will be generated to wake-up the
MCU. In order to detect the suspend state, the MCU should set the USBCKEN and
clear SUSP2 (in the SCC register) to enable the SIE detect function. The RESUME
will be cleared while SUSP is going to ²0². When the MCU is detecting the SUSP,
the condition of RESUME (which wakes-up the MCU ) should be noted and taken
into consideration.
4
PS2_DAI
R
Read only, PDN/DATA input
5
PS2_CKI
R
Read only, PDP/CLK input
6
PS2_DAO
W
Data for driving the PDN/DATA pin when working under 3D PS2 mouse function.
(Default=²1²)
7
PS2_CKO
W
Data for driving the PDP/CLK pin when working under 3D PS2 mouse function.
(Default=²1²)
USC (20H) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus, PS2 or USB. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB
interrupt will occur, if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is
served, the endpoint request flag has to be cleared to ²0².
Bit No.
Label
0
EP0_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 0 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit
should be cleared by firmware.
1
EP1_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 1 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit
should be cleared by firmware.
2
EP2_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 2 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit
should be cleared by firmware.
3, 6
¾
4
5
7
R/W
¾
Function
Reserved
00: Non-USB mode, turn-off V33O, both PDP and PDN can be read and write default
01: Non-USB mode, has 200 ohm between VDD and V33O, both PDP and PDN
can be read and write
MODE_CTRL0
R/W
MODE_CTRL1
10: USB mode, 1.5kW between PDN and V33O, V33O output 3.3V,
both PDP and PDN are read only
11: Non-USB mode, V33O output 3.3V, both PDP and PDN can be read and
write
USB_flag
R/W
This flag is used to indicate that the MCU is in the USB mode - Bit=1
This bit is R/W by FW and will be cleared to ²0² after power-on reset - Default=²0²
USR (21H) Register
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HT82D40REW
There is a system clock control register implemented to select the clock used in the MCU. This register consists of the
USB clock control bit, USBCKEN, second suspend mode control bit, SUSP2, and a system clock selection bit,
SYSCLK. The PS2 mode indicate bit, PS2_flag, and a system clock adjust control bit, CLK_adj.
Bit No.
Label
R/W
0, 1, 2
¾
¾
3
USBCKEN R/W
Function
Reserved bit set ²0²
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=²0²)
When set to 1, turn-off Band-gap circuit. Default value is 0.
In the Power-down Mode this bit should be set high to reduce power consumption.The
LVR has no function. In the USB mode this bit cannot be set high.
4
SUSP2
¾
5
PS2_flag
R/W
6
SYSCLK
This bit is used to specify the system oscillator frequency used by the MCU. If an InteR/W grated 6MHz oscillator is used, this bit should be set to ²1². If an Integrated 12MHz oscillator is used, this bit should be cleared to ²0². (default).
CLK_adj
This bit is used to adjust the system clock for the USB mode for temperature changes.
In the Power-down Mode this bit should be set high to reduce power consumption.
R/W
0: enable (default)
1: disable
7
This flag is used to indicate that the MCU is in the PS2 mode. (Bit=1)
This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)
SCC (22H) Register
STALL and PIPE, PIPE_CTRL, ENDPT_EN Registers
The PIPE register represents whether the corresponding endpoint is accessed by the host or not. After an ACT_EN signal has been sent out, the MCU can check which endpoint had been accessed. This register is set only after the a time
when the host is accessing the corresponding endpoint.
The STALL register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set.
The PIPE_CTRL Register is used for configuring the IN (Bit=1) or OUT (Bit=0) Pipe. The default is define IN pipe. Bit0
(DATA0) of the PIPE_CTRL Register is used to set the data toggle of any endpoint (except endpoint 0) using data toggles to the value DATA0. Once the user wants any endpoint (except endpoint 0) using data toggles to the value DATA0.
the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycles.
The Endpt_EN Register is used to enable or disable the corresponding endpoint (except endpoint 0) Enable Endpoint
(Bit=1) or disable Endpoint (Bit=0)
The bitmaps are list are shown in the following table:
Register
Name
R/W
Bit7~Bit3
Reserved
Bit 2
Bit 1
Bit 0
Default
Value
PIPE_CTRL
R/W
¾
SETIO2
SETIO1
DATA0
00000111
STALL
R/W
¾
STL2
STL1
STL0
00000111
R
¾
Pipe2
Pipe1
Pipe0
00000000
R/W
¾
EP2EN
EP1EN
EP0EN
00000111
PIPE
ENDPT_EN
PIPE_CTRL (41H), STALL (43H), PIPE (44H) and ENDPT_EN (47H) Registers
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HT82D40REW
The USB_STAT Register (40H) is used to indicate the present USB signal state.
Bit No.
Label
R/W
Function
0
EOP
R/W
This bit is used to indicate the SIE has detected a EOP USB signal in the USB Bus.
This bit is set by SIE and cleared by F/W.
1
J_state
R/W
This bit is used to indicate the SIE has detected a J_state USB signal in the USB Bus.
This bit is set by SIE and cleared by F/W.
2
K_state
R/W
This bit is used to indicate the SIE has detected a K_state USB signal in the USB Bus.
This bit is set by SIE and cleared by F/W.
3
SE0
R/W
This bit is used to indicate the SIE has detected a SE0 noise in the USB Bus. This bit
is set by SIE and cleared by F/W.
4
SE1
R/W
This bit is used to indicate the SIE has detected a SE1 noise in the USB Bus. This bit
is set by SIE and cleared by F/W.
5~7
¾
¾
Unused bit, read as ²0²
USB_STAT (40H) Register
The SIES Register is used to indicate the present signal state in which the SIE receives and also defines whether the
SIE has to change the device address automatically.
Bit No.
Label
R/W
Function
0
ADR_ SET
R/W
This bit is used to configure the SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register.
When this bit is set to ²1² by F/W, the SIE will update the device address with the
value of the Address+Remote_WakeUp Register after the PC Host has successfully
read the data from the device by the IN operation. The SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to ²0², the SIE will update the device address immediately after an address is written to the
Address+Remote_WakeUp Register. Default 0.
1
F0_ERR
R/W
This bit is used to indicate that some errors have occurred when accessing the
FIFO0.
This bit is set by SIE and cleared by F/W. Default 0
2
OUT
R/W
This bit is used to indicate there are OUT token (except the OUT zero length) token
has been received. The F/W clear the bit after the OUT data has been read. Also, this
bit will be clear by SIE after the next valid SETUP token is received.
3
IN
R
This bit is used to indicate the current USB receiving signal from PC Host is IN token.
4
NAK
R
This bit is used to indicate the SIE is transmitted NAK signal to Host in response to
PC Host IN or OUT token.
5
CRC_ERR
R/W
This bit indicated there are CRC error, PID error, Bit stuffing error (bit=1). Firmware
must to do something to save device keep alive. This bit is set by SIE and clear by
F/W.
6
EOT
R
End of transaction flag, normal status is ²1². If Suspend=²1² line & EOT=²0² indicated
something wrong in USB Interface. Firmware must to do something to save device
keep alive.
R/W
This bit is used to control whether the USB interrupt is output to the MCU in a NAK response to the PC Host IN or OUT token. Only for Endpoint0
1: has only USB interrupt, data is transmitted to the PC host or data is received from
the PC Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
7
MNI
SIES (45H) Register
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HT82D40REW
The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. The MISC will be cleared by the USB reset signal.
Bit No.
Label
R/W
Function
0
REQ
R/W
After setting the other status of the desired one in the MISC, endpoint FIFO can be
requested by setting this bit to ²1². After the task is completed, this bit must be
cleared to ²0².
1
TX
R/W
This bit defines the direction of data transferring between the MCU and endpoint
FIFO. When the TX is set to ²1², this means that the MCU wants to write data to the
endpoint FIFO. After the task is completed, this bit must be cleared to ²0² before terminating the request to represent the end of transferring. For a read action, this bit
has to be cleared to ²0² to represent that MCU wants to read data from the endpoint
FIFO and has to be set to ²1² after completion.
2
CLEAR
R/W
Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
4
3
SELP1
SELP0
R/W
Defines which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: reserved
5
SCMD
R/W
Used to show that the data in the endpoint FIFO is a SETUP command. This bit has
to be cleared by firmware. That is to say, even if the MCU is busy, the device will not
miss any SETUP commands from the host.
6
READY
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready for operation.
7
LEN0
R/W
Used to indicate that a 0-sized packet has been sent from a host to the MCU. This bit
should be cleared by firmware.
MISC (46H) Register
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which the address is
listed in the following table. After reading the current data, the next data will show after 2ms, this is used to check the
endpoint FIFO status and response to the MISC register, if the read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay 2ms, check 4BH®write* to FIFO1 register and
check not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO1 can be written or not
0AH®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH
Read 0-sized packet sequence form FIFO0
00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H
Write 0-sized packet sequence to FIFO1
0AH®0BH®delay 2ms, check 4BH®09H®08H
Note:
*: There is a 2ms time between 2 read actions or between 2 write actions.
Rev. 1.00
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HT82D40REW
SPI Serial Interface
The SPIR register is used to select SPI mode, clock polarity edge selection and SPI enable or disable selection.
The device includes one SPI Serial Interfaces. The SPI
interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each
other. The devices communicate using a master/slave
technique where only the single master device can initiate a data transfer. A simple four line signal bus is used
for all communication.
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will default to the condition below:
SPI Interface Communication
SPI_CPOL
SBEN
MLS
0
1
1
0
0
CSEN WCOL
0
0
TRF
0
To enable the bus, the SBEN bit should be set high,
then wait for data to be written to the SBDR (TXRX
buffer) register. For the Master Mode, after data has
been written to the SBDR (TXRX buffer) register then
transmission or reception will start automatically. When
all the data has been transferred, the TRF bit should be
set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted
out or data on SDI will be shifted in.
There are three registers for control of the SPI Interface.
These are the SBCR register which is the control register and the SBDR which is the data register and SPIR
register which is the SPI mode control register. The
SBCR register is used to setup the required setup parameters for the SPI bus and also used to store associated operating flags, while the SBDR register is used for
data storage.
0
M0
SPI Bus Enable/Disable
SPI Registers
Label
M1
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
Four lines are used for each function. These are, SDI Serial Data Input, SDO - Serial Data Output, SCK - Serial Clock and SCS - Slave Select. Note that the condition of the Slave Select line is conditioned by the CSEN
bit in the SBCR control register. If the CSEN bit is high
then the SCS line is active while if the bit is low then the
SCS line will be I/O mode. The accompanying timing diagram depicts the basic timing protocol of the SPI bus.
Bit No.
CKS
To Disable the SPI bus SCK, SDI, SDO, SCS should be
I/O mode.
R/W
Function
R/W
0: clock polarity falling (default falling)
1: clock polarity rising
1
SPI_MODE
R/W
0: SPI output the data in the rising edge(polarity=1) or falling edge (polarity=0);
SPI read data in the in the falling edge(polarity=1) or rising edge (polarity=0); (default)
1: SPI first output the data immediately after the SPI is enable. And SPI output
the data in the falling edge(polarity=1) or rising edge (polarity=0); SPI read data
in the in the rising edge(polarity=1) or falling edge (polarity=0)
2
SPI_CSEN
R/W
0: SPI_CSEN disable, SCS define as GPIO (default disable)
1: SPI_CSEN Enable , this bit is used to enable/disable software CSEN function
3
SPI_EN
R/W
This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode
0: I/O mode (default)
1: SPI mode
Reserved bit
R/W
Always 0
7~4
SPIR Register
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HT82D40REW
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
S D O
U
X
B u ffe r
S B E N
M L S
M
In te r n a l B a u d R a te C lo c k
S C K
a n d , s ta rt
E N
a n d , s ta rt
C lo c k P o la r ity
U
X
M
S D O
S D I
U
X
T R F
C 0 C 1 C 2
M a s te r o r S la v e
A N D
In te r n a l B u s y F la g
S B E N
a n d , s ta rt
E N
W r ite S B D R
W r ite S B D R
S B E N
W C O L F la g
E n a b le /D is a b le
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
SPI Block Diagram
Note:
WCOL: set by SPI cleared by users
CSEN: enable/disable chip selection function pin
master mode: 1/0 = with/without SCS output function
Slave mode: 1/0 = with/without SCS input control function
SBEN: enable/disable serial bus (0: initialise all status flags)
when SBEN=0, all status flags should be initialised
when SBEN=1, all SPI related function pins should stay at floating state
TRF: 1 = data transmitted or received, 0= data is transmitting or still not received
CPOL: I/O = clock polarity rising/falling edge: For SPIR Register.
If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0)
SCK is the serial clock timing.
Rev. 1.00
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HT82D40REW
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then go to the following step.
Step 7. Check the TRF bit or wait for an SPI serial
bus interrupt.
SPI Operation
All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
The CSEN bit in the SBCR register controls the SCS line
of the SPI interface. Setting this bit high, will enable the
SPI interface by allowing the SCS line to be active,
which can then be used to control the SPI inteface. If the
CSEN bit is low, the SCS line will be in a floating condition and can therefore not be used for control of the SPI
interface. The SBEN bit in the SBCR register must also
be high which will place the SDI line in a floating condition and the SDO line high. If in the Master Mode the
SCK line will be either high or low depending upon the
clock polarity control bit in SPIR register. If in the Slave
Mode the SCK line will be in a floating condition. If SBEN
is low then the bus will be disabled and SCS, SDI, SDO
and SCK will all be I/O mode.
Step 8. Read data from the SBDR register.
Step 9. Clear TRF.
Step10. Goto step 5.
· Slave Mode:
Step 1. The CKS bit has a don¢t care value in the
slave mode.
Step 2. Setup the M0 and M1 bits to 11 to select the
Slave Mode. The CKS bit is don¢t care.
Step 3. Setup the CSEN bit and setup the
MLS bit to choose if the data is MSB or LSB
first, this must be same as the Master device.
Step 4. Setup the SBEN bit in the SBCR
control register to enable the SPI interface.
Step 5. For write operations: write data to the
SBDR register, which will actually
place the data into the TXRX register, then
wait for the master clock and SCS signal.
After this goto Step 6.
For read operations: the data transferred in
on the SDI line will be stored in the
TXRX buffer until all the data has been
received at which point it will be latched into
the SBDR register.
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then goto the following step.
Step 7. Check the TRF bit or wait for an SPI serial bus
interrupt.
Step 8. Read data from the SBDR register.
Step 9. Clear TRF
Step10. step 5
In the Master Mode, the Master will always generate the
clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Mode:
· Master Mode
Step 1. Select the clock source using the CKS bit in
the SBCR control register
Step 2. Setup the M0 and M1 bits in the SBCR control
register to select the Master Mode and the
required Baud rate. Values of 00, 01 or 10 can
be selected.
Step 3. Setup the CSEN bit and setup the
MLS bit to choose if the data is MSB or LSB
first, this must be same as the Slave device.
Step 4. Setup the SBEN bit in the SBCR
control register to enable the SPI interface.
Step 5. For write operations: write the data to the
SBDR register, which will actually
place the data into the TXRX buffer. Then use
the SCK and SCS lines to output the data.
Goto to step 6.For read operations: the data
transferred in on the SDI line will be
stored in the TXRX buffer until all the data has
been received at which point it will be latched
into the SBDR register.
Rev. 1.00
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HT82D40REW
SPI Configuration Options and Status Control
One option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Some control in SPIR register.
The SPI_CPOL select the clock polarity of the SCK line . The SPI_MODE select SPI data output mode.
SPI include four pins , can share I/O mode status . The status control combine with four bits for SPIR and SBCR register. Include SPI_CSEN , SPI_EN for SPIR register and CSEN ,SBEN for SBCR register.
SPIR(22H)
SBCR(23H)
SPI_EN
SPI_CSEN
0
1
Note:
I/O Status
Note
SBEN
CSEN
SPI
SCS
x
x
x
I/O mode
I/O mode
x
0
x
I/O mode
I/O mode
1
0
1
x
SPI mode
I/O mode
SCS not Floating
1
1
1
0
SPI mode
I/O mode
SCS not Floating
1
1
1
1
SPI mode
SCS mode
The SPI enable, SCS, SDI,
SDO, SCK the internal
Pull-high function is invalid.
X: don¢t care
Error Detection
Programming Considerations
The WCOL bit in the SBCR register is provided to indicate errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application
program. This bit indicates a data collision has occurred
which happens if a write to the SBDR register takes
place during a data transfer operation and will prevent
the write operation from continuing. The bit will be set
high by the Serial Interface but has to be cleared by the
user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration
option.
When the device is placed into the Power Down Mode
note that data reception and transmission will continue.
The TRF bit is used to generate an interrupt when the
data has been transferred or received.
b 7
C K S
b 0
M 1
M 0
S B E N
M L S
C S E N W C O L T R F
S B C R
R e g is te r
T r a n s m itt/R e c e iv e fla g
0 : N o t c o m p le te
1 : T r a n s m is s io n /r e c e p tio n c o m p le te
W r ite c o llis io n b it
0 : C o llis io n fr e e
1 : C o llis io n d e te c te d
S e le c tio n s ig n a l e n a b le /d is a b le b it
0 : S C S flo a tin g fo r I/O m o d e
1 : E n a b le
M S B /L S B fir s t b it
0 : L S B s h ift fir s t
1 : M S B s h ift fir s t
S e r ia l B u s e n a b le /d is a b le b it
0 : D is a b le
1 : E n a b le
M a s te r /S la
M 1
M 0
0
0
0
1
1
0
1
1
v e /B a u d r a te b its
M a s
M a s
M a s
S la v
te r,
te r,
te r,
e m
b a u d ra te : fS
b a u d ra te : fS
b a u d ra te : fS
o d e
P I
P I/
P I/
4
1 6
C lo c k s o u r c e s e le c t b it
0 : f S P I= f S Y S / 2
1 : f S P I= f S Y S
SPI Interface Control Register
Rev. 1.00
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HT82D40REW
S P I_ m o d e = 0
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
S C S
(S P I_ C S E N = 1 )
(I/O
m o d e )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C K
(S P I_ C P O L = 1 )
S C K
(S P I_ C P O L = 0 )
S D I
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S P I_ m o d e = 1
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
S C S
(S P I_ C S E N = 1 )
(I/O
m o d e )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C K
(S P I_ C P O L = 1 )
S C K
(S P I_ C P O L = 0 )
S D I
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Bus Timing
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HT82D40REW
A
S P I T ra n s fe r
W r ite D a ta in to
S B D R
C le a r W C O L
M a s te r
M a s te r o r
S la v e
[M 1 , M 0 ]= 0 0 , 0 1 ,1 0
S e le c t c lo c k [C K S ]
S la v e
Y e s
W C O L = 1 ?
[M 1 , M 0 ]= 1 1
N o
N o
C o n fig u r e
C S E N a n d M L S
T r a n s m is s io n
C o m p le te d ?
(T R F = 1 ? )
Y e s
S B E N = 1
re a d d a ta fro m
S B D R
A
c le a r T R F
T ra n s fe r
F in is h e d ?
N o
Y e s
E N D
SPI Transfer Control Flowchart
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HT82D40REW
Configuration Options
No.
Options
1
PA0~PA7 Pull-high by bit (default Pull-high)
2
PB0~PB7 Pull-high by bit (default Pull-high)
3
PA output mode (CMOS/NMOS/PMOS) by bit (default CMOS)
4
PA0~PA7 wake-up by bit (default enable)
5
PB0~PB7 wake-up by bit (default disable)
6
LVR enable/disable (default enable)
7
WDT function : enable, disable for normal mode (default enable)
8
WDT clock source: 32K RC OSC; T1 (default T1)
9
CLRWDT instruction is by 1 or 2 (default 1 CLRWDT instruction)
10
TBHP enable /disable (default disable)
11
SPI_WCOL enable/disable (default disable)
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EEPROM Data Memory
The embedded EEPROM Data Memory is an I2C type
device and therefore operates using a two wire serial
bus. It has a capacity is 1K organized into a structure of
128 8-bit words and contains the information or data important for user.
· Stop condition
EEPROM Memory Interface
· Acknowledge
A low-to-high transition of SDA with SCL high will be
interpreted as a stop condition. After a read sequence
the stop command will place the EEPROM in a
standby power mode - refer to Start and Stop Definition Timing Diagram.
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
2
The two I C lines are the Serial Clock line, SCL, and the
Serial Data line SDA. The SDA and SCL lines are
bonded to external pins used to control the overall Read
and Write operations on the EEPROM Data Memory.
· Serial data - SDA
EEPROM Memory Addressing
The SDA line is the bidirectional EEPROM serial data
line which is controlled by the external device such as
other host MCU. The host MCU should configure its
relative pin connected to the SDA lines as input or output dynamically opposite to the data direction of the
EEPROM.
The EEPROM memory requires an 8-bit device address
word following a start condition to enable the EEPROM
for read or write operations. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits. Refer to the diagram showing
the Device Address. This is common to all the EEPROM
devices. The next three bits are all zero bits.
· Serial data - SCL
The SCL line is the EEPROM serial clock input line
which is controlled by the external device such as
other host MCU. The host MCU should configure its
relative pin connected to the SCL line as output pin.
The SCL input clocks data into the EEPROM on its
positive edge and clocks data out of the EEPROM on
its negative edge.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address is successful
then the EEPROM will output a zero as an ACK bit. If
not, the EEPROM will return to a standby state.
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted
as a START or STOP condition.
1
0
0
0
R /W
0
EEPROM Memory Operations
· Byte write
A high-to-low transition of SDA with SCL high will be
interpreted as a start condition which must precede
any other command - refer to the Start and Stop Definition Timing diagram.
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device
must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All
inputs are disabled during this write cycle and
EEPROM will not respond until the write cycle is completed.
D a ta a llo w e d
to c h a n g e
S D A
S C L
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
S to p
c o n d itio n
Start and Stop Definition Timing Diagram
D e v ic e a d d r e s s
S D A
1
D e v ic e A d d r e s s
· Start condition
S ta rt
c o n d itio n
0
W o rd a d d re s s
D A T A
S
S ta rt
P
R /W
A C K
A C K
A C K
S to p
Byte Write Timing
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HT82D40REW
· Acknowledge polling
the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address
data word is serially clocked out. The microcontroller
should respond a No ACK - High - signal and a following stop condition.
To maximize bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
· Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
No ACK signal - high - followed by a stop condition.
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
· Sequential read
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with
an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address
limit is reached, the data word address will roll over
and the sequential read continues. The sequential
read operation is terminated when the microcontroller
responds with a No ACK signal - high - followed by a
stop condition.
N o
Y e s
N e x t O p e r a tio n
Acknowledge Polling Flow
· Read operations
The data EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
EEPROM Memory Power-down Considerations
The MCU and EEPROM Memory are powered down
independently of each other. The method of powering
down the MCU is covered in the previous MCU section of the datasheet. The MCU must be powered
down after the read and write operations of the
EEPROM Memory have been completed. The
method of the read or write operation of the EEPROM
Memory is mentioned in the previous EEPROM Memory Operations section of this datasheet.
· Current address read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the EEPROM power is
maintained. The address will roll over during a read
from the last byte of the last memory page to the first
byte of the first page. Once the device address with
D e v ic e a d d r e s s
S D A
D A T A
S to p
S
P
S ta rt
A C K
N o A C K
Current Read Timing
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A
D e v ic e a d d r e s s
S ta rt
A C K
S ta rt
A C K
S to p
P
S
S
A C K
N o A C K
Random Read Timing
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
S to p
P
S
S ta rt
D A T A n + x
A C K
A C K
N o A C K
Sequential Read Timing
Rev. 1.00
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April 1, 2010
HT82D40REW
Data EEPROM Timing Diagram
tf
tr
tL
S C L
tS
S D A
U
:S
tH
T A
tS
tH
IG H
D
O W
:S
T A
tH
D
:D
A T
tS
:D
U
A T
tS
U
tB
U F
:S
T O
P
tA
S D A
A
V a lid
O U T
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
S to p
C o n d itio n
Note:
R
S ta rt
C o n d itio n
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
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HT82D40REW
RF Transceiver
RF Transceiver Features
RF/Analog Circuit Features
MAC/Baseband Features
· ISM band 2.400GHz~2.495GHz operation
· Automatic ACK response and FCS check
· -90dBm/-80dBm sensitivity @ 250k/1M bps
· 62-byte TX FIFO
(Packet error rate under 0.1%)
· Dual 64-byte RX FIFOs
· 3dBm maximum input level
· Various power saving modes
· -3dBm~0dBm typical output power
· Simple four-wire SPI interface
· Differential RF input/output and integrated
TX/RX switch
RF Transceiver Applications
· Integrated low phase noise VCO,
· Home/Building/Factory Automation
frequency synthesizer and PLL loop filter
· Integrated 32MHz oscillator drive
· PC Peripheral
· Digital VCO and filter calibration
· RF Remote Controller
· 18mA in RX and 15mA in TX mode
· Consumer Electronics
· 2.4mA deep sleep mode, 0.1mA power down
· 2-way Medium-Data-Rate Applications
· 1M bps turbo mode supported
· PLL lock-on time less than 130ms
RF Transceiver Overview
The device contains a 2.4GHz RF transceiver with a
Baseband/MAC block. The RF transceiver can be controlled by the MCU for low data rate applications such as
consumer electronics, PC peripherals, toys, industrial
automations, etc. For medium data rate applications like
wireless voice and image transmission, the RF transceiver provides 1M bps turbo mode.
RF Transceiver Block Diagram
RF Transceiver
SI
Lower MAC
SO
SCLK
SEN
RF_P
Interfacing
INT
PHY
Power
Management
Memory
RST
RF_N
VDD
GND
GPIO0~GPIO2
Rev. 1.00
XTAL_P XTAL_N
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HT82D40REW
RF Transceiver D.C. Characteristics
Symbol
ITX
VDD=3V, Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
RF Transceiver TX Active. At 0 dBm output power
DC-DC
Off*
¾
21
30
mA
RF Transceiver RX Active in Normal Mode (250 Kbps)
DC-DC
Off*
¾
19
28
mA
RF Transceiver RX Active in Turbo Mode (1M bps)
DC-DC
Off*
¾
21
30
mA
IRX
ISTB
RF Transceiver in STANDBY mode. Partial 32MHz clock and Sleep
clock remains active. RF/MAC/BB, system clock shutdown.
¾
60
80
mA
IDS
RF Transceiver in DEEP_SLEEP mode. Power to digital circuit remains active to retain Registers and FIFOs. All the other power is
shutdown.
¾
3.2
10.0
mA
IPD
RF Transceiver in POWER_DOWN mode. Minimum wake-up circuit remains active. All power is shutdown. Register and FIFO data
are not retained.
¾
0.6
2.0
mA
Note:
²*² The operating current ITX or IRX listed here is the additional current consumed when the RF Transceiver operates in Active TX mode or Active RX mode. If the RF Transceiver is active, either ITX or IRX should be added
to calculate the relevant operating current of the device for different operating mode. To calculate the standby
current for the whole device, the standby current shown above including ISTB, IDS and IPD should be taken into
account for different Power Saving Mode.
RF Transceiver A.C. Characteristics
VDD=3V, Ta=25°C, LO frequency=2.445GHz, DC-DC Off
Receiver
Parameters
Test Conditions
Min.
Typ.
Max.
Unit
2.400
¾
2.495
GHz
dBm
RF Input Frequency
¾
At antenna input with O-QPSK 250 Kbps
signal, PER £ 0.1%
1 Mbps
¾
-90
RF Sensitivity
¾
¾
-80
¾
dBm
Maximum RF Input
¾
¾
5
¾
dBm
Adjacent Channel Rejection
@ ±5MHz, 250 Kbps
(-82 dBm + 20 dB = -62 dBm)
¾
20
-62
¾
dBc
dBm
Alternative Channel Rejection
@ ±10 MHz, 250Kbps
(-82 dBm + 40 dB = -42 dBm)
¾
40
-42
¾
dBc
dBm
LO Leakage
Measured at the balun matching the
network with the input frequency at
2.4~2.5GHz
¾
-60
¾
dBm
Noise figure
(Including matching)
¾
¾
8
¾
dB
Rev. 1.00
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HT82D40REW
Transmitter
VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off
Parameters
Test Conditions
Min.
Typ.
Max.
Unit
2.400
¾
2.495
GHz
RF carrier frequency
¾
Maximum RF output power
At 0 dBm output power setting
-3
0
¾
dBm
RF output power Accuracy
¾
¾
¾
±4
dBm
RF output power control range
¾
¾
36
¾
dB
TX gain control resolution
¾
0.1
¾
0.5
dB
Carrier suppression
¾
¾
-30
¾
dBc
¾
¾
-30
dBm
¾
¾
-20
dBc
¾
30
¾
%
TX spectrum mask for O-QPSK signal
Offset frequency > 3.5MHz
At 0 dBm output power
¾
TX EVM
Synthesizer
VDD=3V, Ta=25°C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off
Parameters
Test Conditions
Min.
Typ.
Max.
Unit
PLL Stable Time
¾
¾
130
¾
ms
PLL Programming resolution
¾
¾
1
¾
MHz
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HT82D40REW
RF Transceiver Power-on and Reset Characteristics
the external component count and the power consumption. The Baseband/MAC block provides the hardware
architecture for both MAC and PHY layers. It mainly
consists of TX/RX control and digital signal processing
module. Interconnection between the MCU and the RF
Transceiver is implemented by internally connecting the
MCU Master SPI interface to the RF Transceiver Slave
SPI interface. All data transmissions and receptions between MCU and RF Transceiver including RF Transce i ve r co m m a n d s a r e co n d u ct e d a l o n g t h i s
interconnected SPI interface. The RF Transceiver function control is executed by the MCU using its SPI Master
serial interface. The RF Transceiver contains its own independent interrupt which can be used to indicate when
a wake-up event occurs, an available packet reception
occurs or when a packet transmission has successfully
terminated or retransmission is timed out.
The RF Transceiver has built-in power-on reset (POR)
circuit which automatically resets all digital registers
when the power is turned on. The 32MHz oscillator circuit starts to lock frequency of the right clock after
power-on. The whole process takes 3ms for a clock circuit to become stable and completes the power-on reset. It is highly recommended that the user waits at least
3ms before starting to access the RF Transceiver.
The RF Transceiver hardware reset signal (warm start)
named RST is controlled by MCU I/O pin and internally
pulled high with 33kW resistor connected to VCC within
the RF Transceiver. The RF Transceiver will hold in reset state around 20ms after RST signal is released from
the low state.
RF Transceiver Crystal Parameter Specifications
RF Transceiver Internal Connection
The RF Transceiver utilizes external 32MHz crystal to
generate the oscillation for RF Transceiver input clock.
The associated pins are XTAL_P and XTAL_N. The table below lists the parameters of the crystal oscillator
used in the RF Transceiver. To operate the RF Transceiver properly, user has to select the crystal which
meets the following requirements.
Parameters
Min.
Crystal Frequency
Frequency Offset
-40
Typ.
Max.
Unit
32
¾
MHz
¾
40
ppm
Load Capacitance
¾
¾
10
pF
Recovery Time
¾
¾
180
ms
In addition to the RF Transceiver external pins described above there are other MCU to RF Transceiver
interconnecting lines that are described in the above RF
Transceiver Pin Description table. Note that these lines
are internal to the device and are not bonded to external
pins.
V
V
D D
V D D
M C U
32MHz crystal oscillator recovery time highly depends
on the shunt capacitance of 32MHz crystal. The lower
shunt capacitance value makes the recovery time
shorter. This recovery time 180ms is measured with
32MHz crystal by NDK NX3225SA.
V S S
C C
V D D _ R F
S C K
S C L K
S D O
S I
S D I
X T A L _ P
X T A L _ N
S O
S C S
S E N
IN T
IN T
I/O
R S T
R F _ P
R F _ N
R F
T r a n s c e iv e r
G P IO 0
G P IO 1
G N D
G P IO 2
RF Transceiver Functional Description
The RF transceiver integrates receiver, transmitter, voltage-controlled oscillator (VCO), and phase-locked loop
(PLL). It uses advanced radio architecture to minimize
Rev. 1.00
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HT82D40REW
MCU to RF Transceiver Internal Line Descriptions
Pin Name
Type
Description
SCLK
I
Internal RF Transceiver Slave SPI Serial Clock Input Signal.
Internally connected to the MCU Master SPI SCK output signal.
SI
I
Internal RF Transceiver Slave SPI Serial Data Input Signal.
Internally connected to the MCU Master SPI SDO output signal.
SO
O
Internal RF Transceiver Slave SPI Serial Data Output Signal.
Internally connected to the MCU Master SPI SDI input signal.
SEN
I
Internal RF Transceiver Slave SPI Serial interface Enable Input Signal.
Internally connected to the MCU Master SPI SCS output signal.
INT
I
Internal RF Transceiver Interrupt Output Signal.
Internally connected to the MCU INT input signal.
RST
I
Internal RF Transceiver global hardware reset input signal, active low.
Internally connected to the MCU I/O pin configured as output type.
WAKE
I
Internal RF Transceiver Wake-up trigger input signal.
Internally connected to the MCU I/O pin configured as output type.
Notes: (1) The pin descriptions for all external pins except the RF Transceiver pins listed in the above table are
described in the preceding MCU section.
(2) The INT, RSTB and WAKE lines are internally connected to the MCU I/O pins PB0, PB1 and PB2
respectively while the SO, SI, SCLK and SEN lines are internal connected to the MCU I/O pins PB3,
PB4, PB5 and PB6 respectively.
The RF Transceiver is composed of several functional blocks named Interfacing block, Lower MAC block, Memory
block, Power Management block and PHY block. The detailed functions of the functional blocks are described in the
following sections.
RF Transceiver PHY Block
The key features and the block diagram of the PHY layer in RF Transceiver are listed as below.
· Operating frequency range is from 2400MHz to 2495MHz.
· It uses Offset QPSK (OQPSK) modulation to transmit data at 250k/1M bps.
· Direct Sequence Spreading Spectrum (DSSS) is used in baseband algorithm to increase the SNR.
M ix e r
L im itin g
A m p lifie r
P o ly p h a s e
F ilte r
A D C
L N A
A D C
B a s e b a n d
C ir c u it
P L L
R F IO
T o L o w
M A C B lo c k
D A C
T o L o w e r
M A C B lo c k
P A
D A C
PHY Block Architecture
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HT82D40REW
and command transfer between the network and the
physical layers PHY.
The RF Transceiver uses a fractional-N Phase-Locked
Loop (PLL) as frequency synthesizer. Therefore, 1MHz
channel spacing is supported and any integer carrier
frequency between 2400MHz to 2495MHz can be used.
The loop filters of PLL are integrated into the RF Transceiver except one external capacitor which should be
connected between the PLL loop filter external pin and
the ground. In order to keep the PLL stable, the board
layout around the PLL loop filter external capacitor pin
should be carefully designed to avoid EMI. The recommended value of this external capacitor is 100pF.
L o w e r M A C
M e m o ry
P H Y
Lower MAC Block Diagram
MAC Frame Format
· Data Frame
The address field contains the broadcast address
(0xFFFF-FFFFH) or destination address. The bit 0 of
frame control (FC) field is used for Ack-Request which
specifies whether an acknowledgement is required
from the recipient device. If the bit is ²1², the recipient
device shall send an acknowledgement frame back
after determining that the received frame is valid. The
bit 1 of FC field is ²0² for data frame. The length of
payload field is variable from 0 to 56 bytes. The frame
check sequence (FCS) is calculated over the address
field, FC field and the payload. The polynomial is degree 16:
The packet includes a 6 bytes PHY header and a 7~63
bytes PHY payload. The 6 bytes PHY header includes 4
bytes of preamble, 1 byte of start-of-frame delimiter
(SFD) and 1 byte of payload length. Preamble and SFD
are used for receiver packet detection and synchronization. The Frame Length field specifies the length of the
PHY payload field. The valid length can be from 7 to 63
bytes. The frame format is shown as below:
1 b y te
1 b y te
7 ~ 6 3 b y te s
P r e a m b le
S ta rt o f F ra m e
D e lim ite r
F ra m e
L e n g th
P H Y P a y lo a d
In te r fa c in g
T X M A C
Under 1M bps turbo mode, user can use the same program settings of MAC and all MAC functions are remained the same. Compare with 250k bps mode, in 1M
bps mode, signal bandwidth is extended to 8MHz.
4 b y te s
R X M A C
G
1 6
(x ) = x
1 6
+ x
1 2
+ x
5
+ 1
· Acknowledgement Frame
P H Y H e a d e r
The length of acknowledgement frame is always 5
bytes. Bit 1 of FC field is 1 for ACK frame. The payload
field, containing user information of acknowledgement frame, can be configured by SREG0x03 and
SREG0x04. The FCS is calculated over the FCS of
the received packet, FC field and the payload field.
The polynomial is degree 16:
PHY Layer Frame Format
RF Transceiver Low MAC Block
The RF Transceiver MAC provides plenty of hardware-assisted features to relieve the host MCU power
requirement. Besides providing reliable wireless packet
transactions between two nodes, it also handles data
G
1 6
(x ) = x
1 6
+ x
1 2
+ x
5
+ 1
Data Frame
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HT82D40REW
Acknowledgement Frame
TXMAC
Meanwhile, the frame length field of PHY header and
PHY payload will be stored in RXFIFO. Unqualified
packets are skipped.
When the TXFIFO is triggered, the TXMAC gets the
data from TXFIFO to generate a 16-bit FCS and sends
the packet to the PHY layer of the TX immediately. If
necessary, TXMAC handles the retransmission, when
the acknowledgement packet is not received. The block
diagram of a TXMAC is shown below.
RXFIFO0 and RXFIFO1 are mapped into the 64-byte
memory space from 0x300H to 0x33FH as Ping-Pong
FIFOs. If Ping-Pong RX mode is enabled by SREG0x34
[0], RXMAC automatically switches between RXFIFO0
and RXFIFO1 to store incoming frame whenever a new
packet comes. When the MCU host reads the long address memory 0x300H, the RXMAC will change the flag
of SREG0x34 [1] automatically. For manually controlled
RX operation, if the value of the flag SREG0x34 [1] is
²0², the RXFIFO0 shall be read. Otherwise, the
RXFIFO1 shall be read.
RXMAC
The RX PHY of the RF Transceiver filters signals and
tracks the synchronization symbols. If a packet passes
the filtering, RXMAC performs frame type parsing, address recognition and FCS checking. If the destination
address is broadcast address or matches its own identity, configured by SREG0x05 to SREG0x08, and the
FCS check is passed, an interrupt is issued at
SREG0x31 [3] to indicate a valid packet is received.
TXMAC Block Diagram
RXMAC Block Diagram
Rev. 1.00
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HT82D40REW
If an acknowledgement is requested and the replied
ACK frame is not received, the transmitter automatically
resends the packet until the maximum retransmission
times, specified in SREG0x1B [7:4], are reached. To utilize the function properly, the corresponding registers of
both transmitting and receiving sides need to be set correctly.
In the above diagram, the current status of each frame is
represented in SREG0x30. SREG0x30 [7] means
²RXFIFO full² indicating the two RXFIFOs are occupied.
If the MCU host cannot read the RXFIFO in time, the
value of SREG0x30 [7] will be set to ²1². Once the MCU
host read the RXFIFO, the value of the SREG0x30 [7]
will be set to ²0² automatically.
· Auto-retransmission on TX Side
The contents of the RXFIFO can be flushed only by the
following three ways: (1) the MCU host reads length
field of RXFIFO and the last byte of the packet, (2) the
host issues an RX flush, and (3) the software reset by
SREG0x2A [0]. Note that RXFIFO is ready to receive
next packet and all the data in RFIFO will be overwritten
after RXFIFO flushed.
To automatically retransmit a packet when an ACK is
not received, SREG0x1B [2] is required to be set to
²1².
· Auto-acknowledgement on RX Side
To automatically reply an ACK packet when
Ack-Request bit is set to ²1², SREG0x00 [5] should be
set to ²0².
Auto Acknowledgement
The RXMAC supports automatically acknowledgement.
If and only if the packet is successfully received and an
Ack-Request bit, Bit 0, in the FC field of the received
packet is set, RXMAC informs TXMAC to send an acknowledgement packet automatically. User should write
the FC field correctly into the TX FIFO.
Rev. 1.00
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HT82D40REW
RF Transceiver Memory Block
· Short address register (6-bit short addressing mode
The Memory Block of the RF Transceiver is implemented by the SRAM. As the following Memory Block
diagram shown, the RF Transceiver Memory is composed of registers and FIFOs, which can be accessed
by the SPI interface. They are categorized into two kinds
of address spaces. One is the short address space; the
other is the long address space.
register, total 64 registers)
· Long address register (10-bit long addressing mode
register, total 128 registers)
Short address registers are accessed by short addressing mode with valid addresses ranging from 0x00H to
0x3FH. Long address registers are accessed by long
addressing mode with valid addresses ranging from
0x200H to 0x27FH. Short registers are accessed faster
than long registers. Please refer to the following SPI Interface section for detailed addressing rules via SPI interface.
Registers
Registers provide control bits and status flags for the RF
Transceiver operations, including transmission, reception, interrupt control, MAC/baseband/RF parameter
settings, etc. The registers are divided into two types according to addressing mode as listed below.
Memory Space Diagram
Memory Block Diagram
Rev. 1.00
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HT82D40REW
Short Address Registers
Legend: r=reserved
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x00
RXMCR
r
r
NOACKRSP
r
r
r
r
r
0000 0000
0x03
AUINFL
AUINF7
AUINF6
AUINF5
AUINF4
AUINF3
AUINF2
AUINF1
AUINF0
0000 0000
0x04
AUINFH
AUINF15
AUINF14
AUINF13
AUINF12
AUINF11
AUINF10
AUINF9
AUINF8
0000 0000
0x05
DADR_0
DADR[7:0]
0000 0000
0x06
DADR_1
DADR[15:8]
0000 0000
0x07
DADR_2
DADR[23:16]
0000 0000
0x08
DADR_3
0x0D
RXFLUSH
r
WAKEPOL
WAKEPAD
r
DADR[31:24]
r
PTX
r
RXFLUSH
0110 0000
0000 0000
0x12
ACKTO
r
MATOP6
MATOP5
MATOP4
MATOP3
MATOP2
MATOP1
MATOP0
0011 1001
0x17
PACON
r
r
r
PAONTS3
PAONTS2
PAONTS1
PAONTS0
r
0000 0010
0x18
TXCON
r
r
TXONTS3
TXONTS2
TXONTS1
TXONTS0
r
r
1000 1000
0x1B
TXTRIG
TXRTYN3
TXRTYN2
TXRTYN1
TXRTYN0
r
TXACKREQ
r
TXTRIG
0011 0000
0x22
WAKECTL
IMMWAKE
REGWAKE
r
r
r
r
r
r
0100 0000
0x24
TXSR
TXRETRY3
TXRETRY2
TXRETRY1
TXRETRY0
r
r
r
TXNS
0000 0000
0x26
GATECLK
r
r
SPISYNC
r
r
ENTXM
r
r
0000 0000
0x2A
SOFTRST
r
r
r
r
r
r
RSTBB
RSTMAC
0000 0000
0x2E
TXPEMISP
TXPET3
TXPET2
TXPET1
TXPET0
r
r
r
r
0111 0101
0x30
RXSR
RXFFFULL
WRFF1
r
r
r
r
0000 0000
0x31
ISRSTS
r
WAKEIF
r
r
RXIF
r
r
TXNIF
0000 0000
0x32
INTMSK
r
WAKEMSK
r
r
RXMSK
r
r
TXNMSK
1111 1111
0x34
BATRXF
r
r
BATIND
r
r
r
RDFF1
RXFIFO2
0000 0000
0x35
SLPACK
SLPACK
0x36
RFCTL
r
r
r
0x38
BBREG0
r
r
r
RXFFOVFL RXCRCERR
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
WAKECNT8 WAKECNT7
r
r
0000 0000
RFRST
r
r
0000 0000
r
r
TURBO
1000 0001
Short Address Registers List
Rev. 1.00
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Long Address Registers
Legend: r=reserved
Addr.
File
Name
Bit 7
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x200
RFCTRL0
CHANNEL3
CHANNEL2
r
r
r
r
0000 0001
0x201
RFCTRL1
r
r
r
0x202
RFCTRL2
r
RXFC0-1
RXFC0-0
r
r
r
VCORX1
VCORX0
0000 0001
r
r
r
r
r
1000 0100
0x203
RFCTRL3
TXGB4
TXGB3
TXGB2
TXGB1
TXGB0
r
r
r
0000 0000
0x204
RFCTRL4
r
r
r
r
r
RXFCO
RXD2CO1
RXD2CO0
0000 0000
0x205
RFCTRL5
BATTH3
BATTH2
BATTH1
BATTH0
r
r
r
r
0000 0000
0x206
0x207
RFCTRL6
TXFBW1
TXFBW0
32MXCO1
32MXCO0
BATEN
r
r
r
1111 0000
RFCTRL7
r
r
r
RXFC2
r
r
r
r
0000 0000
0x208
RFCTRL8
r
TXD2CO0
r
r
r
r
r
r
0000 1100
0x209
SLPCAL_0
SLPCAL7
SLPCAL6
SLPCAL5
SLPCAL4
SLPCAL3
SLPCAL2
SLPCAL1
SLPCAL0
0000 0000
0x20A
SLPCAL_1
SLPCAL15
SLPCAL14
SLPCAL13
SLPCAL12
SLPCAL11
SLPCAL10
SLPCAL9
SLPCAL8
0000 0000
0x20B
SLPCAL_2 SLPCALRDY
r
r
SLPCALEN
SLPCAL19
SLPCAL18
SLPCAL17
SLPCAL16
0000 0000
0x211
IRQCTRL
r
r
r
r
r
r
IRQCTRL
r
0000 0000
0x22F
TESTMODE
MPSPI
r
r
r
r
0x23D
GPIODIR
r
r
0x23E
GPIO
r
r
0x250
RFCTRL50
r
0x251
RFCTRL51
DCOPC5
0x252
RFCTRL52
SLCTRL6
0x253
RFCTRL53
0x254
Bit 5
Bit 4
CHANNEL1 CHANNEL0
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0
TESTMODE2 TESTMODE1 TESTMODE0 0010 1000
GPIO2DIR
GPIO1DIR
GPIO0DIR
0011 1111
0000 0000
r
r
r
GPIO2
GPIO1
GPIO0
r
r
DCPOC
DCOPC3
DCOPC2
DCOPC1
DCOPC0
0000 0000
DCOPC4
r
r
r
r
r
r
0000 0000
SLCTRL5
SLCTRL4
SLCTRL3
SLCTRL2
SLCTRL1
SLCTRL0
32MXCTRL
1111 1111
r
FIFOPS
DIGITALPS
P32MXE
PACEN2
PACTRL2-2
PACTRL2-1
PACTRL2-0
0000 0000
RFCTRL54
1MCSEN
1MFRCH6
1MFRCH5
1MFRCH4
1MFRCH3
1MFRCH2
1MFRCH1
1MFRCH0
0000 0000
0x259
RFCTRL59
r
r
r
r
r
r
r
PLLOPT3
0000 0001
0x273
RFCTRL73 VCOTXOPT1 VCOTXOPT0
r
r
PLLOPT2
PLLOPT1
PLLOPT0
r
0000 0000
0x274
RFCTRL74
PACEN0
PACEN1
PACTRL1-2
PACTRL1-1
PACTRL1-0
1100 1010
0x275
RFCTRL75
r
r
r
r
SCLKOPT3
SCLKOPT2
SCLKOPT1
SCLKOPT0
0001 0101
0x276
RFCTRL76
r
r
r
r
r
SCLKOPT6
SCLKOPT5
SCLKOPT4
0000 0001
0x277
RFCTRL77
r
r
SLPSEL1
SLPSEL0
SLPVCTRL1 SLPVCTRL0
SLPVSEL1
SLPVSEL0
0000 1000
Rev. 1.00
PACTRL0-2 PACTRL0-1 PACTRL0-0
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HT82D40REW
FIFOs
The RF Transceiver has four power saving modes that
will be further described in Power Saving Modes Section. For ultra low-power operation, Power-down mode
is available which consumes around 0.1mA while the RF
Transceiver is powered down. All data stored in registers and FIFOs will be lost under Power-down mode. In
this mode, The RF Transceiver is able to wake up by a
wake-up input signal. Except Power down mode, the
data in the registers/FIFOs are retained during the other
power saving modes.
FIFOs serve as the temporary data buffers for data
transmission and reception. Each FIFO holds only one
packet at a time. TXFIFO, the transmission FIFO, is
composed of 62-byte FIFO. RX FIFO, the receiving
FIFO, is composed of two 64-byte FIFOs.
· TX FIFO - (62 bytes)
The TXMAC gets the to-be transmitted data from the
62-byte TXFIFO. The memory space of TXFIFO is
from ²0x001² to ²0x03E² and contains a FL field, address field, FC field and payload field. The FL field indicates the length of the address field, FC field and the
payload field. The valid value of frame length is from 5
to 61 bytes.
Power Supply Scheme
The table below lists the recommended values of the external bypass capacitors for each power pin of the RF
Transceiver. For the power pins VDD_RF1 and
VDD_3V, an extra bypass capacitor is needed for the
decoupling purpose while the rest of the power pins require only one bypass capacitor. The path length between the bypass capacitors to each pin should be
made as short as possible.
· RX FIFO - RXFIFO0 (64 bytes) and
RXFIFO1 (64 bytes)
A RXFIFO is composed of two 64-byte FIFOs
(RXFIFO0 and RXFIFO1) to store the incoming
packet. Each of them is designed to store one packet
at a time. RXFIFO contains a FL field, address field,
FC field, payload field and FCS field. The memory
space of RXFIFO is from ²0x300² to ²0x33F². The FL
field, which is extracted from the PHY header, indicates the length of the address field, FC field, the payload field and FCS field. The valid value of frame
length is from 7 to 63 bytes. The value of the FL field of
PHY header is calculated by adding 2, the length of
FCS field of MAC frame, and the above mentioned
value up.
RF Transceiver Power Management
Block
Almost all wireless sensor network applications require
low-power consumption to lengthen battery life. Typical
battery-powered device is required to be operated over
years without replacing its battery. The RF Transceiver
achieves low active current consumption of both the digital and the RF/analog circuits by controlling the supply
voltage and using low-power architecture.
Pin Name
Bypass
Capacitor 1
Bypass
Capacitor 2
VDD_RF1
47pF
10nF
VDD_RF2
47pF
VDD_D
10nF
VDD_3V
10mF
VDD_A
47pF
VDD_PLL
47pF
VDD_CP
10nF
10nF
Recommended External Bypass Capacitors
TXFIFO Format
RXFIFO Format
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HT82D40REW
DC-DC Converter
· POWER_DOWN: All power is shutdown. Registers
There are two ways to supply power to the RF Transceiver. One is through the on-chip DC-DC converter and
the other is without the DC-DC converter. With DC-DC
converter, the RF Transceiver consumes lower current.
With the DC-DC converter, power pins including
VDD_RF1, VDD_RF2, VDD_D, VDD_A, VDD_PLL and
VDD_CP should be hardwired to the DC-DC converter
output, pin VDD_2V2 of the RF Transceiver. Without
DC-DC converter, all the power pins should be directly
hardwired to the external supplied voltage.
and FIFOs data are not retained, a wake-up input signal can wake up the RF Transceiver.
IDLE mode is rarely used because the device should at
least always turns on its RX circuit to capture the on-air
RF signals. The only difference between STANDBY
mode and DEEP_SLEEP mode is the power status of
the sleep clock. To wake the RF Transceiver up, the
MCU host has to control the time of sleep process.
The power management control is used for the low
power operation of MAC and baseband modules. It
manages to turn on and off the 32MHz clock when the
RF Transceiver goes into power saving mode. By turning off the 32MHz clock, the MAC and baseband circuits
become inactive regardless whether their power supplies exist or not. All the digital modules are clock-gated
automatically. That means only when a module is functioning, its clock would then be turned on. This approach
efficiently decreases certain amount of the current consumption.
For this device the on-chip DC-DC converter is not
used. User can set LREG0x250 [4] to ¢0¢ and
LREG0x273 to ²0x4E² to bypass the DC-DC converter.
When the DC-DC converter is bypassed, pins
VDD_2V2 and VDD_3V are shorted internally.
Battery Monitor
The RF Transceiver provides a function to monitor the
RF Transceiver supplied voltage. A 4-bit voltage threshold can be configured so that when the supplied voltage
is lower than the threshold, the system will be notified.
For battery monitor function, please refer to the Section
named Battery Monitor Operations.
RF Transceiver Interfacing Block
The interfacing block mainly includes three parts named
SPI interface, GPIO and Interrupt signal. Each of them
is described as followings.
Power Saving Modes
SPI Interface
The RF Transceiver power modes are classified into the
following four modes:
The MCU communicates with the RF Transceiver via an
internal SPI interface to read/write the control registers
and FIFOs. The SPI interface connected to the MCU
SPI master in the RF Transceiver has the following features:
· IDLE: RF circuit off. The regulator, oscillator, and digi-
tal circuits are on.
· STANDBY: RF/MAC/BB shutdown with sleep and
32MHz clocks remain active
· A 4-line slave SPI interface composed of: SEN (SPI
· DEEP_SLEEP: All power is shutdown except the
enable), SCLK (SPI Clock), SI (Serial Data Input) and
SO (Serial Data Output).
power to the digital circuits and registers and FIFOs
data are retained.
· Most significant bit (MSB) of all addresses and data
transfers on the SPI interface is done first.
Block Diagram of Voltage Regulators with DC-DC Converter On/Bypass
Rev. 1.00
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April 1, 2010
HT82D40REW
¨
SPI Addressing Format
MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for
short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator.
SPI Addressing Format
¨
SPI Characteristics
Parameter
Symbol
Min.
Max.
Unit
fSCLK
¾
5
MHz
SCLK low pulse duration
tCL
100
¾
ns
The minimum time SCLK must be low.
SCLK high pulse duration
tCH
100
¾
ns
The minimum time SCLK must be high.
SEN setup time
tSP
100
¾
ns
The minimum time SEN must be low before the first
positive edge of SCLK.
SEN hold time
tNS
100
¾
ns
The minimum time SEN must be held low after the
last negative edge of SCLK.
SI setup
tSD
25
¾
ns
The minimum time data must be ready at SI, before
the positive edge of SCLK
SI hold time
tHD
25
¾
ns
The minimum time data must be held at SI, after the
positive edge of SCLK.
Rise time
tRISE
¾
25
ns
The maximum rise time for SCLK and SEN.
Fall time
tFALL
¾
25
ns
The maximum fall time for SCLK and SEN.
SCLK, clock frequency
¨
Conditions
SPI Timing Diagram
The following figures show the timing diagrams for the short and long addressing mode respectively. The MCU SPI
master will initiate a read or write operation by asserting the interface enable signal SEN to low, toggling SCLK and
sent the address field by SI. The interface enable signal SEN should be high when a transaction is completed.
tSP
tSD
tHD
tCH
tNS
tCL
SCLK
SEN
read short address data
SI
0 A6 A5 A4 A3 A2 A1 0
SO
X
0 A6 A5 A4 A3 A2 A1 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
X
DR7 DR6 DR5
write short address data
SI
0 A6 A5 A4 A3 A2 A1 1
Dw7 Dw6 Dw5 Dw4 Dw3 Dw2 Dw1 Dw0
0 A6 A5 A4 A3 A2 A1 1
Dw7 Dw6 Dw5
SO
Timing Diagram of Short Addressing Mode
Rev. 1.00
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April 1, 2010
HT82D40REW
The SPI burst mode is provided for the access of long address memory space on a continuous basis. If SEN does
not go high after the 8-bit write data and the SCLK continuously toggles, the followed 8-bit write data is written to
the next address field. Same for the read access, the data of the next address will be read. The SPI burst mode is
only available for the long-address mode.
tSP
tSD
tHD
tCH
tNS
tCL
SCLK
SEN
read long address data
SI
1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 0
X
X
X
X
X
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR7 DR6 DR5 DR4
SO
write long address data
SI
1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 1
X
X
X
X
Dw7 Dw6 Dw5 Dw4 Dw3 Dw2 Dw1 Dw0 Dw7 Dw6 Dw5 Dw4
SO
Timing Diagram of Long Addressing Mode
GPIO
interrupt mask in SREG0x32 is clear (i.e. equals 0), an
interrupt will be issued on the interrupt output pin INT. If
the corresponding interrupt mask is set to 1 (masked),
no interrupt will be issued, but the status is still present.
Whenever the SREG0x31 register is read, the interrupt
and the status are cleared. The three interrupt events
are described as below:
The RF Transceiver has 3 digital GPIO pins. Each GPIO
pins can be configured as input or output by
LREG0x23D respectively. When being configured as an
output pad, the driving capability is 4mA for GPIO0 and
1mA for GPIO1 and GPIO2. The status of these pins
can be configured or read by LREG0x23E.
· Wake-up Alert Interrupt (WAKEIF): Each time a
To benefit wide rang applications, GPIO0, GPIO1 and
GPIO2 can be configured to control the external Power
Amplifier (P.A.) and RF switch according to the current
RF state automatically. Please refer to the following section named ²External Power Amplifier Configuration² for
details.
wake-up event happens the RF Transceiver issues
the interrupt event.
· Packet Received Interrupt (RXIF): This interrupt is is-
sued when an available packet is received in the
RXFIFO. An available packet means that it passes a
RXMAC filter, which includes frame type identifying,
address filtering and FCS check.
Interrupt Signal
· TX FIFO Release Interrupt (TXNIF): This interrupt can
The RF Transceiver provides an interrupt output pin
named INT and the polarity of the interrupt signal is
selectable. The RF Transceiver issues interrupts to the
MCU host on three possible events. If one of the three
events happens, the RF Transceiver sets the corresponding status bit in SREG0x31. If the corresponding
Rev. 1.00
be issued in two possible conditions. The two conditions are when a packet in TXFIFO is triggered and
sent successfully, or when a packet is triggered and
the retransmission is timed out.
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HT82D40REW
RF Transceiver Application Guide
Some typical applications are described in this section to help user gains more understanding of the operation of the
RF Transceiver.
RF Transceiver Hardware Connection
A typical application connection is shown in Application Circuit section. The MCU host serves as a master role, and the
RF Transceiver serves as a slave role. For more information, refer to the Application Circuit section.
RF Transceiver Initialization
After the RF Transceiver is powered up, some registers need to be configured before the data transmission or reception. The procedure is described as below.
· Procedure List
Parameter
Symbol
Min.
Max.
Unit
SREG
0x26
GATECLK
Enable SPI sync function
20
SREG
0x17
PACON1
Increase PAON time
08
SREG
0x18
FIFOEN
Increase TXON time
94
SREG
0x2E
TXPEMISP
VCO calibration period
95
LREG
0x200
RFCTL0
RF optimized control
01
LREG
0x201
RFCTL1
RF optimized control
02
LREG
0x202
RFCTL2
RF optimized control
E0
LREG
0x204
RFCTL4
RF optimized control
06
LREG
0x206
RFCTL6
RF optimized control
C0
1M bps
LREG
0x207
RFCTL7
RF optimized control
F0
1M bps
LREG
0x208
RFCTL8
RF optimized control
8C
LREG
0x23D
GPIODIR
For Setting GPIO to Output
00
LREG
0x250
RFCTL50
RF optimized control
07
LREG
0x251
RFCTL51
RF optimized control
C0
LREG
0x252
RFCTL52
RF optimized control
01
LREG
0x259
RFCTL59
RF optimized control
00
LREG
0x273
RFCTL73
RF optimized control
40
LREG
0x274
RFCTL74
RF optimized control
C6
LREG
0x275
RFCTL75
RF optimized control
13
LREG
0x276
RFCTL76
RF optimized control
07
Conditions
DC-DC OFF
DC-DC OFF
SREG
0x32
INTMSK
Enable all interrupt
00
SREG
0x2A
SOFTRST
Baseband Reset
02
SREG
0x36
RFCTL
RF Reset
04
Reset RF State Machine
SREG
0x36
RFCTL
RF Reset
00
Release RF State Machine
Rev. 1.00
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HT82D40REW
· Registers associated with Initialization
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x17
PACON
r
r
r
PAONTS3
PAONTS2
PAONTS1
PAONTS0
r
0000 0010
0x18
TXCON
r
r
TXONTS3
TXONTS2
TXONTS1
TXONTS0
r
r
1000 1000
0x26
GATECLK
r
r
SPISYNC
r
r
ENTXM
r
r
0000 0000
0x2A
SOFTRST
r
r
r
r
r
r
RSTBB
RSTMAC
0000 0000
0x2E
TXPEMISP
TXPET3
TXPET2
TXPET1
TXPET0
r
r
r
r
0111 0101
0x32
INTMSK
r
WAKEMSK
r
r
RXMSK
r
r
TXNMSK
1111 1111
0x36
RFCTL
r
r
r
RFRST
r
r
0000 0000
0x200
RFCTRL0
CHANNEL3
CHANNEL2
r
r
r
r
0000 0001
0x201
RFCTRL1
r
r
r
r
r
r
VCORX1
VCORX0
0000 0001
0x202
RFCTRL2
r
RXFC0-1
RXFC0-0
r
r
r
r
r
1000 0100
0x204
RFCTRL4
r
r
r
r
r
RXFCO
RXD2CO1
RXD2CO0
0000 0000
0x206
RFCTRL6
TXFBW1
TXFBW0
32MXCO1
32MXCO0
BATEN
r
r
r
1111 0000
0x207
RFCTRL7
r
r
r
RXFC2
r
r
r
r
0000 0000
0x208
RFCTRL8
r
TXD2CO0
r
r
r
r
r
r
0000 1100
WAKECNT8 WAKECNT7
CHANNEL1 CHANNEL0
0x23D
GPIODIR
r
r
GPIO2DIR
GPIO1DIR
GPIO0DIR
0011 1111
0x250
RFCTRL50
r
r
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0
r
DCPOC
DCOPC3
DCOPC2
DCOPC1
DCOPC0
0000 0000
0x251
RFCTRL51
DCOPC5
DCOPC4
r
r
r
r
r
r
0000 0000
0x252
RFCTRL52
SLCTRL6
SLCTRL5
SLCTRL4
SLCTRL3
SLCTRL2
SLCTRL1
SLCTRL0
32MXCTRL
1111 1111
r
r
0x259
RFCTRL59
0x273
RFCTRL73 VCOTXOPT1 VCOTXOPT0
r
r
r
r
r
PLLOPT3
0000 0001
r
r
PLLOPT2
PLLOPT1
PLLOPT0
r
0000 0000
0x274
RFCTRL74
PACEN0
PACTRL0-2
0x275
RFCTRL75
r
r
r
r
SCLKOPT3
SCLKOPT2
SCLKOPT1
SCLKOPT0
0001 0101
0x276
RFCTRL76
r
r
r
r
r
SCLKOPT6
SCLKOPT5
SCLKOPT4
0000 0001
PACTRL0-1 PACTRL0-0
PACEN1
PACTRL1-2 PACTRL1-1 PACTRL1-0
1100 1010
Change RF Channel Procedure
The RF Transceiver operates in 2.4GHz ISM band. The operating frequency is divided into 16 channels. The procedure to change the channels is described as below.
· Set the RF channel. Users can select one of the channels by configuring either LREG0x200 or LREG0x254.
· Turn on the TX MAC gated clock by setting SREG0x26 [2] to 1. To avoid an incomplete acknowledgment frame
transmission happen during RF state machine reset period.
· Reset RF Transceiver state machine by setting SREG0x36 [2] to 1 and then set SREG0x36 [2] back to 0.
· After RF Transceiver reset, delay for a while to ensure the acknowledgment frame, if any, is successfully transmitted.
250 kbps mode: delay 550ms
1M bps mode: delay 300ms
· To disable the TX MAC gated clock by setting SREG26 [2] to 0.
Registers associated with Change Channel Procedure.
Addr.
File
Name
0x26
GATECLK
0x36
RFCTL
0x200
RFCTRL0
0x254
RFCTRL54
Rev. 1.00
Bit 7
Bit 6
Bit 5
r
r
SPISYNC
r
r
r
CHANNEL3
CHANNEL2
CHANNEL1
1MCSEN
1MFRCH6
1MFRCH5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
r
r
ENTXM
r
r
0000 0000
WAKECNT8
WAKECNT7
RFRST
r
r
0000 0000
CHANNEL0
r
r
r
r
0000 0001
1MFRCH4
1MFRCH3
Bit 4
62
1MFRCH2 1MFRCH1 1MFRCH0
0000 0000
April 1, 2010
HT82D40REW
RF Transceiver Interrupt Configuration
The RF Transceiver issues a hardware interrupt at the internally connected interrupt signal line named INT to the MCU
host. There are two related registers that need to be set correctly. All the interrupts are masked (disabled) by default.
The interrupt mask should be removed by setting SREG0x32 in advance. The interrupt is by default sent to the MCU
host as a falling edge signal after mask removed. The polarity can be configured by LREG0x211. The interrupt status
can be read from SREG0x31 when it is triggered.
Registers associated with Interrupt Configuration
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x31
ISRSTS
r
WAKEIF
r
r
RXIF
r
r
TXNIF
0000 0000
0x32
INTMSK
r
WAKEMSK
r
r
RXMSK
r
r
TXNMSK
1111 1111
0x211
IRQCTRL
r
r
r
r
r
r
IRQPOL
r
0000 0000
RF Transceiver External Power Amplifier Configuration
To enable the Power Amplifier (P.A.), users can set LREG0x22F [2:0] value to 0x001B. This register setting integrates
the P.A. enable and the RF Switch Control (TX branch, RX branch) by utilizing GPIO0, GPIO1 and GPIO2. If the RF
Transceiver is in TX mode, the GPIO0 (external P.A. enable) and GPIO1 (TX branch enable) will be pulled HIGH, and
GPIO2 (RX branch enable) will be pulled LOW. If the RF Transceiver is in RX mode, the GPIO0 and GPIO1 will be
pulled LOW, and GPIO2 will be pulled HIGH. The status of GPIO pins are automatically changed corresponding to
TX/RX mode of the RF Transceiver.
· TX mode: [GPIO0, GPIO1, GPIO2] = [HIGH, HIGH, LOW]
· RX mode: [GPIO0, GPIO1, GPIO2] = [LOW, HIGH, HIGH]
Registers associated with External Power Amplifier Configuration
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x22F
TESTMODE
MSPI
r
r
r
r
TESTMODE2
TESTMODE1
TESTMODE0
0010 1000
RF Transceiver Turbo Mode Configuration
The RF Transceiver provides 1M bps Turbo mode to transmit and receive data at a higher data rate. Turbo mode provides an added capability for applications which require more bandwidth. The application circuits need not any modification for Turbo mode.
To use the RF Transceiver in 250k and 1M bps, the following registers need to be configured as below.
Value (hex)
Address
Mode
Addr.
Register
Name
Descriptions
250k
1M
LREG
0x206
RFCTL6
RF optimized control
0x00
0xC0
LREG
0x207
RFCTL7
RF optimized control
0xE0
0xF0
SREG
0x38
BBREG0
Enable Normal/Turbo mode
0x80
0x81
SREG
0x2A
SOFTRST
Baseband Reset
0x02
Registers associated with External Power Amplifier Configuration
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x2A
SOFTRST
r
r
r
r
r
r
RSTBB
RSTMAC
0000 0000
0x38
BBREG0
r
r
r
r
r
r
r
TURBO
1000 0001
0x206
RFCTRL6
TXFBW1
TXFBW0
32MXCO1
32MXCO0
BATEN
r
r
r
1111 0000
0x207
RFCTRL7
r
r
r
RXFC2
r
r
r
r
0000 0000
Rev. 1.00
63
April 1, 2010
HT82D40REW
Typical RF Transceiver TX Operation
The TXMAC inside the RF Transceiver will automatically generate the preamble, Start-of-Frame Delimiter and the FCS
when transmitting. The MCU host must write all other frame fields into TXFIFO for TX operation. To send a packet in TX
FIFO, there are several steps to follow:
Fill necessary data in TXFIFO. The format of TXFIFO is as follows:
¨
TXFIFO Address
0x001
0x0+N
1 Byte
4 Bytes
1 Byte
N Bytes
Frame Length
Destination Address
Frame Control
Payload
· Set Ackreq by SREG0x1B [2], if an acknowledgement / retransmission is required. The RF Transceiver automatically
retransmits the packet till the number of the Max trial times specified in SREG1B [7:4] is reached, if there is no acknowledgement received.
· By triggering SREG0x1B [0], the TXMAC will send the packet immediately. This bit will be automatically cleared.
· Wait for the interrupt status shown in SREG0x31 [0]. If retransmission is not required, SREG0x31 [0] indicates the
packet is successfully transmitted.
· Check SREG0x24 [0] to see if transmission is successful. If SREG0x24 [0] is equal to 0, it means that the transmis-
sion is successful and the ACK was received. The number of times of the retransmission can be read at SREG0x24
[7:4]. If SREG0x24 [0] is equal to 1, it means that the transmission failed and ACK was not received.
Registers associated with Typical TX Operation
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x1B
TXTRIG
TXRTYN3
TXRTYN2
TXRTYN1
TXRTYN0
r
TXACKREQ
r
TXTRIG
0011 0000
0x24
TXSR
TXRETRY3
TXRETRY2
TXRETRY1
TXRETRY0
r
r
r
TXNS
0000 0000
0x31
ISRSTS
r
WAKEIF
r
r
RXIF
r
r
TXNIF
0000 0000
Typical RF Transceiver RX Operation
When a valid packet is received, an interrupt is issued at SREG0x31 [3]. The MCU host can read the whole packet inside the RXFIFO. The RXFIFO is flushed when the frame length field and the last byte of RXFIFO are read, or when the
MCU host triggers a RX flush by SREG0x0D [0]. The format of RXFIFO is as follows:
· RXFIFO Address
0x300
0x307+N
1 Byte
4 Bytes
1 Byte
N Byte
1 Bytes
Frame Length
Destination Address
Frame Control
Payload
Frame Control
· Registers associated with Typical RX Operation
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x0D
RXFLUSH
r
r
r
r
r
PTX
r
RXFLUSH
0110 0000
0x31
ISRSTS
r
WAKEIF
r
r
RXIF
r
r
TXNIF
0000 0000
Rev. 1.00
64
April 1, 2010
HT82D40REW
RF Transceiver Power Saving Operation
Standby, Deep-Sleep and Power-Down Modes are designed for the RF Transceiver. It is only allowed to switch between power saving modes and active mode. The following settings are effective in active mode only.
Standby Mode
Shutdown RF/MAC/BB, while the voltage regulator, partial 32MHz clock and sleep clock remains active.
· Set LREG0x277 [5:4] to ²00² to select for STANDBY Mode.
· Set LREG0x277 [3:2] to ²10² for enable sleep voltage automatically controlled by internal circuit.
· Set LREG0x253 [4] to ²1² to enable partial 32MHz clock.
Deep_Sleep Mode
All power is shutdown except the power to the digital circuits and sleep clock. Registers and FIFOs are retained.
· Set LREG0x277 [5:4] to ²00² to select for DEEP_SLEEP Mode.
· Set LREG0x277 [3:2] to ²10² for enable sleep voltage automatically controlled by internal circuit.
Power Down Mode
All power is shutdown. Registers and FIFOs data are not retained. Initialization is needed after the RF Transceiver back
to active mode. Only the internal connected interrupt line named WAKE can wake the RF Transceiver up.
· Set LREG0x277 [5:4] to ²11² to select for POWER DOWN Mode.
· Set LREG0x277 [3:2] to ²10² for enable sleep voltage automatically controlled by internal circuit.
· Set LREG0x253 [6:5] to ²11² to connect the FIFO power and digital circuit power to ground.
If the internal connected interrupt line named WAKE is going to be used to wake the RF Transceiver up, the configuration for WAKE line should be included. Refer to the following WAKE Line Wake-up Section for details. The on-chip
DC-DC converter is not used for this device and then bypasses it by setting the DCPOC bit in LREG0x250 register to 0.
After the necessary settings mentioned above are configured, user can execute the following procedures to disable
SPISYNC and place the RF Transceiver to the desired power saving mode.
· Set SREG0x26 [5] to ²0² to disable SPISYNC.
· Set SREG0x35 [7] to ²1² to place the RF Transceiver to power saving mode.
Registers associated with Power Saving Operation:
Addr.
File
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
0x26
GATECLK
r
r
SPISYNC
r
r
ENTXM
r
r
0000 0000
0x35
SLPACK
SLPACK
0x250
RFCTRL50
r
r
r
DCPOC
DCOPC3
0x253
RFCTRL53
r
FIFOPS
DIGITALPS
P32MXE
PACEN2
0x277
RFCTRL77
r
r
SLPSEL1
SLPSEL0
Rev. 1.00
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
65
DCOPC2
DCOPC1
DCOPC0
0000 0000
PACTRL2-2 PACTRL2-1 PACTRL2-0
SLPVCTRL1 SLPVCTRL0 SLPVSEL1
0000 0000
SLPVSEL0
0000 0000
0000 1000
April 1, 2010
HT82D40REW
RF Transceiver Wake-up Operation
After entering into Power Saving Mode, the RF Transceiver could be waked up by the internal register trigger. One and
only one method should be used for wake-up operation.
· Configure clock recovery time
WAKECNT, used to calculate for recovery time of 32MHz clock of the RF Transceiver, should be set in advance. User
shall follow the following two steps to configure WAKECNT.
¨
Calculate the period of sleep clock
Set LREG0x20B [4] to 1 and then keep polling LREG0x20B [7] until the value becomes 1. After the value of
LREG0x20B [7] becomes 1, LREG0x20B [3:0], LREG0x20A, LREG0x209 form a 20-bit value C. Then the period
of the sleep clock (Psleepclock) can be calculated by the following equation:
62.5xC
Psleepclock=
(ns )
16
If the sleep clock frequency is higher than the expected value, user can configure LREG0x220 [4:0] to slow down
the clock rate. The new clock period Psleepclock_new is obtained by the following equation:
Psleepclock_new = Psleepclock_ori ´ 2 LREG0x220[4:0] (ns)
¨
Configure WAKECNT to set the recovery time of 32MHz clock to 180ms
Set WAKECNT, i.e. SREG0x36 [4:3] and SREG0x35 [6:0], to (1000*180) / Psleepclock. For example, the period of the
sleep clock, Psleepclock, is 10000ns. Set SREG0x36 [4:3] and SREG0x35 [6:0]} to 0x12.
Register Trigger Wake-up
User can wake the RF Transceiver up from STANDBY and DEEP_SLEEP modes by simply setting SREG0x22 [7:6] to
²11².
When the RF Transceiver is woken up by Register trigger, the following steps shall be executed to complete the operation:
· Wait the RF Transceiver issues a wake-up interrupt. The related wake-up interrupt flag is stored in SREG0x31 [6].
· Turn on SPISYNC function by setting SREG0x26 [5] to 1.
· Setting the LREG0x250 [4] to 1 to turn off the on-chip DC-DC converter.
Registers associated with Power Saving Operation:
Value on
Addr.
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
RXFLUSH
r
r
r
r
r
PTX
r
RXFLUSH
0110 0000
0x22
WAKECTL
IMMWAKE
REGWAKE
r
r
r
r
r
r
0100 0000
0x26
GATECLK
r
r
SPISYNC
r
r
ENTXM
r
r
0000 0000
WAKEIF
r
r
RXIF
r
r
TXNIF
0000 0000
0x31
ISRSTS
r
0x35
SLPACK
SLPACK
0x36
RFCTL
r
r
r
0x209
SLPCAL_0
SLPCAL7
SLPCAL6
SLPCAL5
SLPCAL4
0x20A
SLPCAL_1
SLPCAL15
SLPCAL14
SLPCAL13
0x20B
SLPCAL_2
r
0x250
RFCTRL50
r
Rev. 1.00
SLPCALRD
Y
r
POR
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
WAKECNT8 WAKECNT7
0000 0000
RFRST
r
r
0000 0000
SLPCAL3
SLPCAL2
SLPCAL1
SLPCAL0
0000 0000
SLPCAL12
SLPCAL11
SLPCAL10
SLPCAL9
SLPCAL8
0000 0000
r
SLPCALEN
SLPCAL19
SLPCAL18
SLPCAL17
SLPCAL16
0000 0000
r
DCPOC
DCOPC3
DCOPC2
DCOPC1
DCOPC0
-0000 0000
66
April 1, 2010
HT82D40REW
Primary RF Transceiver TX Operation
Users activate the primary TX mode by setting SREG0x0D [2] to 1. After changing the SREG0x0D [2] value, users
have to reset the RF and let RF state machine go to primary TX mode correctly. If primary TX mode is enabled, the RF
Transceiver will enter power waving mode after ant packet transmits. If primary TX mode is not enabled, the RF Transceiver will switch to RX mode after any packet transmits. If ACK response is needed and primary TX mode is enabled,
the RF Transceiver will enter the Power Saving Mode after ACK frame received. If no ACK frame received, the RF
Transceiver will not enter the Power Saving Mode until the max time to wait for an acknowledgement frame by setting
SREG0x12 [6:0].
Registers associated with Power Saving Operation:
Value on
Addr.
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
RXFLUSH
r
r
r
r
r
PTX
r
RXFLUSH
0110 0000
0x12
ACKTO
r
MATOP6
MATOP5
MATOP4
MATOP3
MATOP2
MATOP1
MATOP0
0011 1001
POR
RF Transceiver Battery Monitor Operation
The RF Transceiver has Battery Monitor function and the procedure to enable the Battery Monitor function is described
as below.
· Set the battery monitor threshold value at LREG0x205 [7:4].
· Enable the battery monitor by setting the LREG0x206 [3] to the value 1.
· Read the battery-low indicator at SREG0x34 [5]. If this bit is set, it means that the supply voltage is lower than the bat-
tery monitor threshold specified by LREG0x205 [7:4].
Registers associated with Power Saving Operation:
Value on
Addr.
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x34
BATRXF
r
r
BATIND
r
r
r
RDFF1
RXFIFO2
0000 0000
0x205
RFCTRL5
BATTH3
BATTH2
BATTH1
BATTH0
r
r
r
r
0000 0000
0x206
RFCTRL6
TXFBW1
TXFBW0
32MXCO1
32MXCO0
BATEN
r
r
r
1111 0000
POR
RF Transceiver Register Definitions
The Memory of the RF Transceiver is categorized into two kinds of addressing mode, known as Short Addressing Registers and Long Addressing Registers. Each of the Register definition is described in the following sections.
Legends of RF Transceiver Register Types
Register Type
Description
R/W
Read/Write register
WT
Write 1 to trigger register, automatically cleared by hardware
RC
Read to clear register
R
Read-only register
R/W1C
Read/Write ²1² to clear register
Rev. 1.00
67
April 1, 2010
HT82D40REW
RF Transceiver Short Addressing Registers (SREG0x00~SREG0x3F)
0x00
RXMCR
0x12
ACKTO
0x22 WAKECTL
0x30
0x03
AUINFL
0x17
PACON
0x24
0x31
ISRSTS
0x04
AUINFH
0x18
TXCON
0x26 GATECLK
0x32
INTMSK
0x05
DADR_0
0x1B
TXTRIG
0x2A SOFTRST
0x34
BATRXF
0x06
DADR_1
¾
0x2E TXPEMISP
0x07
DADR_2
¾
0x08
DADR_3
0x0D RXFLUSH
TXSR
RXSR
0x35
SLPACK
¾
0x36
RFCTL
¾
¾
0x38
BBREG0
¾
¾
¾
· SREG0x00 - RXMCR: Receive MAC Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
NOACKRSP
¾
¾
¾
¾
¾
Type
R
R
R/W
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~6
Reserved: maintain as ²0b00²
Bit 5
NOACKRSP: Automatic Acknowledgement Response
0: (default) enables automatic acknowledgement response
1: disables automatic acknowledgement response
Bit 4~0
Reserved: maintain as ²0b00000²
· SREG0x03 - AUINFL: Acknowledgement User Information Low Byte
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AUINF7
AUINF6
AUINF5
AUINF4
AUINF3
AUINF2
AUINF1
AUINF0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
AUINF [7:0]: 16-bit User Information of Acknowledgement frame Low Byte.
· SREG0x04 - AUINFH: Acknowledgement User Information High Byte
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AUINF15
AUINF14
AUINF13
AUINF12
AUINF11
AUINF10
AUINF9
AUINF8
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
AUINF [15:8]: 16-bit User Information of Acknowledgement frame High Byte.
· SREG0x05 - DADR_0: Device Address 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
DADR [7:0]: 32-bit Address of the RF Transceiver.
68
April 1, 2010
HT82D40REW
· SREG0x06 - DADR_1: Device Address 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DADR15
DADR14
DADR13
DADR12
DADR11
DADR10
DADR9
DADR8
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
DADR [15:8]: 32-bit Address of the RF Transceiver
· SREG0x07 - DADR_2: Device Address 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DADR23
DADR22
DADR21
DADR20
DADR19
DADR18
DADR17
DADR16
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
DADR [23:16]: 32-bit Address of the RF Transceiver.
· SREG0x08 - DADR_3: Device Address 3
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DADR31
DADR30
DADR29
DADR28
DADR27
DADR26
DADR25
DADR24
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
DADR [31:24]: 32-bit Address of the RF Transceiver
· SREG0x0D - RXFLUSH: Receive FIFO Flush
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
PTX
¾
RXFLUSH
Type
R
R
R
R
R
R/W
R
WT
POR
0
1
1
0
0
0
0
0
Bit 7
Reserved: maintain as ²0b0²
Bit 6-5
Reserved: maintain as ²0b11²
Bit 4-3
Reserved: maintain as ²0b00²
Bit 2
PTX: Primary TX mode enable (1)
1: primary TX mode
0: primary RX mode (default)
Note: RF reset, SREG0x36 [2], is needed after switching between PTX and PRX modes
Bit 1
Reserved: maintain as ²0b0²
Bit 0
RXFLUSH: Flush the RX FIFO
1: Flush RX FIFO. RX FIFO data is not modified. If Ping-pong FIFO is enabled
(SREG0x34 [0] =1), both FIFOs are flushed at the same time. Bit is automatically cleared to
²0² by hardware.
Rev. 1.00
69
April 1, 2010
HT82D40REW
· SREG0x12 - ACKTO: Acknowledgement Timeout Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
MATOP6
MATOP5
MATOP4
MATOP3
MATOP2
MATOP1
MATOP0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
1
1
0
0
1
Bit 2
Bit 1
Bit 0
Bit 7
Reserved: maintain as ²0b0²
Bit 6~0
MATOP [6:0]: Maximum Acknowledgement Timeout Period
0000000: 0 (default)
0000001: 1
0000010: 2
:
0111001: 57
:
1111111: 127
· SREG0x17 - PACON: Power Amplifier Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
¾
¾
¾
Type
R
R
R
R/W
R/W
R/W
R/W
R
POR
0
0
0
0
0
0
1
0
PAONTS3 PAONTS2 PAONTS1 PAONTS0
Bit 7~5
Reserved: maintain as ²0b000²
Bit 4~1
PAONTS [3:0]: Power Amplifier Settling Time to begin packet transmission.
0001: (default)
0100: (optimized - do not change)
Bit 0
Reserved: maintain as ²0b0²
¾
· SREG0x18 - TXCON: Transmitter Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
TXONTS3
TXONTS2
TXONTS1
TXONTS0
¾
¾
Type
R
R
R/W
R/W
R/W
R/W
R
R
POR
0
0
0
0
1
0
0
0
Bit 7~6
Reserved: maintain as ²0b00²
Bit 5~2
TXONTS [3:0]: Transmitter Settling Time to begin packet transmission
0010: (default)
0101: (optimized - do not change)
Bit 1~0
Reserved: maintain as ²0b00²
Rev. 1.00
70
April 1, 2010
HT82D40REW
· SREG0x1B - TXTRIG: Transmit FIFO Control Register
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
¾
TXACKREQ
¾
TXTRIG
TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0
Type
R/W
R/W
R/W
R/W
R
R/W
R
WT
POR
0
0
1
1
0
0
0
0
Bit 7-4
TXRTYN [3:0]: Maximum TX Retry Times
0000: 0
:
0011: 3 (default)
:
0101: 15
Bit 3
Reserved: maintain as ²0b0²
Bit 2
TXACKREQ: TX FIFO Acknowledge Request bit
1: acknowledgement packet requested
0: no acknowledgement packet requested (default)
Transmit a packet with Acknowledgement request. If Acknowledgement is not received,
the RF Transceiver retransmits up to xx times.
Bit 1
Reserved: maintain as ²0b0²
Bit 0
TXTRIG: Transmit Trigger bit
1: Transmit Frame in TX FIFO. Bit is automatically cleared to ²0² by hardware.
· SREG0x22 - WAKECTL: Wake-up Control Register
Bit
Name
Bit 7
Bit 6
IMMWAKE REGWAKE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
¾
¾
¾
¾
¾
¾
Type
R/W
WT
R
R
R
R
R
R
POR
0
1
0
0
0
0
0
0
Bit 7
IMMWAKE: Immediate Wake-up Mode Enable bit
1: enable immediate Wake-up Mode
0: disable immediate Wake-up Mode (default)
Bit 6
REGWAKE: Register Triggered Wake-up bit
1: To wake the RF Transceiver up. Bit is automatically to ²0² by hardware.
Bit 5~0
Reserved: maintain as ²0b000000²
· SREG0x24 - TXSR: TX Status Register
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXRETRY3 TXRETRY2 TXRETRY1 TXRETRY0
Bit 3
Bit 2
Bit 1
Bit 0
¾
¾
¾
TXNX
Type
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7-4
TXRETRY [3:0]: TXFIFO Retry Times
0000: 0 (default)
:
0101: 15
TXRETRY indicates the maximum number of retries of the most recent TXFIFO transmission.
Bit 3-1
Reserved: maintain as ²0b000²
Bit 0
TXNX: TXFIFO Normal Release Status
1: Fail, retry count exceed
0: Succeeded (default)
Rev. 1.00
71
April 1, 2010
HT82D40REW
· SREG0x26 - GATECLK: Gated Clock control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
SPISYNC
¾
¾
ENTRM
¾
¾
Type
R
R
R/W
R
R
R/W
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~6
Reserved: maintain as ²0b00²
Bit 5
SPISYNC: SPI Interface Synchronization
1: enable (optimized - do not change)
0: disable (default)
Bit 4~3
Reserved: maintain as ²0b00²
Bit 2
ENTRM: TX MAC Clock Enable Control
1: enable
0: disable (default)
Bit 1~0
Reserved: maintain as ²0b00²
· SREG0x2A - SOFTRST: Software Reset control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
¾
RSTBB
RSTMAC
Type
R
R
R
R
R
R
WT
WT
POR
0
0
0
0
0
0
0
0
Bit 7-2
Reserved: Maintain as ²0b000000²
Bit 1
RSTBB: Baseband Reset
1: reset baseband circuitry. Initialization is not needed after RSTBB reset. Bit is automatically
cleared to 0 by hardware.
Bit 0
RSTMAC: MAC and Short/Long Addressing Registers Reset.
1: Reset MAC circuitry and Short/Long Addressing Registers. Initialization is needed after
RSTMAC reset. Bit is automatically cleared to ²0² by hardware.
· SREG0x2E - TXPEMISP: Transmit Parameters Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
TXPET3
TXPET2
TXPET1
TXPET0
¾
¾
¾
¾
Type
R/W
R/W
R/W
R/W
R
R
R
R
POR
0
1
1
1
0
1
0
1
Bit 7~4
TXPET [3:0]: TXFIFO Retry Times.
0111: (default)
1001: (optimized - do not change)
Bit 3~0
Reserved: maintain as ²0b0101²
Rev. 1.00
72
April 1, 2010
HT82D40REW
· SREG0x30 - RXSR: RX MAC Status Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RXFFFULL
WRFF1
¾
RXFFOVFL
RXCRCERR
¾
¾
¾
Type
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7
RXFFFULL: RX FIFO Full
1: RX FIFO is not available for data receiving
0: RX FIFO is available for data receiving (default)
Bit 6
WRFF1: RX FIFO Status
1: Packet is ready in RX FIFO 1
0: Packet is ready in RX FIFO 0 (default)
Bit 5
Reserved: maintain as ²0b0²
Bit 4
RXFFOVFL: RX FIFO Overflow
1: RX FIFO overflows
0: (default) RX FIFO not overflow
Bit 3
RXCRCERR: RX CRC Error
1: RX CRC error
0: RX CRC is correct (default)
Bit 2~0
Reserved: maintain as ²0b000²
· SREG0x31 - ISRSTS: Interrupt Status Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
WAKEIF
¾
¾
RXIF
¾
¾
TXNIF
Type
R
RC
R
R
RC
R
R
RC
POR
0
0
0
0
0
0
0
0
Bit 7
Reserved: maintain as ²0b0²
Bit 6
WAKEIF: Wake-up Alert Interrupt
1: A wake-up interrupt occurred
0: No wake-up alert interrupt occurred (default)
This bit is cleared to 0 when the register is read.
Bit 5-4
Reserved: maintain as ²0b00²
Bit 3
RXIF: RX FIFO Reception Interrupt
1: A RX FIFO reception interrupt occurred
0: No RX FIFO reception interrupt occurred (default)
This bit is cleared to 0 when the register is read.
Bit 2-1
Reserved: maintain as ²0b00²
Bit 0
TXNIF: TX FIFO Normal Transmission Interrupt
1: TX FIFO normal transmission interrupt occurred
0: No TX FIFO normal transmission interrupt occurred (default)
This bit is cleared to ²0² when the register is read.
Rev. 1.00
73
April 1, 2010
HT82D40REW
· SREG0x32 - INTMSK: Interrupt Mask control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
WAKEMSK
¾
¾
RXMSK
¾
¾
TXNMSK
Type
R
R/W
R
R
R/W
R
R
R/W
POR
1
1
1
1
1
1
1
1
Bit 7
Reserved: maintain as ²0b1²
Bit 6
WAKEMSK: Wake-up Alert Interrupt Mask
1: disable the wake-up interrupt (default)
0: enable the wake-up alert interrupt
Bit 5~4
Reserved: maintain as ²0b11²
Bit 3
RXMSK: RX FIFO Reception Interrupt Mask
1: disable the RX FIFO reception interrupt (default)
0: enable the RX FIFO reception interrupt
Bit 2~1
Reserved: maintain as ²0b11²
Bit 0
TXNMSK: TX FIFO Normal Transmission Interrupt Mask
1: disable the TX FIFO Normal Transmission interrupt (default)
0: enable the TX FIFO Normal Transmission interrupt
· SREG0x34 - BATRXF: Battery and RX FIFO control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
BATIND
¾
¾
¾
RDFF1
RXFIFO2
Type
R
R
R
R
R
R
R
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Reserved: Maintain as ²0b00²
Bit 5
BATIND: Battery Low Indicator
1: battery voltage is lower than the threshold voltage specified by the LREG0x205 [7:4].
0: battery voltage is higher than the threshold voltage specified by the LREG0x205 [7:4]
(default)
Bit 4~2
Reserved: Maintain as ²0b000²
Bit 1
RDFF1: RX FIFO Selected to Read
1: read data from RX FIFO 1
0: read data from RX FIFO 0 (default)
Bit 0
RXFIFO2: RX Ping-Pong FIFO Enable Control
1: enable the RX Ping-Pong FIFOs
0: disable the RX Ping-Pong FIFOs (default)
· SREG0x35 - SLPACK: Sleep Acknowledgement and Wake-up Counter Register
Bit
Bit 7
Name
SLPACK
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
WT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
Bit 7
SLPACK: Sleep Acknowledgement
Place the RF Transceiver to Power Saving Mode. bit is automatically cleared to 0 by hardware.
Bit 6~0
WAKECNT [6:0]: System Clock Recovery Time
0000000: (default).
WAKECNT is a 9-bit value. The WAKECNT [8:7] bits are located in SREG0x36 [4:3].
Rev. 1.00
74
April 1, 2010
HT82D40REW
· SREG0x36 - RFCTL: RF Mode Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Name
¾
¾
¾
Type
R
R
R
R/W
POR
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
RFRST
¾
¾
R/W
R/W
R
R
0
0
0
0
WAKECNT8 WAKECNT7
Bit 7~5
Reserved: Maintain as ²0b000²
Bit 4~3
WAKECNT [8:7]: System Clock Recovery Time
00: (default).
WAKECNT is a 9-bit value. The WAKECNT [6:0] bits are located in SREG0x35 [6:0].
Bit 2
RFRST: RF State Machine Reset.
1: Hold RF state machine in Reset state
0: Normal operation of RF state machine (default)
Perform RF reset by setting RFRST to ²1² and then setting RFRST to ²0². Delay at least 192ms
after performing to allow RF circuitry to calibrate.
Bit 1~0
Reserved: Maintain as ²0b00²
· SREG0x38 - BBREG0: Baseband Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
¾
¾
TURBO
Type
R
R
R
R
R
R
R
R/W
POR
1
0
0
0
0
0
0
1
Bit 7~1
Reserved: Maintain as ²0b1000000²
Bit 0
TURBO: Turbo Mode Select
1: 1M bps Turbo Mode (default)
0: 250k bps Normal Mode
RF Transceiver Long Addressing Registers (LREG0x200~LREG0x27F)
0x200
RFCTRL0
0x211
IRQCTL
0x250 RFCTRL50
0x273 RFCTRL73
0x201
RFCTRL1
0x22F TESTMODE
0x202
RFCTRL2
0x23C
¾
0x251 RFCTRL51
0x274 RFCTRL74
0x252 RFCTRL52
0x275 RFCTRL75
0x203 _RFCTRL3
0x23D
0x204
RFCTRL4
0x23E
GPIODIR
0x253 RFCTRL53
0x276 RFCTRL76
GPIO
0x254 RFCTRL54
0x205
0x277 RFCTRL77
RFCTRL5
¾
0x259 RFCTRL59
0x206
RFCTRL6
¾
¾
¾
0x207
RFCTRL7
¾
¾
¾
0x208
¾
RFCTRL8
¾
¾
¾
0x209 SLPCAL_0
¾
¾
¾
0x20A SLPCAL_1
¾
¾
¾
0x20B SLPCAL_2
¾
¾
¾
Rev. 1.00
75
April 1, 2010
HT82D40REW
· LREG0x200 - RFCTRL0: RF Control Register 0
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
CHANNEL 3 CHANNEL 2 CHANNEL 1 CHANNEL 0
Bit 3
Bit 2
Bit 1
Bit 0
¾
¾
¾
¾
Type
R/W
R/W
R/W
R/W
R
R
R
R
POR
0
0
0
0
0
0
0
1
Bit 7~4
CHANNEL [3:0]: Channel Number. IEEE 802.15.4 2.4GHz band channels (11~26)
0000: channel 11, 2405MHz (default)
1000: channel 19, 2445MHz
0001: channel 12, 2410MHz
1001: channel 20, 2450MHz
0010: channel 13, 2415MHz
1010: channel 21, 2455MHz
0011: channel 14, 2420MHz
1011: channel 22, 2460MHz
0100: channel 15, 2425MHz
1100: channel 23, 2465MHz
0101: channel 16, 2430MHz
1101: channel 24, 2470MHz
0110: channel 17, 2435MHz
1110: channel 25, 2475MHz
0111: channel 18, 2440MHz
1111: channel 26, 2480MHz
Bit 3~0
Reserved: Maintain as ²0b0001²
· LREG0x201 - RFCTRL1: RF Control Register 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
¾
VCORX1
VCORX0
Type
R
R
R
R
R
R
R/W
R/W
POR
0
0
0
0
0
0
0
1
Bit 7~2
Reserved: Maintain as ²0b000000²
Bit 1~0
VCORX [1:0]: RX VC
01: (default)
10: (optimized - do not change)
· LREG0x202 - RFCTRL2: RF Control Register 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
RXFC0-1
RXFC0-0
¾
¾
¾
¾
¾
Type
R
R/W
R/W
R
R
R
R
R
POR
1
0
0
0
0
0
0
0
Bit 7
Reserved: Maintain as ²0b1²
Bit 6~5
RXFC0 [1:0]: RX Filter Control 0.
00: (default)
11: (optimized - do not change)
Bit 4~0
Reserved: Maintain as ²0b00000²
Rev. 1.00
76
April 1, 2010
HT82D40REW
· LREG0x203 - RFCTRL3: RF Control Register 3
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
TXGB4
TXGB3
TXGB2
TXGB1
TXGB0
¾
¾
¾
Type
R/W
R/W
R/W
R/W
R/W
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7-3
TXGB [4:0]: TX Gain Control in dB. Gain step is monotonic and nonlinear with gain resolution
of 0.1 ~ 0.5 dB. Gain Resolution is variable between chips.
10000: -3.1 dBm
00000: 0 dBm (default)
10001: -3.3 dBm
00001: -0.1 dBm
10010: -3.6 dBm
00010: -0.3 dBm
10011: -3.8 dBm
00011: -0.6 dBm
10100: -4.2 dBm
00100: -0.9 dBm
10101: -4.4 dBm
00101: -1.1 dBm
10110: -4.7 dBm
00110: -1.2 dBm
10111: -5.0 dBm
00111: -1.3 dBm
11000: -5.3 dBm
01000: -1.4 dBm
11001: -5.7 dBm
01001: -1.5 dBm
11010: -6.2 dBm
01010: -1.7 dBm
11011: -6.5 dBm
01011: -2.0 dBm
11100: -6.9 dBm
01100: -2.2 dBm
11101: -7.4 dBm
01101: -2.4 dBm
11110: -7.9 dBm
01110: -2.6 dBm
11111: -8.3 dBm
01111: -2.8 dBm
TX Output Power Configuration Summary table:
TX Output Power Register Control
LREG0x253 [3:0]
00
Rev. 1.00
LREG0x274 [7:0]
C6 for DC-DC OFF
77
LREG0x203 [7:3]
TX Output Power
00000
0 dBm
00001
-0.1 dBm
00010
-0.3 dBm
00011
-0.6 dBm
00100
-0.9 dBm
00101
-1.1 dBm
00110
-1.2 dBm
00111
-1.3 dBm
01000
-1.4 dBm
01001
-1.5 dBm
01010
-1.7 dBm
01011
-2.0 dBm
01100
-2.2 dBm
01101
-2.4 dBm
01110
-2.6 dBm
01111
-2.8 dBm
10000
-3.1 dBm
10001
-3.3 dBm
10010
-3.6 dBm
10011
-3.8 dBm
10100
-4.2 dBm
10101
-4.4 dBm
10110
-4.7 dBm
10111
-5.0 dBm
April 1, 2010
HT82D40REW
TX Output Power Register Control
LREG0x253 [3:0]
00
Bit 2~0
LREG0x274 [7:0]
LREG0x203 [7:3]
TX Output Power
11000
-5.3 dBm
11001
-5.7 dBm
11010
-6.2 dBm
11011
-6.5 dBm
11100
-6.9 dBm
11101
-7.4 dBm
11110
-7.9 dBm
11111
-8.3 dBm
C6 for DC-DC OFF
0C
81
11111
-16 dBm
0C
09
11111
-24 dBm
09
01
11111
-32 dBm
08
01
11111
-40 dBm
Reserved: Maintain as ²0b000²
· LREG0x204 - RFCTRL4: RF Control Register 4
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
RXFCO
RXD2O1
RXD2O0
Type
R
R
R
R
R
R/W
R/W
R\/W
POR
0
0
0
0
0
0
0
0
Bit 7~3
Reserved: Maintain as ²0b00000²
Bit 2
RXFCO: RX Filter Calibration output
1: (optimized - do not change)
0: (default)
Bit 1~0
RXD2O [1:0]: RX Divide-by-2 option
00: (default)
10: (optimized - do not change)
· LREG0x205 - RFCTRL5: RF Control Register 5
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
BATTH3
BATTH2
BATTH1
BATTH0
¾
¾
¾
¾
Type
R/W
R/W
R/W
R/W
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~4
Bit 3~0
Rev. 1.00
BATTH [3:0]: Battery Monitor Threshold.
0000: 1.8V (default)
0001: 1.9V
0010: 2.0V
0011: 2.1V
0100: 2.2V
0101: 2.3V
0110: 2.4V
0111: 2.5V
1000: 2.6V
1001: 2.7V
1010: 2.8V
1011: 2.9V
1100: 3.0V
1101: 3.3V
1110: 3.4V
1111: 3.6V
Reserved: Maintain as ²0b0000²
78
April 1, 2010
HT82D40REW
· LREG0x206 - RFCTRL6: RF Control Register 6
Bit
Bit 7
Bit 6
Bit 5
Name
TXFBW1
TXFBW0
Type
R/W
R/W
R/W
POR
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BATEN
¾
¾
¾
R/W
R/W
R
R
R
1
0
0
0
0
32MXCO1 32MXCO0
Bit 7~6
TXFBW [1:0]: TX Filter
00: Optimized for 250k bps Normal Mode
11: Optimized for 1M bps Turbo Mode
Bit 5~4
32MXCO [1:0]: 32MHz Crystal Oscillator
00: (Optimized - do not change)
11: (default)
Bit 3
BATEN: Battery Monitor Enable
1: Enable
0: Disable (default)
Bit 2~0
Reserved: Maintain as ²0b000²
· LREG0x207 - RFCTRL7: RF Control Register 7
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
RXFC2
¾
¾
¾
¾
Type
R
R
R
R/W
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~5
Reserved: Maintain as ²0b000²
Bit 4
RXFC2: RX Filter Control 2
1: For 1M bps Turbo Mode
0: For 250k bps Normal Mode (default)
Bit 3~0
Reserved: Maintain as ²0b0000²
· LREG0x208 - RFCTRL8: RF Control Register 8
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
TXD2CO1
TXD2CO0
¾
¾
¾
¾
¾
¾
Type
R/W
R/W
R
R
R
R
R
R
POR
0
0
0
0
1
1
0
0
Bit 7~6
TXD2CO [1:0]: TX Divide-by-2 Option
00: (default)
10: (Optimized - do not change)
Bit 5~0
Reserved: Maintain as ²0b001100²
· LREG0x209 - SLPCAL_0: Sleep Clock Calibration 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLPCAL7
SLPCAL6
SLPCAL5
SLPCAL4
SLPCAL3
SLPCAL2
SLPCAL1
SLPCAL0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
SLPCAL [7:0]: Sleep Clock Calibration Counter bit 7~0
A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time
period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
79
April 1, 2010
HT82D40REW
· LREG0x20A - SLPCAL_1: Sleep Clock Calibration 1
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SLPCAL15 SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9
Bit 0
SLPCAL8
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7-0
SLPCAL [15:8]: Sleep Clock Calibration Counter bit 15~8
A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time
period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
· LREG0x20B - SLPCAL_2: Sleep Clock Calibration 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLPCALRDY
¾
¾
Type
R
R
R
WT
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16
Bit 7
SLPCALRDY: Sleep Clock Calibration Ready
1: Sleep Clock Calibration counter is ready to be read.
0: Not Ready (default)
Bit 6-5
Reserved: Maintain as ²0b00²
Bit 4
SLPCALEN: Sleep Clock Calibration Enable
1: Starts the Sleep Clock Calibration counter. Bit is automatically cleared to ²0² by hardware
Bit 3-0
SLPCAL [19:16]: Sleep Clock Calibration Counter bit 19~16
A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time
period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
· LREG0x211 - IRQCTRL: Interrupt Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
¾
IRQPOL
¾
Type
R
R
R
R
R
R
R/W
R
POR
0
0
0
0
0
0
0
0
Bit 7~2
Reserved: Maintain as ²0b000000²
Bit 1
IRQPOL: Interrupt Edge Polarity
1: Rising Edge
0: Falling Edge (default)
Bit 0
Reserved: Maintain as ²0b0²
Rev. 1.00
80
April 1, 2010
HT82D40REW
· LREG0x22F - TESTMODE: Test Mode Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
MSPI
¾
¾
¾
¾
Type
R/W
R
R
R
R
R/W
R/W
R/W
POR
0
0
1
0
1
0
0
0
TESTMODE2 TESTMODE1 TESTMODE0
Bit 7
MSPI: Multiple SPI Operation
1: Enable multiple SPI Operation, SO will be High-Z state when SPI inactive
0: Single SPI Operation, SO will be low when SPI inactive (default)
Bit 6-3
Reserved: Maintain as ²0b0101²
Bit 2-0
TESTMODE [2:0]: Special Operation
000: (default) Normal Operation
001: GPIO0, GPIO1 and GPIO2 are configured to control the external P.A., LNA and RF switch
101: Single-Tone test mode
Others: Undefined.
· LREG0x23D - GPIODIR: GPIO Pin Direction
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
¾
¾
Type
R
R
R/W
R/W
R/W
POR
0
0
1
1
1
Bit 2
Bit 1
Bit 0
GPIO1DIR
GPIO0DIR
R/W
R/W
R/W
1
1
1
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0 GPIO2DIR
Bit 7-6
Reserved: Maintain as ²0b00²
Bit 5-3
GDIRCTRL [2:0]: GPIO Direction Control
000: (Optimized - do not change)
111: (default)
Bit 2
GPIO2DIR: General Purpose I/O GPIO2 Direction
1: Input (default)
0: Output
Bit 1
GPIO1DIR: General Purpose I/O GPIO1 Direction
1: Input (default)
0: Output
Bit 0
GPIO0DIR: General Purpose I/O GPIO0 Direction
1: Input (default)
0: Output
· LREG0x23E - GPIO: GPIO
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
GPIO2
GPIO1
GPIO0
Type
R
R
R
R
R
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~3
Reserved: Maintain as ²0b00000²
Bit 2
GPIO2: Setting for output/Status for input of General Purpose I/O Pin GPIO2
0: (default)
Bit 1
GPIO1: Setting for output/Status for input of General Purpose I/O Pin GPIO1
0: (default)
Bit 0
GPIO0: Setting for output/Status for input of General Purpose I/O Pin GPIO0
0: (default)
Rev. 1.00
81
April 1, 2010
HT82D40REW
· LREG0x250 - RFCTRL50: RF Control Register 50
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
DCPOC
DCOPC3
DCOPC2
DCOPC1
DCOPC0
Type
R
R
R
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
Reserved: Maintain as ²0b000²
Bit 4
DCPOC: DC-DC Converter Power Control
1: Enable
0: Bypass (default)
Bit 3~0
DCOPC [3:0]: DC-DC Converter Optimization Control
0000: (default)
0111: (Optimized - do not change)
· LREG0x251 - RFCTRL51: RF Control Register 51
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DCOPC5
DCOPC4
¾
¾
¾
¾
¾
¾
Type
R/W
R/W
R/W
R/W
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 1
Bit 0
Bit 7~6
DCOPC [5:4]: DC-DC Converter Optimization Control
00: (default)
11: (Optimized - do not change)
Bit 5~0
Reserved: Maintain as 0b000000
· LREG0x252 - RFCTRL52: RF Control Register 52
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
SLCTRL6
SLCTRL5
SLCTRL4
SLCTRL3
SLCTRL2
SLCTRL1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~1
SLCTRL [6:0]: Sleep Clock Control
0000000: (Optimized - do not change)
1111111: (default)
Bit 0
32MXCTRL: Start-up Circuit in 32MHz Crystal Oscillator Control
1: Enable (default)
0: Disable
Rev. 1.00
82
SLCTRL0 32MXCTRL
April 1, 2010
HT82D40REW
· LREG0x253 - RFCTRL53: RF Control Register 53
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
FIFOPS
DIGITALPS
P32MXE
Type
R/W
R/W
R/W
R/W
R
R
R
R
POR
0
0
0
0
0
0
0
0
PACEN2 PACTRL2-2 PACTRL2-1 PACTRL2-0
Bit 7
Reserved: Maintain as ²0b0²
Bit 6
FIFOPS: FIFO Power while the RF Transceiver is in Power Saving Mode
1: GND
0: VDD (default)
Bit 5
DIGITALPS: Digital Power while Sleep
1: GND
0: VDD (default)
Bit 4
P32MXE: Partial 32MHz Clock Enable
1: Enable
0: Disable (default)
Bit 3
PACEN2: Power Amplifier Control 2 Enable
1: Enable
0: Disable (default)
Bit 2~0
PACTRL2-[2:0]: Power Amplifier Control 2
000: (default)
PACTRL2 [2:0] is for 1st stage Power Amplifier current fine tuning. Please follow the TX Output
Power Configuration Summary Table in LREG0x203 Register definition.
Rev. 1.00
83
April 1, 2010
HT82D40REW
· LREG0x254 - RFCTRL54: RF Control Register 54
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
1MCSEN
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
1MCSCH6 1MCSCH5 1MCSCH4 1MCSCH3 1MCSCH2 1MCSCH1 1MCSCH0
Bit 7
1MCSEN: 1 MHz Channel Spacing Enable
1: Enable. When LREG0x254 [7] = 1, RF channel can only be selected by LREG0x254 [6:0] and
the setting of LREG0x200 [7:4] will not change the channel number at all.
0: Disable (default)
Bit 6~0
1MCSCH [6:0]: 1 MHz Channel Spacing Channel Number
LREG0x254 [6:0] only works when LREG0x254 [7] = 1.
0100001: 2433 MHz
0000000: 2400 MHz
0100010: 2434 MHz
0000001: 2401 MHz
0100011: 2435 MHz
0000010: 2402 MHz
0100100: 2436 MHz
0000011: 2403 MHz
0100101: 2437 MHz
0000100: 2404 MHz
0100110: 2438 MHz
0000101: 2405 MHz
0100111: 2439 MHz
0000110: 2406 MHz
0101000: 2440 MHz
0000111: 2407 MHz
0101001: 2441 MHz
0001000: 2408 MHz
0101010: 2442 MHz
0001001: 2409 MHz
0101011: 2443 MHz
0001010: 2410 MHz
0101100: 2444 MHz
0001011: 2411 MHz
0101101: 2445 MHz
0001100: 2412 MHz
0101110: 2446 MHz
0001101: 2413 MHz
0101111: 2447 MHz
0001110: 2414 MHz
0110000: 2448 MHz
0001111: 2415 MHz
0110001: 2449 MHz
0010000: 2416 MHz
0110010: 2450 MHz
0010001: 2417 MHz
0110011: 2451 MHz
0010010: 2418 MHz
0110100: 2452 MHz
0010011: 2419 MHz
0110101: 2453 MHz
0010100: 2420 MHz
0110110: 2454 MHz
0010101: 2421 MHz
0110111: 2455 MHz
0010110: 2422 MHz
0111000: 2456 MHz
0010111: 2423 MHz
0111001: 2457 MHz
0011000: 2424 MHz
0111010: 2458 MHz
0011001: 2425 MHz
0111011: 2459 MHz
0011010: 2426 MHz
0111100: 2460 MHz
0011011: 2427 MHz
0111101: 2461 MHz
0011100: 2428 MHz
0111110: 2462 MHz
0011101: 2429 MHz
0111111: 2463 MHz
0011110: 2430 MHz
1000000: 2464 MHz
0011111: 2431 MHz
1000001: 2465 MHz
0100000: 2432 MHz
Rev. 1.00
84
1000010: 2466 MHz
1000011: 2467 MHz
1000100: 2468 MHz
1000101: 2469 MHz
1000110: 2470 MHz
1000111: 2471 MHz
1001000: 2472 MHz
1001001: 2473 MHz
1001010: 2474 MHz
1001011: 2475 MHz
1001100: 2476 MHz
1001101: 2477 MHz
1001110: 2478 MHz
1001111: 2479 MHz
1010000: 2480 MHz
1010001: 2481 MHz
1010010: 2482 MHz
1010011: 2483 MHz
1010100: 2484 MHz
1010101: 2485 MHz
1010110: 2486 MHz
1010111: 2487 MHz
1011000: 2488 MHz
1011001: 2489 MHz
1011010: 2490 MHz
1011011: 2491 MHz
1011100: 2492 MHz
1011101: 2493 MHz
1011110: 2494 MHz
1011111: 2495 MHz
1100000: Undefined
:
1111111: Undefined
April 1, 2010
HT82D40REW
· LREG0x259 - RFCTRL59: RF Control Register 59
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
¾
¾
PLLOPT3
Type
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~1
Reserved: Maintain as ²0b0000000²
Bit 0
PLLOPT3: PLL Performance Optimization
1: (default)
0: (Optimized - do not change)
· LREG0x273 - RFCTRL73: RF Control Register 73
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
¾
¾
PLLOPT2
PLLOPT1
PLLOPT0
¾
VCOTXOPT1 VCOTXOPT0
Type
R/W
R/W
R
R
R/W
R/W
R/W
R
POR
0
0
0
0
0
0
0
0
Bit 3
Bit 2
Bit 7~6
VCOTXOPT [1:0]: VCO for TX Optimization
00: (default)
01: (Optimized - do not change)
Bit 5~4
Reserved: Maintain as ²0b00²
Bit 3~1
PLLOPT [2:0]: PLL Performance Optimization
000: (default)
111: Optimized for DC-DC Converter Bypass
Bit 0
Reserved: Maintain as ²0b0²
· LREG0x274 - RFCTRL74: RF Control Register 74
Bit
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
PAC0EN PACTRL0-2 PACTRL0-1 PACTRL0-0 PAC1EN PACTRL1-2 PACTRL1-1 PACTRL1-0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
0
0
1
0
1
0
Bit 7
PAC0EN: Power Amplifier Control 0 Enable
1: Enable (default)
0: Disable
Bit 6~4
PACTRL0 [2:0]: Power Amplifier Control 0
100: (default)
PACTRL0 [2:0] is for 1st stage Power Amplifier current large scale control.
Bit 3
PAC1EN: Power Amplifier Control 1 Enable
1: Enable (default)
0: Disable
Bit 2-0
PACTRL1 [2:0]: Power Amplifier Control 1
100: Optimized for DC-DC on
110: Optimized for DC-DC off
010: (default)
PACTRL1 [2:0] is for 2nd stage Power Amplifier current control. Please follow the TX Output
Power Configuration Summary Table in LREG0x203 Register definition.
Rev. 1.00
85
April 1, 2010
HT82D40REW
· LREG0x275 - RFCTRL75: RF Control Register 75
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
SCLKOPT3
SCLKOPT2
SCLKOPT1
SCLKOPT0
Type
R
R
R
R
R/W
R/W
R/W
R/W
POR
0
0
0
1
0
1
0
1
Bit 7~4
Reserved: Maintain as ²0b0001²
Bit 3~0
SCLKOPT [3:0]: Sleep Clock Optimization
0011: (Optimized - do not change)
0101: (default)
· LREG0x276 - RFCTRL76: RF Control Register 76
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
¾
¾
¾
SCLKOPT6
SCLKOPT5
SCLKOPT4
Type
R
R
R
R
R
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
1
Bit 7~3
Reserved: Maintain as ²0b00000²
Bit 2~0
SCLKOPT [6:4]: Sleep Clock Optimization
111: (Optimized - do not change)
001: (default)
· LREG0x277 - RFCTRL77: RF Control Register 77
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
¾
¾
SLPSEL1
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
SLPSEL0 SLPVCTRL1 SLPVCTRL0 SLPVSEL1 SLPVSEL0
Bit 7~6
Reserved: Maintain as ²0b00²
Bit 5~4
SLPSEL [1:0]: Power Saving Mode Selection
00: (default) Standby / Deep Sleep Mode
01: Undefined
10: Undefined
11: Power down Mode
Bit 3~2
SLPVCTRL [1:0]: Sleep Voltage Control
00: Undefined
01: Controlled by LREG0x27 [1:0]
10: (default) automatically controlled by internal circuit
11: Undefined
Bit 1~0
SLPVSEL [1:0]: Sleep Voltage Selection
00: (default - no not change)
Rev. 1.00
86
April 1, 2010
HT82D40REW
RF Transceiver Power-down and Wake-up
The MCU and RF Transceiver are powered down independently of each other. The method of powering down the MCU
is covered in the previous MCU section of the datasheet. The RF Transceiver must be powered down before the MCU
is powered down. The method of powering down the RF Transceiver is mentioned in the previous Power Saving Mode
section of this datasheet.
For a RF Transceiver interrupt to occur, in addition to the bits for the related enable and interrupt polarity control described in RF Transceiver Interrupt Configuration section being set, the global interrupt enable control and the related
interrupt enable control bits in host MCU must also be set. If the bits related to the interrupt function are configured
properly, the RF Transceiver will generate an interrupt signal on INT pin connected to the MCU I/O pin to get the attentions from MCU and then the interrupt subroutine will be serviced. If the related interrupt control bits in host MCU are
not set properly, then the interrupt signal on RF Transceiver INT line will be a wake-up signal and no interrupt will be
serviced.
Using the RF Transceiver Function
To use the RF Transceiver function, several important steps must be implemented to ensure that the RF Transceiver
operates normally:
· The host MCU must be configured as the Master SPI. Therefore, the MCU SPI mode selection bits [M1, M0] in SPI
Interface Control Register can not be set to [1, 1] as slave mode.
· Although the SPI mode selection bits [M1, M0] can be set to [0, 0], [0, 1] and [1, 0], along with the SPI clock source
selection bit CKS, to force the host MCU SPI interface to operate as Master SPI with different baud rate, there are
some limitations on the maximum SPI clock speed that can be selected to be suitable for the RF Transceiver slave
SPI clock speed. As the maximum RF Transceiver slave SPI clock frequency is 5MHz, care must be taken for the
combinations of the SPI clock source selection CKS and mode selection [M1, M0] when the system clock frequency is greater than 5MHz. For example, if the system clock operates at a frequency of 6MHz, the SPI mode selection [M1, M0] and clock source selection CKS should not be set to [0, 0] and 0. Doing so will obtain a Master SPI
baud rate of 6MHz that is greater than the maximum clock frequency of the slave SPI which may result in SPI interface malfunction.
¨
SPI Master/Slave/Baud rate selection bits in SBCR Register
Bit
Bit 6
Bit 5
Name
M1
M0
Value
00, 01, 10
00: SPI master mode; baud rate is fSPI
01: SPI master mode; baud rate is fSPI/4
10: SPI master mode; baud rate is fSPI/16
11: SPI slave mode ® can not be used
¨
SPI Clock source selection bit in SBCR Register
Bit
Bit 7
Name
CKS
Value
0, 1
0: fSPI = fSYS/2
1: fSPI = fSYS
· Since the MSB is first shifted in on SI line and shifted out on SO line for the RF Transceiver slave SPI read/write oper-
ations, the MSB/LSB selection bit MLS in MCU Master SPI SBCR register should be set to 1 for MSB shift first on
SDI/SDO lines.
¨
SPI MSB/LSB first selection bit in SBCR Register
Rev. 1.00
Bit
Bit 5
Name
MLS
Setting value
1
87
April 1, 2010
HT82D40REW
· As the RF Transceiver slave SPI timing diagram shows, the SPI data output mode selection SPI_MODE and the
clock polarity selection SPI_CPOL of the master SPI should be correctly set to fit the slave SPI protocol requirement.
To successfully communicate with the RF Transceiver slave SPI, the SPI_MODE and SPI_CPOL of the MCU master
SPI should be set to [1, 1].
¨
SPI_MODE and SPI_CPOL setup in SPIR Register
Bit
Bit 1
Bit 0
Name
SPI_MODE
SPI_CPOL
Setting value
1
1
The relevant timing diagram for the above setting is shown in the preceding SPI Bus Timing diagram in SPI Serial
Interface section.
· For the MCU master SPI to completely control the slave SPI SEN line, the MCU master SPI uses a general purpose
I/O line via application program instead of the SPI SCS line with hardware mechanism. To achieve this requirement,
the software CSEN enable control bit SPI_CSEN of the Master SPI should be set to 0, then the master SPI SCS line
will lose the SCS line characteristics and be configured as a general purpose I/O line.
¨
SPI_CSEN software CSEN enable control bit in SPIR Register
Bit
Bit 2
Name
SPI_CSEN
Setting value
0
0: the software CSEN function is disabled and the SCS line is configured as an I/O line
· Finally set the SPI_EN bit to 1 to ensure that the pin-shared function for other three SPI lines known as SCK, SDI and
SDO are surely selected.
¨
SPI_EN software SPI interface lines enable control bit in SPIR Register
Bit
Bit 2
Name
SPI_EN
Setting value
1
1: the pin-shared function of the SPI interface lines is enabled.
After the above setup conditions have been implemented, the MCU can enable the SPI interface by setting the
SBEN bit high. The MCU can then begin communication with the RF Transceiver using the SPI interface. The detailed MCU Master SPI functional description is provided within the SPI Serial Interface section of the MCU
datasheet.
Rev. 1.00
88
April 1, 2010
HT82D40REW
Application Circuits
RF_VCC
22pF
RF_VCC
10nF
1pF
1pF
32M
100pF
10nF
ANT
22pF
3.9nH
RF_VCC
1nF
31
32
33
34
35
36
37
38
39
40
5.6nH
5.6nH
VDD_GR/
VDD_BG
VDD_A
XTAL_N
XTAL_P
VDD_PLL
VDD_CP
VDD_VCO
LOOP_C
DB5
VDD_RF1
1pF
1
RF_VCC
RF_P
RF_N
VDD_RF2
NC
VDDP
SCL
SDA
1nF
VDD
EP_SCK
EP_SDA
VDD
VSSP
VDD
V33O
0.1uF
10R
PB7
PA0
PA1
30
29
28
27
26
25
24
RF_VCC
RF_VCC
23
22
21
20
19
18
17
16
15
14
13
12
11
RF_VCC
HT82D40REW
VDD_3V
VDD_2V2
VDD_D
GPIO0
GPIO1
GND
GPIO2
PA2
PA3
PA4
PA5
PA6/ TMR0
PA7/ TMR1
RES
VSS
PDP
PDN
2
3
4
5
6
7
8
9
10
1nF
DD+
USB
1
2
3
4
Rev. 1.00
VDD
DD+
1uF
EP_SCK
EP_SDA
VDD
100K
89
1uF
April 1, 2010
HT82D40REW
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
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HT82D40REW
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
101
April 1, 2010
HT82D40REW
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
102
April 1, 2010
HT82D40REW
Package Information
SAW Type 40-pin (6mm´6mm for 0.75mm) QFN Outline Dimensions
D
D 2
3 1
4 0
3 0
b
1
E
E 2
e
2 1
A 1
A 3
1 0
2 0
L
1 1
K
A
· GTK
Symbol
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
¾
0.008
¾
b
0.007
0.010
0.012
D
¾
0.236
¾
E
¾
0.236
¾
e
¾
0.020
¾
D2
0.173
0.177
0.179
E2
0.173
0.177
0.179
L
0.014
0.016
0.018
K
0.008
¾
¾
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
¾
0.20
¾
b
0.18
0.25
0.30
D
¾
6.00
¾
E
¾
6.00
¾
e
¾
0.50
¾
D2
4.40
4.50
4.55
E2
4.40
4.50
4.55
L
0.35
0.40
0.45
K
0.20
¾
¾
103
April 1, 2010
HT82D40REW
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
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5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
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46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
104
April 1, 2010