256Mb : x32 Dual Die Synchronous DRAM 256M (8Mx32bit) Hynix SDRAM Memory This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Oct. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Document Title 256Mbit (8M x32) Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Sep. 2009 Preliminary 1.0 Release Oct. 2009 Rev 1.0 / Oct. 2009 2 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DESCRIPTION The Hynix H57V2622GMR Synchronous DRAM (Dual Die) ideally suited for the consumer memory applications which requires large memory density and high bandwidth uses Hinix’s 128Mb SDR monolithic die and has similar functionality. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal). Rev 1.0 / Oct. 2009 3 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series 256Mb Synchronous DRAM(8M x 32) FEATURES ● Standard SDRAM Protocol ● Uses 2pcs of 128Mb Monolithic Die ● Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V ● All device pins are compatible with LVTTL interface ● 4096 Refresh cycles / 64ms ● Programmable CAS latency of 2 or 3 ● Programmable Burst Length and Burst Type ● Operating Temp. - Commercial Temp. : 0oC ~ 70oC, Industrial Temp. : -40oC ~ 85oC ● This product is in compliance with the directive pertaining of RoHS. ORDERING INFORMATION Part Number Clock Frequency CAS Latency H57V2622GMR-60X 166MHz 3 H57V2622GMR-75X 133MHz 3 H57V2622GMR-60X 166MHz 3 H57V2622GMR-75X 133MHz 3 Voltage Organization Interface 3.3V 4Banks x 2Mbits x16 x 2Die LVTTL Note : 1. H57V2622GMR-XXC : Normal power, Commercial Temp. (0~70℃) 2. H57V2622GMR-XXI : Normal power, Industrial Temp. (-40~85℃) 3. H57V2622GMR-XXL : Low power, Commercail Temp. (0~70℃) 4. H57V2622GMR-XXJ : Low power, Industrial Temp. (-40~85℃) Rev 1.0 / Oct. 2009 4 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BALL CONFIGURATION 1 2 3 A DQ26 DQ24 B DQ28 C 4 5 6 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 A11 J CLK CKE A9 BA0 /CS /RAS K DQM1 NC NC /CAS /WE DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 Rev 1.0 / Oct. 2009 Top View 5 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BALL DESCRIPTIONS SYMBOL TYPE DESCRIPTION CLK INPUT Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE INPUT Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS INPUT Chip Select: Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 INPUT Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 INPUT Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details DQM0 ~ DQM3 I/O Data Mask: Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 I/O Data Input / Output: Multiplexed data input / output pin VDD / VSS SUPPLY Power supply VDDQ / VSSQ SUPPLY I/O Power supply NC - Rev 1.0 / Oct. 2009 No connection : These pads should be left unconnected 6 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O x 2 Die Synchronous DRAM Self refresh logic & timer Internal Row Counter 2nd Die 2Mx16 Bank0~4 CLK Column Pre Decoder DQM0 ~ DQM3 DQ0 I/O Buffer & Logic Column Active Memory Cell Array Sense AMP & I/O Gate Refresh WE 2Mx16 Bank0~4 X Decoders CAS 1st Die X Decorders RAS State Machine CS Row Pre Decoder Row Active CKE DQ31 Y decoerders Column Add Counter Bank Select A0 BA1 Burst Counter Burst Length A11 Address Buffers A1 Address Register Mode Register CAS Latency Data Out Control Pipe Line Control BA0 Rev 1.0 / Oct. 2009 7 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series ABSOLUTE MAXIMUM RATING Parameter Symbol Rating Unit 0 ~ 70 oC -40 ~ 85 oC TSTG -55 ~ 125 oC Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W TSOLDER 260 . 10 Ambient Temperature (Commercial Temp.) Ambient Temperature (Industrial Temp.) Storage Temperature Soldering Temperature . Time TA C . Sec o DC OPERATING CONDITION (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Parameter Symbol Min Max Unit Note VDD, VDDQ 3.0 3.6 V 1 Input High Voltage VIH 2.0 VDDQ + 0.3 V 1, 2 Input Low Voltage VIL -0.3 0.8 V 1, 3 Power Supply Voltage Note: 1. All voltages are referenced to VSS = 0V. 2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration. 3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration. AC OPERATING TEST CONDITION (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃, VDD=3.3±0.3V / VSS=0V) Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 0.5 x VDDQ V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 0.5 x VDDQ V CL 50 pF AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1 Note: 1. See Next Page Rev 1.0 / Oct. 2009 8 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series VTT = 1.4V VTT = 1.4V RT = 250 Ohom RT = 50 Ohom Output Output Z0 = 50 Ohom 50pF 50pF DC Output Load Circuit AC Output Load Circuit CAPACITANCE (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃ , f=1MHz) Parameter Input capacitance Data input / output capacitance Pin Symbol Min Max Unit CLK CI1 4.0 8.0 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE CI2 4.0 8.0 pF DQM0 ~ DQM3 CI3 4.0 8.0 pF DQ0 ~ DQ31 CI/O 3.5 6.5 pF DC CHARACTERRISTICS I (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note: 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Rev 1.0 / Oct. 2009 9 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DC CHARACTERISTICS II Parameter Operating Current (Commercial : TA = 0~70℃, Industrial : TA = -40~85℃) Symbol IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA IDD2P CKE ≤ VIL(max), tCK = 15ns Precharge Standby Current in Power Down Mode IDD2PS Speed Test Condition 166 133 160 140 Unit Note mA 1 Normal 2.0 mA Low Power 1.6 mA Normal 2.0 mA Low Power 1.6 mA 3 CKE ≤ VIL(max), tCK = ∞ 3 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 18 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 IDD3P CKE ≤ VIL(max), tCK = 15ns 8 IDD3PS CKE ≤ VIL(max), tCK = ∞ 8 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 40 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 35 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active 200 200 mA 1 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 400 380 mA 2 Self Refresh Current IDD6 CKE ≤ 0.2V mA 3 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode IDD2N mA mA mA Normal 4 Low Power 1.6 Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V2622GMR-XXC : Normal, Rev 1.0 / Oct. 2009 H57V2622GMR-XXL : Low Power 10 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter Symbol 166 133 Min Max Min Max Unit Note CL = 3 tCK3 6.0 1000 7.5 1000 ns CL = 2 tCK2 - - 10 1000 ns Clock High Pulse Width tCHW 2.5 - 2.5 - ns 1 Clock Low Pulse Width tCLW 2.5 - 2.5 - ns 1 CL = 3 tAC3 - 5.4 - 5.4 ns 2 CL = 2 tAC2 - - - 6 ns 2 Data-out Hold Time tOH 2.0 - 2.5 - ns Data-Input Setup Time tDS 1.5 - 1.5 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - ns 1 Address Setup Time tAS 1.5 - 1.5 - ns 1 Address Hold Time tAH 0.8 - 0.8 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - ns 1 Command Setup Time tCS 1.5 - 1.5 - ns 1 Command Hold Time tCH 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - ns CL = 3 tOHZ3 2.7 5.4 2.7 5.4 ns CL = 2 tOHZ2 - - 3 6 ns System Clock Cycle Time Access Time From Clock CLK to Data Output in High-Z Time Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev 1.0 / Oct. 2009 11 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol 166 133 Min Max Min Max Unit Operation tRC 60 - 63 - ns Auto Refresh tRRC 60 - 63 - ns RAS to CAS Delay tRCD 18 - 20 - ns RAS Active Time tRAS 42 100K 42 100K ns RAS Precharge Time tRP 18 - 20 - ns RAS to RAS Bank Active Delay tRRD 12 - 15 - ns CAS to CAS Delay tCCD 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - CLK Data-in to Precharge Command tDPL 2 - 2 - CLK Data-In to Active Command tDAL DQM to Data-Out Hi-Z tDQZ 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - CLK CL = 3 tPROZ3 3 - 3 - CLK CL = 2 tPROZ2 - - 2 - CLK Power Down Exit Time tDPE 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - CLK Refresh Time tREF - 64 - 64 ms RAS Cycle Time Precharge to Data Output High-Z Note CLK 5 1 Note: 1. A new command can be given tRC after self refresh exit. Rev 1.0 / Oct. 2009 12 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 A3 CAS Latency OP Code A2 BT A1 A0 Burst Length Burst Type A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency A3 Burst Type 0 Sequential 1 Interleave Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 0 1 0 1 1 0 1 0 A2 A1 A0 Reserved 0 0 0 2 0 1 3 0 Reserved 1 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Reserved 1 0 0 Reserved Reserved 1 Reserved Reserved 1 1 0 Reserved 1 0 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full page Reserved Rev 1.0 / Oct. 2009 13 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series COMMAND TRUTH TABLE Function ADDR A10 /AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X Op Code No Operation H X L H H H X X Device Deselect H X H X X X X X Bank Active H X L L H H X Row Address BA V Column L V Read H X L H L H Read with Autoprecharge H X L H L H X Column H V Write H X L H L L X Column L V Write with Autoprecharge H X L H L L X Column H V Precharge All Banks H X L L H L X X H X Precharge selected Bank H X L L H L X X L V Burst stop H X L H H L X X DQM H X V X Auto Refresh H H L L L H X X Burst-Read Single-Write H X L L L H X A9 Pin High (Other Pins OP code) Self Refresh Entry H L X X X X X X X X X X X X Self Refresh Exit L H Precharge Power Down Entry H L Precharge Power Down Exit L H Clock Suspend Entry H L Clock Suspend Exit L H X L L L H H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V X Note 2 1 Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. see to Next page (DQM TRUTH TABLE) Rev 1.0 / Oct. 2009 14 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series DQM TRUTH TABLE Function CKEn-1 CKEn DQM0 DQM1 DQM2 DQM3 Data Write/Output enable H X L L L L Data Mask/Output disable H X H H H H DQ0 to DQ7 write enable / output enable H X L X X X DQ0 to DQ7 write inhibit / output disable H X H X X X DQ8 to DQ15 write enable / output enable H X X L X X DQ8 to DQ15 write inhibit / output disable H X X H X X DQ16 to DQ23 write enable / output enable H X X X L X DQ16 to DQ23 write inhibit / output disable H X X X H X DQ24 to DQ31 write enable / output enable H X X X X L DQ24 to DQ31 write inhibit / output disable H X X X X H Note 1. H: High Level, L: Low Level, X: Don't Care 2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK Rev 1.0 / Oct. 2009 15 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State idle Row Active Read Command CS RAS CAS WE BA0/ BA1 L L L L L L L H X L L H L L L H L H L Amax-A0 Notes Mode Register Set Set the Mode Register X Auto or Self Refresh Start Auto or Self Refresh BA X Precharge No Operation H BA Row Add. Bank Activate Activate the specified bank and row L L BA Col Add. A10 Write/WriteAP ILLEGAL 4 H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4 L H H H X X No Operation No Operation 3 H X X X X X Device Deselect No Operation or Power Down 3 L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Precharge 7 L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Start Write : optional AP(A10=H) 6 L H L H BA Col Add. A10 Read/ReadAP Start Read : optional AP(A10=H) 6 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Termination Burst: Start the Precharge L L H H BA Row Add. Bank Activate ILLEGAL L H L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8,9 L H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8 L H H H X X No Operation Continue the Burst Rev 1.0 / Oct. 2009 OP CODE Action Description OP CODE OP CODE 5 4 16 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State Read Write Read with Auto Precharge Write with Auto Precharge (Sheet 2 of 4) Command CS RAS CAS WE BA0/ BA1 Amax-A0 X X H X X X L L L L L L L H X L L H L L L H L H L Action Description Notes Device Deselect Continue the Burst Mode Register Set ILLEGAL 13 X Auto or Self Refresh ILLEGAL 13 BA X Precharge Termination Burst: Start the Precharge 10 H BA Row Add. Bank Activate ILLEGAL 4 L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8 H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8,9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Rev 1.0 / Oct. 2009 OP CODE OP CODE OP CODE 17 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State Precharging Row Activating Write Recovering (Sheet 3 of 4) Command CS RAS CAS WE BA0/ BA1 L L L L L L L H X L L H L L L H L H L Amax-A0 13 X Auto or Self Refresh ILLEGAL 13 BA X Precharge No Operation: Bank(s) idle after tRP H BA Row Add. Bank Activate ILLEGAL 4,12 L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Bank(s) idle after tRP H X X X X X Device Deselect No Operation: Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,11,1 2 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Row Active after tRCD H X X X X X Device Deselect No Operation: Row Active after tRCD L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP Start Write: Optional AP(A10=H) L H L H BA Col Add. A10 Read/ReadAP Start Read: Optional AP(A10=H) L H H H X X No Operation No Operation: Row Active after tDPL OP CODE OP CODE Mode Register Set Notes ILLEGAL Rev 1.0 / Oct. 2009 OP CODE Action Description 9 18 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CURRENT STATE TRUTH TABLE Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing (Sheet 4 of 4) Command CS RAS CAS WE BA0/ BA1 Amax-A0 X X Action Description Notes Device Deselect No Operation: Row Active after tDPL Mode Register Set ILLEGAL 13 X Auto or Self Refresh ILLEGAL 13 BA X Precharge ILLEGAL 4,13 H BA Row Add. Bank Activate ILLEGAL 4,12 L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,9,12 L H H H X X No Operation No Operation: Precharge after tDPL H X X X X X Device Deselect No Operation: Precharge after tDPL L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after tRC H X X X X X Device Deselect No Operation: idle after tRC L L L L Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after 2 clock cycles H X X X X X Device Deselect No Operation: idle after 2 clock cycles H X X X L L L L L L L H X L L H L L L H L H L Rev 1.0 / Oct. 2009 OP CODE OP CODE OP CODE 19 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. Rev 1.0 / Oct. 2009 20 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CKE Enable(CKE) Truth TABLE (Sheet 1 of 2) CKE Command Current State Self Refresh Previous Current Cycle Cycle CS RAS CAS WE Notes H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 L H H X X X X X L H H H X X Power Down mode exit, all banks idle 2 L X X X X X L X X X ILLEGAL 2 X X L X X X X Power Down L All Banks Idle Action BA0, ADDR BA1 H L L L X X X X H H H X X X H H L H X X H H L L H X H H L L L H X H H L L L L OP CODE H L H X X X H L L H X X H L L L H X H L L L L H X X Entry Self Refresh H L L L L L OP CODE Mode Register Set L X X X X X X Power Down Rev 1.0 / Oct. 2009 Maintain Power Down Mode Refer to the idle State section of the Current State Truth Table X 3 3 Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table X 3 4 3 3 3 4 4 21 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) CKE Command Current State Any State other than listed above Previous Current Cycle Cycle CS RAS CAS WE Action BA0, ADDR BA1 H H X X X X X X Refer to operations of the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend Notes Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev 1.0 / Oct. 2009 22 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series PACKAGE INFORMATION 90 Ball FBGA, 8mm x 13mm x 1.1mm, 0.8mm pitch Unit [mm] 8.00 ± 0.10 A1 Index Mark 0.8(Typ) 0.8 6.40 BSC 0.8(Typ) 0.450 ± 0.05 4.00 ± BSC 5.6 ± 0.05 3.20 ± 0.05 13.0 ± 0.10 11.20 Bottom View 0.05 0.340 1.1max Rev 1.0 / Oct. 2009 ± 0.05 Side View 23