U632H16 PowerStore 2K x 8 nvSRAM Features High-performance CMOS nonvolatile static RAM 2048 x 8 bits 25 ns Access Times 12 ns Output Enable Access Times ICC = 15 mA at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using external capacitor Hardware or Software initiated STORE (STORE Cycle Time < 10 ms) Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 20 μs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7-HBM) RoHS compliance and Pb- free Package: SOP28 (300 mil) Description The U632H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U632H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 μF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U632H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence or via a single pin (HSB). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Pin Description Pin Configuration VCAP 1 28 n.c. 2 3 27 VCCX W Signal Name Signal Description A0 - A10 Address Inputs DQ0 - DQ7 Data In/Out 4 26 25 A5 5 24 A8 A9 A4 A3 6 7 23 n.c. E Chip Enable 22 G 8 A1 9 10 20 A10 E G Output Enable A2 Write Enable 19 DQ7 W VCCX Power Supply Voltage 11 18 VSS Ground DQ1 12 VCAP Capacitor DQ2 13 14 17 16 15 DQ6 DQ5 HSB Hardware Controlled Store/Busy A7 A6 A0 DQ0 VSS SOP 21 HSB DQ4 DQ3 Top View March 31, 2006 STK Control #ML0046 1 Rev 1.0 U632H16 Block Diagram VCCX EEPROM Array 32 x (64 x 8) VSS VCAP STORE SRAM Array Row Decoder A5 A6 A7 A8 A9 RECALL Power Control VCCX VCAP Store/ Recall Control HSB 32 Rows x 64 x 8 Columns DQ0 DQ1 Column I/O Input Buffers DQ2 DQ3 DQ4 DQ5 DQ6 Software Detect Column Decoder G A0 A1 A2 A3 A4 A10 DQ7 A0 - A10 E W Truth Table for SRAM Operations Operating Mode E HSB W G DQ0 - DQ7 Standby/not selected H H * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and outputsignals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratingsa Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.3 VCC+0.5 V Output Voltage VO -0.3 VCC+0.5 V Power Dissipation PD 1 W Power Supply Voltage Operating Temperature Storage Temperature a: C-Type K-Type Ta 0 -40 70 85 °C °C Tstg -65 150 °C Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STK Control #ML0046 2 Rev 1.0 March 31, 2006 U632H16 Recommended Operating Conditions Symbol Power Supply Voltageb VCC Input Low Voltage VIL Input High Voltage VIH DC Characteristics Symbol Conditions -2 V at Pulse Width 10 ns permitted Min. Max. Unit 4.5 5.5 V -0.3 0.8 V 2.2 VCC+0.3 V C-Type K-Type Conditions Unit Min. Operating Supply Currentc ICC1 Max. Min. Max. VCC VIL VIH = 5.5 V = 0.8 V = 2.2 V tc = 25 ns 90 95 mA Average Supply Current during STORE c ICC2 VCC E W VIL VIH = 5.5 V ≤ 0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 6 7 mA Average Supply Current during PowerStore Cycle ICC4 VCC VIL VIH = 4.5 V = 0.2 V ≥ VCC-0.2 V 4 4 mA ICC(SB)1 VCC E = 5.5 V = VIH tc = 25 ns 30 34 mA Standby Supply Currentd (Cycling TTL Input Levels) Operating Supply Current at tcR = 200 nsc (Cycling CMOS Input Levels) ICC3 VCC W VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 15 15 mA Standby Supply Currentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 3 3 mA b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. c: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2. March 31, 2006 STK Control #ML0046 3 Rev 1.0 U632H16 C-Type DC Characteristics Symbol Unit Min. Output High Voltage Output Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 mA = 8 mA Output High Current Output Low Current IOH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V VCC = 5.5 V VIH VIL = 5.5 V = 0V VCC = 5.5 V VOH VOL = 5.5 V = 0V Input Leakage Current High Low IIH IIL Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ K-Type Conditions Max. 2.4 Min. Max. 2.4 0.4 0.4 -4 8 -4 mA mA 1 μA μA 8 1 -1 -1 1 1 -1 -1 V V μA μA SRAM Memory Operations No. e: f: g: h: Symbol Switching Characteristics Read Cycle Unit Alt. IEC Min. Max. 1 Read Cycle Timef tAVAV tcR 2 Address Access Time to Data Validg tAVQV ta(A) 25 ns 3 Chip Enable Access Time to Data Valid tELQV ta(E) 25 ns 4 Output Enable Access Time to Data Valid tGLQV ta(G) 12 ns 5 E HIGH to Output in High-Zh tEHQZ tdis(E) 13 ns 6 G HIGH to Output in High-Zh tGHQZ tdis(G) 13 ns 7 E LOW to Output in Low-Z tELQX ten(E) 5 ns 8 G LOW to Output in Low-Z tGLQX ten(G) 0 ns 9 Output Hold Time after Address Change tAXQX tv(A) 3 ns 10 Chip Enable to Power Activee tELICCH tPU 0 ns 11 Chip Disable to Power Standbyd, e tEHICCL tPD 25 ns 25 ns Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or coincident with E transition LOW. Measured ± 200 mV from steady state output voltage. STK Control #ML0046 4 Rev 1.0 March 31, 2006 U632H16 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f tcR (1) Ai Address Valid ta(A) (2) DQi Output Output Data Valid Previos Data Valid tv(A) (9) Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g tcR (1) Ai Address Valid ta(A) (2) ta(E) (3) E ten(E) (7) G DQi Output ICC No. tPD (11) tdis(E) (5) ta(G) (4) tdis(G) (6) ten(G) (8) High Impedance ACTIVE Output Data Valid tPU (10) STANDBY Symbol Switching Characteristics Write Cycle 25 Unit Alt. #1 Alt. #2 12 Write Cycle Time tAVAV 13 Write Pulse Width tWLWH 14 Write Pulse Width Setup Time tAVAV IEC Min. Max. tcW 25 ns tw(W) 20 ns tWLEH tsu(W) 20 ns 15 Address Setup Time tAVWL tAVEL tsu(A) 0 ns 16 Address Valid to End of Write tAVWH tAVEH tsu(A-WH) 20 ns 17 Chip Enable Setup Time tELWH tsu(E) 20 ns tELEH tw(E) 20 ns 18 Chip Enable to End of Write 19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 12 ns 20 Data Hold Time after End of Write tWHDX tEHDX th(D) 0 ns 21 Address Hold after End of Write tWHAX tEHAX th(A) 0 ns 22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 23 W HIGH to Output in Low-Z tWHQX ten(W) March 31, 2006 STK Control #ML0046 5 Rev 1.0 10 5 ns ns U632H16 Write Cycle #1: W-controlledj tcW (12) Ai Address Valid tsu(E) (17) th(A) (21) E W tsu(A) Input Data Valid Input Output th(D) (20) tsu(D) (19) (15) DQi DQi tsu(A-WH) (16) tw(W) (13) tdis(W) (22) ten(W) (23) High Impedance Previous Data Valid Write Cycle #2: E-controlledj tcW (12) Ai E W Address Valid tsu(A) (15) tw(E) (18) th(A) (21) tsu(W) (14) tsu(D) (19) DQi th(D) (20) Input Data Valid Input DQi High Impedance Output undefined i: j: L- to H-level H- to L-level If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W must be VIH during address transition. STK Control #ML0046 6 Rev 1.0 March 31, 2006 U632H16 Nonvolatile Memory Operations Mode Selection E W HS B A10 - A0 (hex) Mode I/O Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active L H H 000 555 2AA 7FF 0F0 70F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active k, l k, l k, l k, l k, l k L H H 000 555 2AA 7FF 0F0 70E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active k, l k, l k, l k, l k, l k X X L X STORE/Inhibit Output High Z ICC2/Standby m Notes l k: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C. l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G. m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the part will go into standby mode inhibiting all operation until HSB rises. No. PowerStore Power Up RECALL/ Hardware Controlled STORE 24 Power Up RECALL Durationn, e Conditions Alt. Min. Max. Unit 650 μs 10 ms IEC tRESTORE 25 STORE Cycle Duration tHLQX td(H)S 26 HSB Low to Inhibit One tHLQZ tdis(H)S 27 HSB High to Inhibit Offe tHHQX ten(H)S 28 External STORE Pulse Widthe tHLHX tw(H)S VCC > 4.5 V μs 1 700 ns 250 ns mA HSB Output Low Currente, o IHSBOL HSB = VOL 3 HSB Output High Currente, o IHSBOH HSB = VIL 5 60 μA 4.0 4.5 V Low Voltage Trigger Level n: o: Symbol VSWITCH tRESTORE starts from the time VCC rises above VSWITCH. HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U632H16 to be ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U632H16 HSB pins. March 31, 2006 STK Control #ML0046 7 Rev 1.0 U632H16 PowerStore and automatic Power Up RECALL VCAP 5.0 V VSWITCH t PowerStore Power Up RECALL W tPDSTOREp (24) (24) tRESTORE tRESTORE tDELAYp DQi POWER UP RECALL BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT PowerStore Hardware Controlled Store HSB DQi Output tw(H)Sq (28) ten(H)S (27) tdis(H)S (26) High Impedance Previous Data Valid Data Valid td(H)S (25) No. Symbol Software Controlled STORE/ RECALL Cycle Unit Alt. IEC Min. Max. 29 STORE/RECALL Initiation Time tAVAV tcR 30 Chip Enable to Output Inactives tELQZ tdis(E)SR 600 ns 31 STORE Cycle Time tELQXS td(E)S 10 ms 32 RECALL Cycle Timer tELQXR td(E)R 20 μs 33 Address Setup to Chip Enable tAVELN tsu(A)SR 0 ns 34 Chip Enable Pulse Widths, t tELEHN tw(E)SR 20 ns 35 Chip Disable to Address Change tEHAXN th(A)SR 0 ns 25 ns p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S. q: After tw(H)S HSB is hold down internal by STORE operation. r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. STK Control #ML0046 8 Rev 1.0 March 31, 2006 U632H16 Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation) tcR (29) Ai E ADDRESS 1 ADDRESS 6 tw(E)SR tw(E)SR (33) tsu(A)SR DQi tcR (29) High Impedance Output (33) (34) (35) th(A)SR tsu(A)SR (34) (35) th(A)SR tdis(E) (5) td(E)S (31) td(E)R (32) VALID tdis(E)SR (30) VALID Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation) tcR (29) Ai E DQi Output ADDRESS 1 ADDRESS 6 th(A)SR (35) tw(E)SR tsu(A)SR (33) High Impedance (34) (33) (35) th(A)SR tsu(A)SR VALID td(E)S (31) td(E)R (32) VALID tdis(E)SR (30) u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U632H16 performs a STORE or RECALL. w: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles. March 31, 2006 STK Control #ML0046 9 Rev 1.0 U632H16 Test Configuration for Functional Check 5V DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 HSB E W ment of all 8 output pins DQ0 Simultaneous measure- VIL A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 relevant test measurement VIH Input level according to the Vccxy VCAP 480 VO 30 pF x HSB 255 VSS x: In measurement of tdis-times and ten-times the capacitance is 5 pF. y: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances. Capacitancee Input Capacitance Output Capacitance Conditions VCC VI f Ta Symbol = 5.0 V = VSS = 1 MHz = 25 °C Min. Max. Unit CI 8 pF CO 7 pF All pins not under test must be connected with ground by capacitors. Ordering Code Example U632H16 S C 25 G1 Type Leadfree Option G1 = Leadfree Green Package Package S = SOP28 (300 mil) Access Time 25 = 25 ns Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C Device Marking (example) Product specification ZMD U632H16SC 25 Z 0425 G1 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Internal Code STK Control #ML0046 10 Rev 1.0 March 31, 2006 U632H16 Device Operation The U632H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may occur also when VCCX rises above VSWITCH after a low power condition. RECALL cycles may also be initiated by a software sequence. SRAM READ The U632H16 performs a READ cycle whenever E and G are LOW and HSB and W are HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or HSB is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Automatic STORE During normal operation, the U632H16 will draw current from VCCX to charge up a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCCX pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX March 31, 2006 STK Control #ML0046 11 and initiate a STORE operation. Figure 1 shows the proper connection of capacitors for automatic STORE operation. The charge storage capacitor should have a capacity of 100 μF (± 20 %) at 6 V. Each U632H16 must have its own 100 μF capacitor. Each U632H16 must have a high quality, high frequency bypass capacitor of 0.1 μF connected between VCAP and VSS, using leads and traces that are as short as possible. This capacitor do not replace the normal expected high frequency bypass capacitor between the power supply voltage and VSS. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB LOW will be ignored unless at least one WRITE operation has taken place since the most recent STORE cycle. Note that if HSB is driven LOW via external circuitry and no WRITEs have taken place, the part will still be disabled until HSB is allowed to return HIGH. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. Automatic RECALL During power up an automatic RECALL takes place. At a low power condition (power supply voltage < VSWITCH) an internal RECALL request may be latched. As soon as power supply voltage exceeds again the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the U632H16 is in a WRITE state at the end of a power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W and power supply voltage. Software Nonvolatile STORE The U632H16 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U632H16 implements nonvolatile operation while remaining compatible with standard 2K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: Rev 1.0 U632H16 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence, although it is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: has been forced LOW, the WRITE will not occur and the STORE operation will begin immediately. HARDWARE-STORE-BUSY (HSB) is a high speed, low drive capability bidirectional control line. In order to allow a bank of U632H16s to perform synchronized STORE functions, the HSB pin from a number of chips may be connected together. Each chip contains a small internal current source to pull HSB HIGH when it is not being driven LOW. To decrease the sensitivity of this signal to noise generated on the PC board, it may optionally be pulled to power supply via an external resistor with a value such that the combined load of the resistor and all parallel chip connections does not exceed IHSBOL at VOL (see Figure 1 and 2). Only if HSB is to be connected to external circuits, an external pull-up resistor should be used. During any STORE operation, regardless of how it was initiated, the U632H16 will continue to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of a STORE operation, the part will be disabled until HSB actually goes HIGH. Hardware Protection 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 555 2AA 7FF 0F0 70E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL The U632H16 offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCAP < VSWITCH, all software or HSB initiated STORE operations will be inhibited. Preventing Automatic STORES Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. HSB Nonvolatile STORE The hardware controlled STORE Busy pin (HSB) is connected to an open drain circuit acting as both input and output to perform two different functions. When driven LOW by the internal chip circuitry it indicates that a STORE operation (initiated via any means) is in progress within the chip. When driven LOW by external circuitry for longer than tw(H)S, the chip will conditionally initiate a STORE operation after tdis(H)S. READ and WRITE operations that are in progress when HSB is driven LOW (either by internal or external circuitry) will be allowed to complete before the STORE operation is performed, in the following manner. After HSB goes LOW, the part will continue normal SRAM operation for tdis(H)S. During tdis(H)S, a transition on any address or control signal will terminate SRAM operation and cause the STORE to commence. Note that if an SRAM WRITE is attempted after HSB STK Control #ML0046 The PowerStore function can be disabled on the fly by holding HSB HIGH with a driver capable of sourcing 15 mA at VOH of at least 2.2 V as it will have to overpower the internal pull-down device that drives HSB LOW at the onset of an PowerStore for 50 ns. When the U632H16 is connected for PowerStore operation (see Figure 1) and VCCX crosses VSWITCH on the way down, the U632H16 will attempt to pull HSB LOW; if HSB does not actually get below VIL, the part will stop trying to pull HSB LOW and abort the PowerStore attempt. Disabling Automatic STORES If the PowerStore function is not required, then VCAP should be tied directly to the power supply and VCCX should by tied to ground. In this mode, STORE operation may be triggered through software control or the HSB pin. In either event, VCAP (Pin 1) must always have a proper bypass capacitor connected to it (Figure 2). 12 Rev 1.0 March 31, 2006 U632H16 Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL VCAP 5.0 V VSWITCH t STORE inhibit Power Up RECALL VCAP + 100 μF ± 20 % 0.1 μF Bypass VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (24) tRESTORE VCCX HSB Power Supply Power Supply VCAP 10 KΩ (optional, see description HSB nonvolatile store) 0.1 μF Bypass VSS Figure 1: Automatic STORE Operation Schematic Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCX HSB 10 KΩ (optional, see description HSB nonvolatile store) Figure 2: Disabling Automatic STORES Schematic Diagram Low Average Active Power The U632H16 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the power supply voltage level The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. March 31, 2006 STK Control #ML0046 13 Rev 1.0 U632H16 LIFE SUPPORT POLICY SIMTEK products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SIMTEK product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by SIMTEK for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However SIMTEK Corporation (SIMTEK) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. SIMTEK does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent SIMTEK’s warranty on any product beyond that set forth in its standard terms and conditions of sale. SIMTEK reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. Simtek Corporation 4250 Buckingham Drive suite 100 • Colorado Springs, CO 80907 • USA Phone: +(800)637-1667 • Fax: +(719)531-9481 • Email: [email protected] • http://www.simtek.com March 31, 2006 Change record Date Name Change 01.11.2001 Ivonne Steffens format revision and release for „Memory CD 2002“ 22.04.2002 Thomas Wolf Matthias Schniebel removing „at least“ for the 100 μF capacitor on page 11 (Automatic STORE) 20.04.2004 Matthias Schniebel adding „Leadfree Green Package“ to ordering information adding „Device Marking“ 7.4.2005 Stefan Günther adding RoHS compliance and Pb- free, 106 endurance cyclesand 100a data retention, PDIP 28 (600mil) and ESD limitations deleted, Simtek Assigned Simtek Document Control Number 1.0