Obsolete - Not Recommended for New Designs U630H16 HardStore 2K x 8 nvSRAM Features Description • The U630H16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U630H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through the state of the NE pin. The U630H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, • • • • • • • • • • • • • • • • High-performance CMOS nonvolatile static RAM 2048 x 8 bits 25, 35 and 45 ns Access Times 12, 20 and 25 ns Output Enable Access Times Hardware STORE Initiation (STORE Cycle Time < 10 ms) Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Hardware RECALL Initiation (RECALL Cycle Time < 20 ms) Unlimited RECALL cycles from EEPROM Unlimited Read and Write to SRAM Single 5 V ± 10 % Operation Operating temperature ranges: 0to70 ×C -40to85 ×C -40to125 °C(only 35 ns) QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7-HBM) RoHS compliance and Pb- free Packages:SOP28 (300 mil), PDIP28 (300/600 mil) Pin Configuration further input or output are disabled until the cycle is completed. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Pin Description NE 1 28 VCC n.c. 2 3 27 W 26 Signal Name Signal Description 4 25 24 n.c. A8 A0 - A10 Address Inputs A9 DQ0 - DQ7 Data In/Out n.c. G E Chip Enable G Output Enable W NE Write Enable VCC Power Supply Voltage VSS Ground A7 A6 A5 5 A4 6 7 23 8 PDIP 22 SOP 21 9 20 E A0 DQ0 10 11 19 DQ7 DQ6 DQ1 12 DQ2 13 14 A3 A2 A1 VSS 18 17 16 15 A10 DQ5 Nonvolatile Enable DQ4 DQ3 Top View March 31, 2006 STK Control #ML0036 1 Rev 1.0 U630H16 Block Diagram EEPROM Array 32 x (64 x 8) VCC STORE Row Decoder A5 A6 A7 A8 A9 SRAM Array 32 Rows x 64 x 8 Columns DQ0 DQ1 Input Buffers Column I/O DQ2 DQ3 DQ4 DQ5 DQ6 VSS RECALL Store/ Recall Control Column Decoder VCC G NE A0 A1 A2 A3 A4 A10 DQ7 E W Truth Table for SRAM Operations Operating Mode E NE W G DQ0 - DQ7 Standby/not selected H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratingsa Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.3 VCC+0.5 V Output Voltage VO -0.3 VCC+0.5 V Power Dissipation PD 1 W Power Supply Voltage Operating Temperature Storage Temperature C-Type K-Type A-Type Ta 0 -40 -40 70 85 85 °C °C °C Tstg -65 150 °C a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STK Control #ML0036 2 Rev 1.0 March 31, 2006 U630H16 Recommended Operating Conditions Symbol Power Supply Voltage VCC Input Low Voltage VIL Input High Voltage VIH Conditions -2 V at Pulse Width 10 ns permitted C-Type Symbol DC Characteristics Average Supply Current during STOREc Standby Supply Currentd (Cycling TTL Input Levels) ICC1 Max. Unit 4.5 5.5 V -0.3 0.8 V 2.2 VCC+0.3 V K-Type A-Type Conditions Unit Min. Operating Supply Currentb Min. Max. Min. Max. Min. Max. VCC VIL VIH = 5.5 V = 0.8 V = 2.2 V tc tc tc = 25 ns = 35 ns = 45 ns 90 80 75 95 85 80 85 - mA mA mA ICC2 VCC E W VIL VIH = 5.5 V ≥ VCC-0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 6 7 7 mA ICC(SB)1 VCC E = 5.5 V ≥ VIH tc tc tc = 25 ns = 35 ns = 45 ns 30 23 20 34 27 23 27 - mA mA mA Average Supply Current at tcR = 200 nsb (Cycling CMOS Input Levels) ICC3 VCC W VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 15 15 15 mA Standby Supply Currentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 1 1 2 mA b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2. March 31, 2006 STK Control #ML0036 3 Rev 1.0 U630H16 Symbol DC Characteristics Conditions Output High Voltage Output Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 mA = 8 mA Output High Current Output Low Current IOH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V VCC = 5.5 V VIH VIL = 5.5 V = 0V VCC = 5.5 V VOH VOL = 5.5 V = 0V Input Leakage Current High Low IIH IIL Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ Min. Max. Unit 0.4 V V 2.4 -4 mA mA 1 μA μA 8 -1 μA μA 1 -1 SRAM Memory Operations No. Switching Characteristics Read Cycle Symbol 25 35 45 Unit Alt. IEC Min. Max. Min. Max. Min. Max. 1 Read Cycle Timef tAVAV tcR 2 Address Access Time to Data Validg tAVQV ta(A) 25 35 45 ns 3 Chip Enable Access Time to Data Valid tELQV ta(E) 25 35 45 ns 4 Output Enable Access Time to Data Valid tGLQV ta(G) 12 20 25 ns 5 E HIGH to Output in High-Zh tEHQZ tdis(E) 13 17 20 ns 6 G HIGH to Output in High-Zh tGHQZ tdis(G) 13 17 20 ns 7 E LOW to Output in Low-Z tELQX ten(E) 5 5 5 ns 8 G LOW to Output in Low-Z tGLQX ten(G) 0 0 0 ns 9 Output Hold Time after Addr. Changeg tAXQX tv(A) 3 3 3 ns 10 Chip Enable to Power Activee tELICCH tPU 0 0 0 ns 11 Chip Disable to Power Standbyd, e tEHICCL tPD e: f: g: h: 25 35 25 45 35 ns 45 ns Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or coincident with E transition LOW. Measured ± 200 mV from steady state output voltage. STK Control #ML0036 4 Rev 1.0 March 31, 2006 U630H16 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f tcR Ai (1) Address Valid ta(A) (2) DQi Output Data Valid Previous Data Valid Output tv(A) (9) Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g tcR (1) Ai Address Valid ta(A) (2) E ta(E) (3) tdis(E) ten(E) (7) G (5) ta(G) (4) tdis(G) (6) ten(G) (8) DQi High Impedance tPU (10) ACTIVE Output ICC Output Data Valid tPD (11) STANDBY No. Switching Characteristics Write Cycle Symbol 25 35 45 Unit Alt. #1 Alt. #2 12 Write Cycle Time tAVAV 13 Write Pulse Width tWLWH 14 Write Pulse Width Setup Time tAVAV IEC tcW 25 35 45 ns tw(W) 20 30 35 ns tWLEH tsu(W) 20 30 35 ns tsu(A) 0 0 0 ns 20 30 35 ns tsu(E) 20 30 35 ns tELEH tw(E) 20 30 35 ns 15 Address Setup Time tAVWL tAVEL 16 Address Valid to End of Write tAVWH tAVEH tsu(A-WH) 17 Chip Enable Setup Time tELWH 18 Chip Enable to End of Write Min. Max. Min. Max. Min. Max. 19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 12 18 20 ns 20 Data Hold Time after End of Write tWHDX tEHDX th(D) 0 0 0 ns 21 Address Hold after End of Write tWHAX tEHAX th(A) 0 0 0 ns 22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 23 W HIGH to Output in Low-Z tWHQX ten(W) March 31, 2006 STK Control #ML0036 5 10 5 13 5 Rev 1.0 15 5 ns ns U630H16 Write Cycle #1: W-controlledj tcW Ai (12) Address Valid tsu(E) (17) th(A) (21) E tsu(A-WH) (16) tw(W) (13) W tsu(A) tsu(D) (19) (15) DQi Input DQi Output tdis(W) (22) Previous Data th(D) (20) Input Data Valid ten(W) (23) High Impedance Write Cycle #2: E-controlledj tcW (12) Ai E tsu(A) (15) Address Valid tw(E) (18) tsu(W) (14) W th(D) (20) tsu(D) (19) DQi Input th(A) (21) ten(E) (7) tdis(W) (22) DQi Input Data Valid High Impedance Output undefined i: j: L- to H-level H- to L-level If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W and NE must be > VIH during address transitions. STK Control #ML0036 6 Rev 1.0 March 31, 2006 U630H16 Nonvolatile Memory Operations No. 24 k: Symbol STORE Cycle Inhibit and Automatic Power Up RECALL Min. Alt. Max. Unit 650 μs 4.5 V IEC Power Up RECALL Durationk, e tRESTORE Low Voltage Trigger Level VSWITCH 4.0 tRESTORE starts from the time VCC rises above VSWITCH. STORE Cycle Inhibit and Automatic Power Up RECALL VCC 5.0 V VSWITCH t STORE inhibit Power Up RECALL (24) tRESTORE Mode Selection E W G NE Mode Power Notes L H L L Nonvolatile RECALL Active l L L H L Nonvolatile STORE ICC2 L L L H L H L No operation Active * * H or L l: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. March 31, 2006 STK Control #ML0036 7 Rev 1.0 U630H16 STORE Cycles Symbol Min. No. STORE Cycle W-controlled Alt. IEC Max. Unit 10 ms 25 STORE Cycle Timem tWLQX td(W)S 26 STORE Initiation Cycle Timen tWLNH tw(W)S 25 ns 27 Output Disable Setup to NE Fall tGHNL tsu(G)S 5 ns 28 NE Setup tNLWL tsu(N)S 5 ns 29 Chip Enable Setup tELWL tsu(E)S 5 ns STORE Cycle: W-controlledo NE G tsu(G)S tsu(N)S (27) tw(W)S (26) (28) W tsu(E)S (29) E td(W)S (25) DQi High Impedance Output Symbol No. STORE Cycle E-controlled Min. Alt. IEC Max. Unit 10 ms 30 STORE Cycle Time tELQXS td(E)S 31 STORE Initiation Cycle Time tELNHS tw(E)S 25 ns 32 Output Disable Setup to E Fall tGHEL tsu(G)S 5 ns 33 NE Setup tNLEL tsu(N)S 5 ns 34 Write Enable Setup tWLEL tsu(W)S 5 ns STORE Cycle: E-controlledo tsu(N)S NE G (33) tsu(G)S (32) tsu(W)S (34) W tw(E)S (31) E DQi Output td(E)S (30) High Impedance STK Control #ML0036 8 Rev 1.0 March 31, 2006 U630H16 RECALL Cycles Symbol No. RECALL Cycle NE-controlled Min. Alt. IEC Max. Unit 20 μs 35 RECALL Cycle Timep tNLQX td(N)R 36 RECALL Initiation Cycle Timeq tNLNH tw(N)R 25 ns 37 Output Enable Setup tGLNL tsu(G)R 5 ns 38 Write Enable Setup tWHNL tsu(W)R 5 ns 39 Chip Enable Setup tELNL tsu(E)R 5 ns 40 NE Fall to Output Inactive tNLQZ tdis(N)R 25 ns Max. Unit 20 μs RECALL Cycle: NE-controlledo tw(N)R (36) NE tsu(G)R G (37) W tsu(W)R (38) tdis(N)R (40) E tsu(E)R (39) td(N)R (35) High Impedance DQi Output Symbol No. RECALL Cycle E-controlled Min. Alt. IEC 41 RECALL Cycle Time tELQXR td(E)R 42 RECALL Initiation Cycle Time tELNHR tw(E)R 25 ns 43 NE Setup tNLEL tsu(N)R 5 ns 44 Output Enable Setup tGLEL tsu(G)R 5 ns 45 Write Enable Setup tWHEL tsu(W)R 5 ns RECALL Cycle: E-controlledo tsu(N)R NE (43) tsu(G)R (44) G W tsu(W)R (45) E DQi tw(E)R (42) td(E)R (41) High Impedance Output March 31, 2006 STK Control #ML0036 9 Rev 1.0 U630H16 Symbol Min. No. RECALL Cycle G-controlled Alt. IEC Max. Unit 20 μs 46 RECALL Cycle Time tGLQXR td(G)R 47 RECALL Initiation Cycle Time tGLNH tw(G)R 25 ns 48 NE Setup tNLGL tsu(N)R 5 ns 49 Write Enable Setup tWHGL tsu(W)R 5 ns 50 Chip Enable Setup tELGL tsu(E)R 5 ns RECALL Cycle: G-controlledo, r tsu(N)R NE (48) tw(G)R (47) G W tsu(W)R (49) tsu(E)R (50) E td(G)R (46) DQi High Impedance Output m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by V CC < VSWITCH (STORE inhibit). n: Once tw(W)S has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to terminate the STORE initiation cycle. o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated. For E-controlled STORE during tw(E)S W, G, NE have to be static. p: Measured with W and NE both HIGH, and G and E LOW. q: Once tw(N)R has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. r: If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL. STK Control #ML0036 10 Rev 1.0 March 31, 2006 U630H16 Test Configuration for Functional Check 5V NE E W G 480 ment of all 8 output pins VIL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Simultaneous measure- VIH A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 relevant test measurement Input level according to the VCCt VO 30 pF s 255 VSS s: In measurement of tdis-times and ten-times the capacitance is 5 pF. t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances. Capacitancee Conditions VCC VI f Ta Input Capacitance Output Capacitance Symbol = 5.0 V = VSS = 1 MHz = 25 °C Min. Max. Unit CI 8 pF CO 7 pF All pins not under test must be connected with ground by capacitors. Ordering Code Example U630H16 S C 25 G1 Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package Package D u= PDIP28 (300 mil) D1 = PDIP28 (600 mil) S = SOP28 (300 mil) Access Time 25 = 25 ns 35 = 35 ns (C/K Type on special request) 45 = 45 ns Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C A = -40 to 125 °C (only 35 ns and SOP28 package) u: on special request Device Marking (example) Product specification ZMD U630H16SC 25 Z 0425 G1 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Internal Code March 31, 2006 STK Control #ML0036 11 Rev 1.0 U630H16 Device Operation The U630H16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0 - 7 pins are tristated until the cycle is completed. If E and G are LOW and W and NE are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, indicating the end of the STORE. Hardware Nonvolatile RECALL SRAM READ The U630H16 performs a READ cycle whenever E and G are LOW while W and NE are HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or NE is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW and NE is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The U630H16 is a high speed memory and therefore must have a high frequency bypass capacitor of approximately 0.1 μF connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise problems. Hardware Nonvolatile STORE A STORE cycle is performed when NE, E and W are LOW while G is HIGH. While any sequence to achieve this state will initiate a STORE, only W initiation and E initiation are practical without risking an unintentional SRAM WRITE that would STK Control #ML0036 A RECALL cycle is performed when E, G and NE are LOW while W is HIGH. Like the STORE cycle, RECALL is initiated when the last of the three clock-signals goes to the RECALL state. Once initiated, the RECALL cycle will take „RECALL Cycle Time“ to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on some control pins to cause a RECALL, preventing inadvertend multi-triggering. Automatic Power Up RECALL On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below VSWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after VCC exceeds VSWITCH. If the U630H16 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W and system VCC. Hardware Protection The U630H16 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the U630H16 offers hardware protection through VCC Sense. When VCC < VSWITCH the externally initiated STORE operation will be inhibited. 12 Rev 1.0 March 31, 2006 U630H16 Low Average Active Power The U630H16 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. March 31, 2006 STK Control #ML0036 13 Rev 1.0 U630H16 LIFE SUPPORT POLICY Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. March 31, 2006 Change record Date/Rev Name Change 01.11.2001 Ivonne Steffens format revision and release for „Memory CD 2002“ 11.08.2003 Matthias Schniebel adding A-Type with ICC1 = 85mA; ICC2 = 7mA; ICC3 = 15mA; ICC(SB) = 2mA; ICC(SB)1 = 27 mA 20.04.2004 Matthias Schniebel adding „Leadfree Green Package“ to ordering information adding „Device Marking“ 7.4.2005 Stefan Günther changing to 106 endurance cycles and 100a data retention, delete ESD classes, change ordering code, PDIP 300 on special request, RoHS and Pb- free added, C/K limitation for PDIP deleted 31.3.2006 Troy Meester changed to obsolete status Simtek Assigned Simtek Document Control Number 1.0