NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM General Description Features The NMC27C32B is a 32k UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. The NMC27C32B is designed to operate with a single a 5V power supply with g 10% tolerance. The NMC27C32B is packaged in a 24-pin dual-in-line package with a quartz window. The quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written electrically into the device by following the programming procedure. This EPROM is fabricated with National’s proprietary, time proven CMOS double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability. Y Y Y Y Y Y Y Y Low CMOS power consumption Ð Active Power: 55 mW Max Ð Standby Power: 0.55 mW Max Extended temperature range, b40§ C to a 85§ C Fast and reliable programming TTL, CMOS compatible inputs/outputs TRI-STATEÉ output Manufacturer’s identification code for automatic programming High current CMOS level output drivers Compatible with NMOS 2732 Block Diagram Pin Names A0 – A11 Addresses CE Chip Enable OE Output Enable VPP Programming Voltage O0 –O7 Outputs VCC Power Supply GND Ground TL/D/8827 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/D/8827 RRD-B30M17/Printed in U. S. A. http://www.national.com NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM December 1996 Connection Diagram 27C256 27256 27C128 27128 27C64 2764 27C16 2716 VPP VPP VPP A12 A12 A12 A7 A7 A7 A7 A6 A6 A6 A5 A5 A4 27C16 2716 NMC27C32B Dual-In-Line Package 27C64 2764 27C128 27128 27C256 27256 VCC VCC VCC PGM PGM A14 VCC NC A13 A13 A6 A8 A8 A8 A8 A5 A5 A9 A9 A9 A9 A4 A4 A4 VPP A11 A11 A11 A3 A3 A3 A3 OE OE OE OE A2 A2 A2 A2 A10 A10 A10 A10 A1 A1 A1 A1 CE CE CE CE A0 A0 A0 A0 O7 O7 O7 O7 O0 O0 O0 O0 O6 O6 O6 O6 O1 O1 O1 O1 O5 O5 O5 O5 O2 O2 O2 O2 O4 O4 O4 O4 GND GND GND GND O3 O3 O3 O3 TL/D/8827 – 2 Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32B pins. Order Number NMC27C32BQ See NS Package Number J24AQ Commercial Temp Range (0§ C to a 70§ C) VCC e 5V g 10% Parameter/Order Number Access Time (ns) NMC27C32BQ150 150 NMC27C32BQ200 200 NMC27C32BQ250 250 Extended Temp Range (b40§ C to a 85§ C) VCC e 5V g 10% Parameter/Order Number NMC27C32BQE200 http://www.national.com Access Time (ns) 200 2 Absolute Maximum Ratings (Note 1) OE/VPP Supply and A9 Voltage with Respect to Ground If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Under Bias b 40§ C to a 85§ C Storage Temperature VCC Supply Voltage with Respect to Ground b 65§ C to a 150§ C a 6.5V to b 0.6V All Output Voltages with Respect to Ground (Note 9) VCC a 1.0V to GNDb0.6V 1.0W 300§ C Operating Conditions (Note 6) a 7.0V to b 0.6V All Input Voltages except A9 and OE/VPP with Respect to Ground (Note 9) a 14.0V to b 0.6V Power Dissipation Lead Temperature (Soldering, 10 sec.) Temperature Range NMC27C32BQ150, 200, 250 NMC27C32BQE200 0§ C to a 70§ C b 40§ C to a 85§ C VCC Power Supply a 5V g 10% READ OPERATION DC Electrical Characteristics Symbol Parameter Conditions Min Typ Max 0.01 1 Units mA 10 mA 0.01 1 mA 5 20 mA 3 10 mA CE e VIH 0.1 1 mA CE e VCC 0.5 100 mA ILI Input Load Current VIN e VCC or GND IPP OE/VPP Load Current OE/VPP e VCC or GND ILO Output Leakage Current VOUT e VCC or GND, CE e VIH ICC1 VCC Current (Active) TTL Inputs CE e VIL, f e 5 MHz Inputs e VIH or VIL, I/O e 0 mA ICC2 VCC Current (Active) CMOS Inputs CE e GND, f e 5 MHz Inputs e VCC or GND, I/O e 0 mA ICCSB1 VCC Current (Standby) TTL Inputs ICCSB2 VCC Current (Standby) CMOS Inputs VIL Input Low Voltage b 0.2 0.8 V VIH Input High Voltage 2.0 VCC a 1 V VOL1 Output Low Voltage IOL e 2.1 mA VOH1 Output High Voltage IOH e b400 mA VOL2 Output Low Voltage IOL e 10 mA VOH2 Output High Voltage IOH e b10 mA 0.45 2.4 V V 0.1 V VCC b 0.1 V AC Electrical Characteristics NMC27C32B Symbol Parameter Conditions Q150 Min Max Q200, QE200 Min Max Q250 Min Units Max tACC Address to Output Delay CE e OE e VIL 150 200 250 ns tCE CE to Output Delay 150 200 250 ns tOE OE to Output Delay OE e VIL CE e VIL 60 60 70 ns tDF OE High to Output Float tCF CE High to Output Float tOH Output Hold from Addresses, CE or OE, Whichever Occurred First CE e VIL OE e VIL 0 50 0 60 0 70 ns 0 50 0 60 0 60 ns CE e OE e VIL 0 3 0 0 ns http://www.national.com Capacitance TA e a 25§ C, f e 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN1 Input Capacitance except OE/VPP VIN e 0V 6 12 pF CIN2 OE/VPP Input Capacitance VIN e 0V 16 20 pF COUT Output Capacitance VOUT e 0V 9 12 pF AC Test Conditions Output Load Input Rise and Fall Times Input Pulse Levels 1 TTL Gate and CL e 100 pF (Note 8) s 5 ns 0.45V to 2.4V Timing Measurement Reference Level Inputs Outputs 0.8V and 2V 0.8V and 2V AC Waveforms (Note 7) TL/D/8827 – 3 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC b tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) b 0.10V; Low to TRI-STATE, the measured VOL1 (DC) a 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC a 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL e 1.6 mA, IOH e b 400 mA. CL: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to b 2.0V for 20 ns Max, except for OE/VPP which cannot exceed b 0.2V. Note 10: Typical values are for TA e 25§ C and nominal supply voltages. http://www.national.com 4 Programming Characteristics (Notes 1, 2, 3 & 4) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 tOES OE Setup Time 1 ms tDS Data Setup Time 1 ms tVCS VCC Setup Time 1 ms tAH Address Hold Time 0 ms tDH Data Hold Time tCF Chip Enable to Output Float Delay tPW Program Pulse Width tOEH OE Hold Time tDV Data Valid from CE tPRT OE Pulse Rise Time During Programming tVR VPP Recovery Time IPP VPP Supply Current During Programming Pulse ICC VCC Supply Current TA Temperature Ambient 20 25 VCC Power Supply Voltage 6.0 6.25 6.5 V VPP Programming Supply Voltage 12.5 12.75 13.0 tFR Input Rise, Fall Time VIL Input Low Voltage VIH Input High Voltage 2.4 tIN Input Timing Reference Voltage 0.8 2.0 V tOUT Output Timing Reference Voltage 0.8 2.0 V ms 1 OE e VIL ms 0 95 100 60 ns 105 ms 1 ms OE e VIL 250 ns 50 ns 1 ms CE e VIL, OE e VPP 30 mA 10 mA 30 §C 5 V ns 0.0 0.45 4.0 V V Programming Waveforms TL/D/8827 – 4 Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings. 5 http://www.national.com Fast Programming Algorithm Flow Chart (Note 4) TL/D/8827 – 5 FIGURE 1 http://www.national.com 6 Functional Description common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. DEVICE OPERATION The six modes of operation of the NMC27C32B are listed in Table I. A single 5V power supply is required in the read mode. All inputs are TTL levels except for OE/VPP during programming. In the program mode the OE/VPP input is pulsed from a TTL low level to 12.75V. Programming CAUTION: Exceeding 14V on pin 20 OE/VPP will damage the NMC27C32B. Initially, and after each erasure, all bits of the NMC27C32B are in the ‘‘1’’ state. Data is introduced by selectively programming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The NMC27C32B is in the programming mode when OE/VPP is at 12.75V. It is required that at least a 0.1 mF capacitor be placed across VCC and ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE input. A program pulse must be applied at each address location to be programmed. The NMC27C32B is programmed with the Fast Programming Algorithm shown in Figure 1 . Each Address is programmed with a series of 100 ms pulses until it verifies good, up to a maximum of 25 pulses. Most memory cells will Program with a single 100 ms pulse. Read Mode The NMC27C32B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC – tOE. The sense amps are clocked for fast access time. VCC should therefore be maintained at operating voltage during read and verify. If VCC temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to ensure proper output data. Standby Mode The NMC27C32B has a standby mode which reduces the active power dissipation by 99%, from 55 mW to 0.55 mW. The NMC27C32B is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Note: Some programmer manufactures due to equipment limitation may offer interactive program Algorithm (Shown in Figure 2 ). Output OR-Tying Because EPROMs are usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connection. The 2-line control function allows for: a. The lowest possible memory power dissipation, and b. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a The NMC27C32B must not be programmed with a DC signal applied to the CE input. Programming multiple NMC27C32Bs in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled NMC27C32B may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE input programs the paralleled NMC27C32B. TABLE I. Mode Selection Pins Mode CE (18) OE/VPP (20) VCC (24) Outputs (9 – 11, 13 – 17) Read VIL VIL 5V DOUT Standby VIH Don’t Care 5V Hi-Z Program VIL 12.75V 6.25V DIN Program Verify VIL VIL 6.25V DOUT Program Inhibit VIH 12.75V 6.25V Hi-Z Output Disable Don’t Care VIH 5V Hi-Z 7 http://www.national.com Functional Description (Continued) erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. Program Inhibit Programming multiple NMC27C32B in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE) of the parallel NMC27C32B may be common. A TTL low level program pulse applied to an NMC27C32B’s CE input with OE/VPP at 12.75V will program that NMC27C32B. A TTL high level CE input inhibits the other NMC27C32B from being programmed. The recommended erasure procedure for the NMC27C32B is exposure to short wave ultraviolet light which has a wavelength of 2537Ð. The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15 W-sec/cm2. The NMC27C32B should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table III shows the minimum NMC27C32B erasure time for various light intensities. An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. Program Verify A verify should be performed on the programmed bit to determine whether they were correctly programmed. The verify is accomplished with OE/VPP and CE at VIL. Data should be verified tDV after the falling edge of CE. MANUFACTURER’S IDENTIFICATION CODE The NMC27C32B has a manufacturer’s identification code to aid in programming. The code, shown in Table II, is two bytes wide and is stored in a ROM configuration on the chip. It identifies the manufacturer and the device type. The code for the NMC27C32B is, ‘‘8F01’’, where ‘‘8F’’ designates that it is made by National Semiconductor, and ‘‘01’’ designates a 32k part. The code is accessed by applying 12.0V g 0.5V to address pin A9. Addresses A1–A8, A10–A11, CE, and OE are held at VIL. Address A0 is held at VIL for the manufacturer’s code, and at VIH for the device code. The code is read out on the 8 data pins. Proper code access is only guaranteed at 25§ C g 5§ C. The primary purpose of the manufacturer’s identification code is automatic programming control. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designerÐthe standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. ERASURE CHARACTERISTICS The erasure characteristics of the NMC27C32B are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ð– 4000Ð range. After programming, opaque labels should be placed over the NMC27C32B’s window to prevent unintentional TABLE II. Manufacturer’s Identification Code A0 (8) O7 (17) O6 (16) O5 (15) O4 (14) O3 (13) O2 (11) O1 (10) O0 (9) Hex Data Manufacturer Code VIL 1 0 0 0 1 1 1 1 8F Device Code VIH 0 0 0 0 0 0 0 1 01 Pins TABLE III. Minimum NMC27C32B Erasure Time http://www.national.com Light Intensity (mW/cm2) Erasure Time (Minutes) 15,000 20 10,000 25 5,000 50 8 9 http://www.national.com NMC27C32B 32,768-Bit (4096 x 8) CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number NMC27C32BQ NS Package Number J24AQ LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Email: support @ nsc.com http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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