AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET DECEMBER 2005 5303B can be configured to support general-purpose A/V interface (YPrPb, SVHS, and CVBS) for TVs, DVD recorders, digital set-top boxes, and PVRs. Video and audio gains are programmable. All switching and function settings are controlled via I2C. Configurable Device Address • • Mux Gn_out Blue or Pb Bl1 Bl2 Bl3 Mux Bl_out Red or Pr or C Rd1 Rd2 Rd3 Mux Rd_out CVBS1 CVBS2 CVBS3 Picture-in-Picture Application Expandable Multi-function Inputs (up to 6 channels) +5V, +12V Package • 48-QFN TV 3-SCART Interface TV A/V Interface (YPrPb/SVHS/CVBS) DVD Recorder A/V Interface Digital Set-Top Box A/V Interface PVR A/V Interface Page: 1 of 16 © 2005 TERIDIAN Semiconductor Corporation Gain CVBS_out Mux R1 R2 R3 Mux L1 L2 L3 Mux SCLK SDATA APPLICATIONS Gain Gn1 Gn2 Gn3 Power Supply • FB_out Green or Y or CVBS CVBS or Y Power Down Mode Mux Func_out 0/6dB R_out L_out Vref Serial Port Support Circuits Pdwn Rbias Tgen GND I2C Control FB1 FB2 FB3 0V/6V/12V GND • 3:1 video and audio mux Programmable gain video drivers 0/6 dB audio drivers TV SCART Interface RGB+FB, SVHS and CVBS video modes 12V TV Function pins mux General Purpose A/V Interface YPrPb, SVHS and CVBS video modes Mux GND • • • • Func1 Func2 Func3 GND Three Input A/V Interface VDD Dev_Addr Blue, CVBS, R, L, Fast Blanking, and TV Function) and also supports SCART SVHS video mode. In addition, the FEATURES VCC The AVPro® 5303B device is a universal three input A/V switch interface IC designed for TV and general-purpose A/V applications. The device provides interfaces for three full sets of TV SCART input signals (Red, Green, VCC VCC DESCRIPTION Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Functional Description The 5303B is an analog A/V interface IC designed for TV and general-purpose A/V applications. The device accepts up to three sets of SCART input signals (Red, Green, Blue, CVBS, R, L, Fast Blanking, and TV Function). By way of 3:1 mux, SCART 1, 2, or 3 signals can be selected at the device’s output pins. The 5303B supports four SCART video modes: RGB/CVBS, RGBonly, CVBS-only and SVHS. The RGB and CVBS video driver gains are programmable from 2 to 1.4 in 0.2 steps, and the R/L audio driver gain can be 0dB or 6dB. The R/L audio drivers can accept signals from 0.5Vrms to 2Vrms. For general-purpose A/V applications, video switches and drivers can be configured to support component video (YPrPb), S-Video (SVHS), and composite video (CVBS) signals. All switching and programmable functions of the device are controlled through a standard I2C serial interface DC Restore for RGB, Y, and CVBS: The device will generate a DC restore level on each video output based on timing referenced to a horizontal sync pulse. When the sync pulse is detected, the DC restore circuit will act to position the blank level to 1.2V at the respective RGB, Y, or CVBS output pin(s). DC Restore for SVHS and YPrPb: In the SVHS mode, the CVBS pin is used as Luma input and the Red pin is used as Chroma input. The DC restore function for Luma signal is equivalent to CVBS signal. The DC restore circuit will position the output blank level to 1.2V at the respective Luma output pin. For the Chroma input, the on-chip clamp circuit will be used to position the output mid-scale DC level to 1.8V. In the YPrPb mode, the mid-scale DC level for Pr and Pb outputs will also be at 1.8V. A/V Input Source Selection The device accepts up to three sets of A/V input signals. Bits 0 & 1 of Register 0 determine which of the sets will be present at the device’s output pins. Video Mode Selection The device supports four video modes for TV SCART applications: RGB/CVBS, RGB-only, CVBS-only, and SVHS. Bits 2, 3, & 4 set the active video mode. RGB/CVBS video mode is a default mode. For generalpurpose A/V applications, the device supports YPrPb/CVBS and CVBS/SVHS video modes. RGB Gain The gain of the RGB outputs can be adjusted to one of four different levels. Bits 0 & 1 Register 1 set the gain of the RGB output amplifiers according to the following table: Bit 1 Bit 0 0 0 1 1 0 1 0 1 RGB Amplifier Gain Gain = 2 V/V Gain = 1.8 V/V Gain = 1.6 V/V Gain = 1.4 V/V CVBS Gain The gain of the CVBS output can be adjusted to one of four different levels. Bits 2 & 3 Register 1 set the gain of the CVBS output amplifier according to the following table: Bit 3 Bit 2 0 0 1 1 0 1 0 1 CVBS Amplifier Gain Gain = 2 V/V Gain = 1.8 V/V Gain = 1.6 V/V Gain = 1.4 V/V Audio Gain The gain of the R/L audio amplifiers can be set to either 0dB or 6dB. Bit 4 of Register 1 sets the gain of the amplifiers according to the following table: Bit 4 0 1 Page: 2 of 16 R/L Amplifier Gain Gain = 0 dB Gain = 6 dB © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Serial Port Definition TV Function Input The TV Function feature generally supports three-level logic signal required for SCART TV Function Switching: Input Voltage TV Function Switching Mode 0-2V 4.5-7V 9.5-12V Broadcast TV 16:9 Peritelevision Reproduction Normal Peritelevision Reproduction In the AVPro® 5303B device, the TV Function feature works in pass through mode only. The three inputs, Func1, Func2 and Func3 support the pass through mode of the TV Function feature. A 100kΩ load is recommended for typical operation at the Func_out pin. Fast Blanking (FB) Input The FB1, FB2 and FB3 inputs support two-level logic signal required for SCART Fast Blanking: Logic Input Voltage 0 1 0-0.4V 1-3V Fast Blanking Mode Chip Power Down The whole chip (except negligible on-chip biasing circuit) can be powered down by setting Pdwn pin to high (5V). Configurable Device Address Dev_Addr pin sets the address of the 5303B device. There are two possible device addresses that the 5303B can have: 1001000x 1010000x Description Dev_Addr pin left OPEN (Default) Dev_Addr pin connected to GND In the case of picture-in-picture or 6-channel inputs application, a second device is required to have a different address from the first or original device. This can be done by connecting the Dev_Addr pin of the second device to GND while leaving the Dev_Addr pin of the first device OPEN or unconnected. Page: 3 of 16 The 5303B includes a read register in which the upper four bits identify the specific chip within the AVPro® family. This allows a single application platform and software to work with a wide variety of AVPro® chips. The ID code for the 5303B is 0010. Data Transfers CVBS Active RGB Active Following a 3:1 input mux stage is a unity-gain FB video driver. The FB video driver is designed to match the video drivers of RGB in bandwidth and time delay and can support a minimum load of 300Ω. Device Address Internal functions of the device are monitored and controlled by a standard inter-IC (I2C)bus with data being transferred MSB first on the rising edge of the clock. The serial port operates in a slave mode only and can be written to or read from. The device uses 7-bit addressing, and does not support 10-bit addressing mode. The write register data is sent sequentially, such that if register 1 is to be programmed, then registers 0 and 1 need to be sent. If only register 0 needs to be programmed, then only registers 0 data needs to be sent. It will support standard and fast bus speed. The default address of the device is 1001000x (1001000 for Write and 10010001 for Read). A data transfer starts when the SDATA pin is driven from HIGH to LOW by the bus master while the SCLK pin is HIGH. On the following eight clock cycles, the device receives the data on the SDATA pin and decodes that data to determine if a valid address has been received. The first seven bits of information are the address with the eighth bit indicating whether the cycle is a read (bit is HIGH) or a write (bit is LOW). If the address is valid for this device, on the falling SCLK edge of the eighth bit of data, the device will drive the SDATA pin low and hold it LOW until the next rising edge of the SCLK pin to acknowledge the address transfer. The device will continue to transmit or receive data until the bus master has issued a stop by driving the SDATA pin from LOW to HIGH while the SCLK pin is held HIGH Write Operation: When the read/write bit (LSB) is LOW and a valid address is decoded, the device will receive data from the SDATA pin. The device will continue to latch data into the registers until a stop condition is detected. The device generates an acknowledge after each byte of data written. Read Operation: When the read/write bit (LSB) is HIGH and a valid address is decoded, the device will transmit the data from the internal register on the following eight SCLK cycles. Following the transfer of the register data and the acknowledge from the master, the device will release the data bus. Reset: At power-up the serial port defaults to the states indicated in boldface type. The device also responds to the system level reset that is transmitted through the serial port. When the master sends the address 00000000 followed by the data 00000110, the device resets to the default condition. © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET SERIAL PORT REGISTER TABLES Read register Device Address = 10010001 (10100001 when Dev_Addr = 0) Function Not Used Bits xxxx0000 Description Not Used Device ID Code 0010xxxx This code identifies the device type as the 5303B. Write Registers: Device Address = 10010000 (10100000 when Dev_Addr = 0). Bold indicates default setting. Register 0: Signal Source Selection Register 0: Video Mode BLUE Chroma/Pr/Pb enable Bits xxxxxxx0 RED Chroma/Pr/Pb enable xxxxxxx1 xxxxxx0x FB_OUT set to 0V xxxxxx1x xxxxx0xx GN_OUT set to 0V xxxxx1xx xxxx0xxx xxxx1xxx Audio/FUNC Source Selection Description Blue input set for Chroma/Pr/Pb Blue input set for Y or Blue(DC Restore) Red input set for Chroma/Pr/Pb Red input set for Y or Red(DC Restore) FB_OUT for normal operation FB_OUT SET TO 0V GN_OUT for normal operation GN_OUT SET TO 0V Bits 00xxxxxx ROUT R1 LOUT L1 FUNC_OUT 01xxxxxx R2 L2 FUNC2 10xxxxxx R3 L3 FUNC3 11xxxxxx Not Used Not Used Not Used FUNC1 Register 1: Audio/Video Gain Control Function RBG Gain Function CVBS Gain Bits xxxxxx00 Description 2 xxxxxx01 xxxxxx10 xxxxxx11 1.8 1.6 1.4 Bits xxxx00xx Description 2 1.8 1.6 1.4 Xxxx01xx Xxxx10xx Xxxx11xx Function Audio Gain Bits xxx0xxxx xxx1xxxx Page: 4 of 16 Description 0 dB 6 dB © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Register 2: XXXX XXXX. User must write to register 2 (contents written are a don’t care) prior to writing to register 3. Register 3: Video Signal Source Selection Video Mode RED Source Selection Bits xxxxxx00 RED_OUT RD1 RD2 RD3 0V xxxxxx01 xxxxxx10 xxxxxx11 Video Mode CVBS Source Selection Bits xxxx00xx CVBS_OUT CVBS1 CVBS2 CVBS3 0V xxxx01xx xxxx10xx xxxx11xx Video Mode BLUE Source Selection Bits xx00xxxx BLUE_OUT BL1 BL2 BL3 0V xx01xxxx xx10xxxx xx11xxxx Video Mode GREEN Source Selection Page: 5 of 16 Bits 00xxxxxx GN_OUT GN1 FB_OUT FB1 01xxxxxx GN2 FB2 10xxxxxx GN3 FB3 11xxxxxx Not Used Not Used © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET PIN DESCRIPTIONS Name Analog Pins Func1 Func2 Func3 FB1 FB2 FB3 Gn1 Gn2 Gn3 Bl1 Bl2 Bl3 Rd1 Rd2 Rd3 CVBS1 CVBS2 CVBS3 R1 R2 R3 L1 L2 L3 Func_out FB_out Gn_out Bl_out Rd_out CVBS_out R_out L_out Page: 6 of 16 Pin Type 25 24 23 48 5 36 2 7 38 3 8 39 1 6 37 47 4 35 14 16 18 15 17 19 22 45 41 40 44 46 21 13 I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O Description TV Function Input 1 TV Function Input 2 TV Function Input 3 Fast Blanking Input 1 Fast Blanking Input 2 Fast Blanking Input 3 Green Input 1 Green Input 2 Green Input 3 Blue Input 1 Blue Input 2 Blue Input 3 Red Input 1 Red Input 2 Red Input 3 CVBS Input 1 CVBS Input 2 CVBS Input 3 Right Audio Input 1 Right Audio Input 2 Right Audio Input 3 Left Audio Input 1 Left Audio Input 2 Left Audio Input 3 TV Function Output Fast Blanking Output Green Output Blue Output Red Output CVBS Output Right Audio Output Left Audio Output © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET PIN DESCRIPTIONS (Continued) Name Pin Type Description Digital Pins Dev_Addr 29 I Device Address Input Pdwn 28 I Chip Power Down SCLK 30 I Serial Clock Input: This pin accepts a serial port clock input signal. SDATA 31 I/O Serial Data Input/Output that can receive or transmit serial data. Power/Ground Pins VCC 9, 33, 43 - +5 VDC power supply pins. VDD 27 - +12 VDC power supply pin for function switching circuits. Vref 20 - Internal voltage reference, bypass pin. Add capacitor 0.1µF(1.0 µF for better PSRR ) to ground. GND 20, 26, 34, 42 - Ground for all blocks. Rbias 11 - Bias point of internal current generator. Add resistor 10.0kΩ(+ 1%) to ground. Tgen 32 - Reference point for internal timing circuit. Add capacitor 470pF to ground. N/C 12 - No connect. Page: 7 of 16 © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond the maximum ratings may damage the device PARAMETER Storage temperature RATING -55 to 150 °C +125 °C -0.3 V < VCC < 6V -0.3 V < VDD < 13V -0.3V to VCC+0.3 V -0.3V to VCC+0.3 V -0.3 V < VDD < 13V -0.3 V < VDD < 13V Junction operating temperature 5V supply voltage pins 12V supply pin Voltage applied to Digital and Video Inputs Voltage applied to video pins Voltage applied to audio pins Voltage applied to FNC pin (input) SPECIFICATIONS: Unless otherwise specified: 0° < Ta < 70 °C; power supplies VCC = +5.0 V ±5%, VDD = 12.0 V ±5%. CONDITION Parameter Operating Characteristics Power Supply Currents (Default register setting) PSRR Switch time All outputs not loaded VCC (+5 VDC) VDD (+12 VDC) Pdwn = 1 VCC (+5 VDC) VDD (+12 VDC) fin = 100 Hz, 0.3 Vpp on VCC/ VDD From serial data acknowledge Wake time From Power Down Condition Power Supply Currents (Default register setting) MIN MAX UNIT 16.5 4 20 5 mA mA 2.3 10 3 100 mA µA dB NOM 40 2.0 µs 5 µs 2 Serial Port Timing (Set by I C controller) SCLK Input Frequency SCLK LOW time (tCL) 1.3 SCLK HIGH time (tCH) 0.6 Rise time (tRT) Fall time (tFT) Data set-up time* (tDSU) Data hold time* (tDH) Start set-up time (tSSU) 400 SCLK and SDATA SCLK and SDATA SDATA change to SCLK HIGH SCLK LOW to SDATA change kHz µs 300 300 µs ns ns ns ns 100 30 0.6 µs Start hold time (tSH) 0.6 µs Stop set-up time (tPSU) 0.6 Glitch rejection maximum pulse on SCLK and/or SDATA * These specifications also apply to an acknowledge generated by the device. Page: 8 of 16 © 2005 TERIDIAN Semiconductor Corporation 50 µs ns Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET SPECIFICATIONS (continued) Digital I/O Characteristics (SCLK, SDATA, Pdwn, Dev_Addr) CONDITION Parameter High level input voltage Low level input voltage High level input current (SCLK, Vin = Vcc - 1.0V Pdwn, Dev_Addr) High level input current (SDATA) Vin = Vcc - 1.0V Low level input current (SCLK, Vin = 1.0V Pdwn) Low level input current Vin = 1.0V (Dev_Addr) Low level input current (SDATA) Vin = 1.0V Low level output voltage (SDATA) IOL = 3 mA Fall time (tFT) VIhmin to VILmax Acknowledge or read (SDATA) with CL = 400pF tCH tFT MIN 0.7* VCC GND-0.3 -10 NOM MAX VCC+0.3 0.3* VCC 10 UNIT V V µA -50 -10 50 10 µA µA -300 10 µA -50 50 0.4 250 µA V ns tCL SCLK tsh tDH tPSU tDSU tssu MSB SDATA Start tRT LSB Stop Serial Port Timing (Typical) Page: 9 of 16 © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Video Characteristics - Unless otherwise noted, typical output loading on all video outputs is 150Ω. All video outputs are capable of withstanding a sustained 75Ω load to ground without damage. PARAMETER CONDITION MIN Input Impedance Input Dynamic Range RGB Gain Control A0 = reading xx00xxxx gain All video inputs fin = 100 kHz, THD < 0.15% 1.0 Vpp input, fin = 100 kHz; Register 1 = xxxxxx00 Register 1 = xxxxxx01 Register 1 = xxxxxx10 Register 1 = xxxxxx11 1.0 Vpp input, fin = 100 kHz; Register 1 = xxxx00xx Register 1 = xxxx01xx Register 1 = xxxx10xx Register 1 = xxxx11xx RGB or SVHS output channel to channel Amplitude loss measured at 10MHz, A0 = 2V/V 3dB, A0 = 2V/V 100 CVBS Gain Control A0 = reading xx00xxxx gain Output Gain Inequality Video Bandwidth Output DC Level Blank level clamp voltage Average level Signal to Noise Ratio Cross Talk Output to Output Differential Delay Differential Phase Differential Gain Page: 10 of 16 NOM MAX kΩ Vpp 1.5 1.9 2.0 2.1 A0 –12% A0 –22% A0 –33% A0 –10% A0 –20% A0 –30% A0 –8% A0 –18% A0 –27% 1.9 2.0 2.1 A0 –12% A0 –22% A0 –33% A0 –10% A0 –20% A0 –30% A0 –8% A0 –18% A0 –27% -2.5 1.0 UNIT 2.5 V/V V/V V/V V/V V/V V/V V/V V/V % 0.7 dB 25 MHz RGB, CVBS or Luma output 1.2 V Chroma, Pr or Pb output 1 Vpp input fin = 4.43 MHz, 1 Vpp RGB signals, fin = 100 kHz CVBS output CVBS output 1.8 75 -65 V dB dB ns Deg. % 58 -20 -2.5 -2.5 © 2005 TERIDIAN Semiconductor Corporation 20 2.5 2.5 Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Audio Characteristics - Unless otherwise noted, all audio outputs shall drive a load of 10.3 kΩ. All audio outputs will withstand a sustained 300Ω to ground without damage. PARAMETER Input Impedance Output Impedance Audio Gain Control Frequency Response Dynamic Range A Weighting filter Signal to Noise ratio A Weighting filter Distortion (THD) DC Offset Output Phase Matching Cross Talk Audio to video path skew CONDITION MIN 110 NOM 160 1.6 MAX 210 5 UNIT kΩ Ω fin = 1.0 kHz Register 1 = xxx0xxxx Register 1 = xxx1xxxx 0.5 Vrms input, Flat within ± 0.3 dB Measured -3 dB point fin = 1.0 kHz, 2.0 Vrms 100 90 100 kHz dB fin = 1.0 kHz, 2.0 Vrms 90 100 dB 0 6 dB dB kHz 20 0.5 Vrms output 2 Vrms output -250 fin = 1.0 kHz, 0.5 Vrms fin = 1.0 kHz, 2.0 Vrms 0.03 0.1 250 % % mV Deg. dB ns UNIT 75 0.5 100 150 NOM MAX With Output Load, 10kΩ, Vin = 12V 290 500 Ω With Output Load, 10kΩ, Vin = 9.5V 350 500 Ω With Output Load, 10kΩ, Vin = 7V 220 500 Ω NOM MAX UNIT 0.4 3.0 50 kΩ V V ns Video input = 1.0 Vpp @ 100 kHz Audio input = 0.5 Vrms @ 1.0 kHz TV Function Pin Characteristics PARAMETER CONDITION MIN Output Load Series Resistance @ Func_out 10 kΩ Fast Blanking (FB) Pin Characteristics PARAMETER CONDITION MIN Input Impedance Blanking Input Level FB1, FB2, FB3 Input Logical “0” Input Logical “1” FB to RGB Signals @ FB_out 100 0.0 1.0 -50 300 Blanking Delay Output Load FB Gain Page: 11 of 16 Ω 1.0 © 2005 TERIDIAN Semiconductor Corporation V/V Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET VDD VCC VCC VCC Application Diagram: (For TV 2/3-SCART Application) (SC1) 1 Dev_Addr 2 (SC1) (SC2) (SC2) (SC3) Func1 Func2 Func3 Mux FB1 FB2 FB3 Mux (SC1) (SC2) 75 (SC3) 19 20 21 0.01uF (SC1) (SC2) 75 (SC3) 0.01uF (SC1) (SC2) 75 (SC3) (SC3) 0.01uF (SC1) (SC2) 75 (SC3) 0.01uF (SC1) 75 (SC2) (SC3) 0.1uF 10k (SC1) (SC2) (SC3) 0.1uF 10k (SC1) (SC2) (SC3) Micro FB_out 300 Gain Mux Bl1 Bl2 Bl3 Mux Rd1 Rd2 Rd3 Mux 75 Gn_out 75 75 Bl_out 75 75 Rd_out 75 Gain CVBS_out Mux 75 75 R1 R2 R3 Mux L1 L2 L3 Mux SCLK SDATA Func_out 100k Gn1 Gn2 Gn3 CVBS1 CVBS2 CVBS3 0V/6V/12V 0/6dB R_out 10uF 10k L_out 10uF 10k Vref Serial Port Support Circuits Pdwn Rbias Tgen 10k 1uF Page: 12 of 16 © 2005 TERIDIAN Semiconductor Corporation GND GND GND GND 470pF Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET Application Diagram: (Dual AVPro® 5303B Application) (SC1) Dev_Addr Not Connected Input #1 Input #1 Input #1 5303B Output #1 (Device Address = 1001000x) (SC2) SCLK SDATA Dev_Addr (SC3) GND 5303B (Device Address = 1010000x) Output #2 SCLK SDATA Micro Page: 13 of 16 © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET PACKAGE PIN DESIGNATION Page: 14 of 16 FB1 CVBS1 CVBS_out FB_out Rd_out VCC GND Gn_out Bl_out Bl3 Gn3 Rd3 48 47 46 45 44 43 42 41 40 39 38 37 (Top View) Rd1 1 36 FB3 Gn1 2 35 CVBS3 Bl1 3 34 GND CVBS2 4 33 VCC FB2 5 32 Tgen Rd2 6 31 SDATA Gn2 7 30 SCLK Bl2 8 29 Dev_Addr VCC 9 28 Pdwn GND 10 27 VDD Rbias 11 26 GND N/C 12 25 Func1 17 18 19 20 21 22 23 24 L2 R3 L3 Vref R_out Func_out Func3 Func2 15 L1 16 14 R1 R2 13 L_out AVPro 5303B © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET MECHANICAL DRAWING 48QFN Package 0.85 NOM./ 0.9MAX. 6 5.75 0.65 NOM./ 0.7MAX. 0.00 / 0.005 3 0.20 REF. 2.875 1 2 3 2.875 3 6 5.75 12º MAX SIDE VIEW TOP VIEW SEATING PLANE 0.24 / 0.6 3.95 / 4.25 1.975 / 2.125 0.4 0.24 / 0.6 1 0.45 2 3 1.975 / 2.125 1.975 / 2.125 0.15 / 0.25 0.35 Min. BOTTOM VIEW Page: 15 of 16 0.35 Min. © 2005 TERIDIAN Semiconductor Corporation Rev 1.0 AVPro® 5303B Universal 3-Input A/V Switch Interface DATA SHEET ORDERING INFORMATION PART DESCRIPTION ORDER NO. ® ® PACKAGE MARK AVPro 5303B Universal 3-Input A/V Switch Interface (48 QFN) AVPro 5303B-CM AVPro® 5303B-CM AVPro® 5303B Universal 3-Input A/V Switch Interface (48 QFN) Tape and Reel AVPro® 5303B-CMR AVPro® 5303B-CM AVPro® 5303B Universal 3-Input A/V Switch Interface (48 QFN) Lead Free AVPro® 5303B-CM/F AVPro® 5303B-CM AVPro® 5303B Universal 3-Input A/V Switch Interface (48 QFN) Lead Free, Tape and Reel AVPro® 5303B-CMR/F AVPro® 5303B-CM This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corporation, 6440 Oak Canyon Road, Irvine, CA 92618-5201 TEL (714) 508-8800, FAX (714) 508-8875, http://www.teridian.com 12/16/05 – Rev 1.0 © 2005 TERIDIAN Semiconductor Corporation Page: 16 of 16 © 2005 TERIDIAN Semiconductor Corporation Rev 1.0