W29C102 64K × 16 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K × 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C102 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • Single 5-volt program and erase operations • Low power consumption − Active current: 25 mA (typ.) − Standby current: 20 µA (typ.) • Fast page-write operations − 128 words per page − Page program cycle: 10 mS (max.) − Effective word-program cycle time: 39 µS − Optional software-protected data write • Automatic program timing with internal VPP generation • End of program detection − Toggle bit − Data polling • Fast chip-erase operation: 50 mS • Read access time: 70/90/120 nS • Latched address and data • Typical page program/erase cycles: 1K/10K • TTL compatible I/O • Ten-year data retention • JEDEC standard word-wide pinouts • Software and hardware data protection • Available packages: 40-pin 600 mil DIP, TSOP and 44-pin PLCC -1- Publication Release Date: March 1998 Revision A3 W29C102 PIN CONFIGURATIONS 1 2 NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 GND DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE 3 4 5 BLOCK DIAGRAM 40 VDD 39 38 WE NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 37 36 35 6 7 34 33 8 9 40-pin DIP 10 11 32 31 30 29 12 13 28 27 14 15 16 26 25 24 17 18 23 22 19 20 21 V DD VSS DQ0 CE OUTPUT BUFFER CONTROL OE WE A0 A9 A10 A11 A12 A13 A14 A15 NC WE VDD NC 1 2 3 CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 12 13 14 40 39 38 37 4 5 36 35 6 7 34 33 8 9 40-pin TSOP 10 11 32 31 30 29 28 27 26 15 16 25 17 18 24 23 22 19 20 21 . GND A8 A7 A6 A5 A4 A3 A2 A1 A0 DECODER . CORE ARRAY A15 OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND PIN DESCRIPTION D D D / Q Q Q C N N 13 14 15 E C C 6 5 4 3 2 1 V D D / W N E C A A 1 1 5 4 SYMBOL 44 43 42 41 40 DQ12 7 39 A13 DQ11 8 38 A12 9 37 A11 10 36 A10 DQ10 DQ9 44-pin PLCC 35 A9 DQ8 11 GND 12 34 GND NC 13 33 NC DQ7 14 32 A8 DQ6 15 31 A7 30 A6 29 A5 DQ5 16 DQ4 17 A0−A15 DQ0−DQ15 18 19 20 21 22 23 24 25 26 27 28 D D D D Q Q Q Q 3 2 1 0 / N A A O C 0 1 E A A A 2 3 4 Address Inputs Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable VDD Power Supply GND Ground NC -2- PIN NAME No Connection . . DQ15 W29C102 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of data within a page is to be changed, data for the entire page must be loaded into the device. Any word that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the word-load cycle, the addresses are latched by the falling edge of either CE or WE, whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs first. If the host loads a second word into the page buffer within a word-load cycle time (TBLC) of 200 µS, after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional word is loaded into the page buffer. A7 to A15 specify the page address. All words that are loaded into the page buffer must have the same page address. A0 to A6 specify the word address within the page. The words may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written simultaneously into the memory array. The typical programming time is 5 mS. The entire memory array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-word program commands (with specific data to a specific address) to be performed before the data load operation. The three-word load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C102 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-word program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the -3- Publication Release Date: March 1998 Revision A3 W29C102 software data protection feature. To reset the device to unprotected mode, a six-word command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Hardware Data Protection The integrity of the data stored in the W29C102 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7 & DQ15)- Write Status Detection The W29C102 includes a data polling feature to indicate the end of a programming cycle. When the W29C102 is in the internal programming cycle, any attempt to read DQ7 and/or DQ15 of the last word loaded during the page/word-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6 & DQ14)- Write Status Detection In addition to data polling, the W29C102 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 and/or DQ14 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the device code (004Fh). The product ID operation can be terminated by a three-word command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. -4- W29C102 TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V) MODE PINS CE OE WE Read VIL VIL VIH AIN Dout Write VIL VIH VIL AIN Din Standby VIH X X X High Z X VIL X X High Z/DOUT X X VIH X High Z/DOUT X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL AIN DIN Product ID VIL VIL VIH A0 = VIL; A1−A15 = VIL; A9 = VHH Manufacturer Code 00DA (Hex) VIL VIL VIH A0 = VIH; A1−A15 = VIL; A9 = VHH Device Code 004F (Hex) Write Inhibit Output Disable ADDRESS -5- DQ. Publication Release Date: March 1998 Revision A3 W29C102 Command Codes for Software Data Protection BYTE SEQUENCE TO ENABLE PROTECTION ADDRESS DATA TO DISABLE PROTECTION ADDRESS DATA 0 Write 5555H AAAAH 5555H AAAAH 1 Write 2AAAH 5555H 2AAAH 5555H 2 Write 5555H A0A0H 5555H 8080H 3 Write - - 5555H AAAAH 4 Write - - 2AAAH 5555H 5 Write - - 5555H 2020H Software Data Protection Acquisition Flow Software Data Protection Enable Flow (Optional page-load operation) Software Data Protection Disable Flow Load data AAAA to address 5555 Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 5555 to address 2AAA Load data A0A0 to address 5555 Load data 8080 to address 5555 Sequentially load up to 128 words of page data Load data AAAA to address 5555 Load data 5555 to address 2AAA Pause 10 mS Exit Load data 2020 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ15−DQ0 (Hex) Address Format: A14−A0 (Hex) -6- W29C102 Command Codes for Software Chip Erase BYTE SEQUENCE ADDRESS DATA 0 Write 5555H AAAAH 1 Write 2AAAH 5555H 2 Write 5555H 8080H 3 Write 5555H AAAAH 4 Write 2AAAH 5555H 5 Write 5555H 1010H Software Chip Erase Acquisition Flow Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 8080 to address 5555 Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 1010 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ15−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: March 1998 Revision A3 W29C102 Command Codes for Product Identification BYTE SEQUENCE ALTERNATE SOFTWARE (5) PRODUCT IDENTIFICATION ENTRY ADDRESS DATA SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS SOFTWARE PRODUCT IDENTIFICATION EXIT DATA ADDRESS 0 Write 5555H AAH 5555H AAH 5555H DATA 1 Write 2AAAH 55H 2AAAH 55H 2AAAH 55H 2 Write 5555H 90H 5555H 80H 5555H F0H AAH 3 Write - - 5555H AAH - 4 Write - - 2AAAH 55H - - 5 Write - - 5555H 60H - - Pause 10 µS Pause 10 µS - Pause 10 µS Software Product Identification Acquisition Flow Product Identification Entry (1) Product Identification Mode (2, 3) Product Identification Exit (1) Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 8080 to address 5555 Load data AAAA to address 5555 Read address = 0 data = 00DA Load data AAAA to address 5555 Load data 5555 to address 2AAA Load data 5555 to address 2AAA Load data F0F0 to address 5555 Read address = 1 data = 004F Pause 10 µS (4) Load data 6060 to address 5555 Normal Mode Pause 10 µS Notes for software product identification: (1) Data format: DQ15−DQ0 (Hex); address format: A14−A0 (Hex). (2) A1−A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. (5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29C102 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except OE -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on A9 and OE Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS LIMITS CE = OE = VIL, WE = VIH, all I/Os open UNIT MIN. TYP. MAX. - 25 60 mA - 2 3 mA - 20 200 µA Address inputs = VIL/VIH, at f = 5 MHz Standby VDD Current ISB1 (TTL input) Standby VDD Current CE = VIH, all I/Os open Other inputs = VIL/VIH ISB2 (CMOS input) CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND Input Leakage Current ILI VIN = GND to VDD - - 10 µA Output Leakage Current ILO VOUT = GND to VDD - - 10 µA Input Low Voltage VIL - - - 0.8 V Input High Voltage VIH - 2.0 - - V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V Output High Voltage CMOS VOH2 IOH = -100 µA; VCC = 4.5V 4.2 - - V -9- Publication Release Date: March 1998 Revision A3 W29C102 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT µS mS Power-up to Read Operation TPU. READ 100 Power-up to Write Operation TPU. WRITE 5 CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance Input Capacitance CONDITIONS CI/O CIN VI/O = 0V VIN = 0V MAX. UNIT 12 6 pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3.0V <5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF for 90/120 nS CL = 30 pF for 70 nS AC Test Load and Waveform +5V 1.8KΩ DOUT 100 pF for 90/120 nS 30 pF for 70 nS (Including Jig and Scope) 1.3KΩ Input Output 3V 1.5V 1.5V 0V Test Point - 10 - Test Point W29C102 AC Characteristics, continued Read Cycle Timing Parameters (VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29C102-70 W29C102-90 W29C102-12 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TAA - 70 - 90 - 120 nS Output Enable Access Time TOE - 35 - 45 - 60 nS CE High to High-Z Output TCHZ - 25 - 25 - 30 nS OE High to High-Z Output TOHZ - 25 - 25 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Byte/Page-write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write Cycle (erase and program) TWC - - 10 mS Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS WE and CE Setup Time TCS 0 - - nS WE and CE Hold Time TCH 0 - - nS OE High Setup Time TOES 0 - - nS OE High Hold Time TOEH 0 - - nS CE Pulse Width TCP 70 - - nS WE Pulse Width TWP 70 - - nS WE High Width TWPH 100 - - nS Data Setup Time TDS 50 - - nS Data Hold Time TDH 0 - - nS Byte Load Cycle Time TBLC - - 150 µS Notes: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH. (b) Low level signal's reference level is VIL. - 11 - Publication Release Date: March 1998 Revision A3 W29C102 AC Characteristics, continued DATA Polling Characteristics (1) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Data Hold Time TDH 10 - - nS OE Hold Time TOEH 10 - - nS OE to Output Delay (2) TOE - - - nS Write Recovery Time TWR 0 - - nS MIN. TYP. MAX. UNIT Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. Toggle Bit Characteristics (1) PARAMETER SYMBOL Data Hold Time TDH 10 - - nS OE Hold Time TOEH 10 - - nS OE to Output Delay (2) TOE - - - nS OE High Pulse TOEHP 150 - - nS Write Recovery Time TWR 0 - - nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. - 12 - W29C102 TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 TCE CE TOE OE T OHZ VIH WE TOH DQ15-0 T CHZ High-Z High-Z Data Valid Data Valid TAA WE Controlled Write Cycle Timing Diagram TWC TAS TAH Address A15-0 CE TCS TCH TOES T OEH OE WE TWP TWPH TDS DQ15-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: March 1998 Revision A3 W29C102 Timing Waveforms, continued CE Controlled Write Cycle Timing Diagram T AS T WC T AH Address A15-0 T CPH T CP CE T OES T OEH OE WE T DS DQ15-0 High Z Data Valid T DH Internal Write Starts Page Write Cycle Timing Diagram TWC Address A15-0 DQ15-0 CE OE T WPH TBLC TWP WE Word 0 Word 1 Word 2 Word N-1 Internal Write Start - 14 - Word N W29C102 Timing Waveforms, continued DATA Polling Timing Diagram Address A15-0 An An An An An WE CE TOEH OE TDH TWR HIGH-Z TOE DQ7 or DQ15 Toggle Bit Timing Diagram WE CE OE TOEH TDH TOE HIGH-Z TWR DQ6 or DQ14 Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of DQ6 and DQ14 may vary. 3. Any address location may be used but the address should not vary. - 15 - Publication Release Date: March 1998 Revision A3 W29C102 Timing Waveforms, continued Page Write Timing Diagram Software Data Protection Mode Address A15-0 2AAA 5555 DQ15-0 AAAA TWC Byte/page load cycle starts Three-byte sequence for software data protection mode 5555 5555 A0A0 CE OE TBLC TWP WE TWPH SW2 SW1 SW0 Word N-1 Word 0 Word N (last word) Internal write starts Reset Software Data Protection Timing Diagram Six-word sequence for resetting software data protection mode Address A15-0 DQ15-0 5555 2AAA AAAA 5555 5555 5555 8080 AAAA 2AAA 5555 TWC 5555 2020 CE OE TWP TBLC WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts - 16 - W29C102 Timing Waveforms, continued 5-Volt-only Software Chip Erase Timing Diagram Six-word code for 5V-only software chip erase Address A15-0 DQ15-0 5555 2AAA AAAA 5555 5555 5555 8080 AAAA 2AAA 5555 TWC 5555 1010 CE OE TWP TBLC WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts - 17 - Publication Release Date: March 1998 Revision A3 W29C102 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (µA) W29C102-70 70 60 200 600 mil DIP 1K W29C102-90 90 60 200 600 mil DIP 1K W29C102-12 120 60 200 600 mil DIP 1K W29C102Q-70 70 60 200 40-pin TSOP (10 mm × 14 mm) 1K W29C102Q-90 90 60 200 40-pin TSOP (10 mm × 14 mm) 1K W29C102Q-12 120 60 200 40-pin TSOP (10 mm × 14 mm) 1K W29C102T-70 70 60 200 40-pin TSOP (10 mm × 20 mm) 1K W29C102T-90 90 60 200 40-pin TSOP (10 mm × 20 mm) 1K W29C102T-12 120 60 200 40-pin TSOP (10 mm × 20 mm) 1K W29C102P-70 70 60 200 44-pin PLCC 1K W29C102P-90 90 60 200 44-pin PLCC 1K W29C102P-12 120 60 200 44-pin PLCC 1K W29C102-70B 70 60 200 600 mil DIP 10K PACKAGE CYCLE W29C102-90B 90 60 200 600 mil DIP 10K W29C102-12B 120 60 200 600 mil DIP 10K W29C102Q-70B 70 60 200 40-pin TSOP (10 mm × 14 mm) 10K W29C102Q-90B 90 60 200 40-pin TSOP (10 mm × 14 mm) 10K W29C102Q-12B 120 60 200 40-pin TSOP (10 mm × 14 mm) 10K W29C102T-70B 70 60 200 40-pin TSOP (10 mm × 20 mm) 10K W29C102T-90B 90 60 200 40-pin TSOP (10 mm × 20 mm) 10K W29C102T-12B 120 60 200 40-pin TSOP (10 mm × 20 mm) 10K W29C102P-70B 70 60 200 44-pin PLCC 10K W29C102P-90B 90 60 200 44-pin PLCC 10K W29C102P-12B 120 60 200 44-pin PLCC 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W29C102 PACKAGE DIMENSIONS 40-pin PDIP Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 Min. Nom. Max. 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 2.055 2.070 52.20 52.58 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.590 0 0.630 0.650 15 0.090 2.29 Notes: 20 E S c A A2 A1 Base Plane Seating Plane L B 5.33 0.25 0.150 eA S 1 Min. Nom. Max. 0.210 0.010 a E1 Dimension in mm Dimension in inches e1 eA a B1 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 E HE 17 GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 4.70 0.020 0.51 0.145 0.150 0.155 3.68 3.81 3.94 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.36 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.29 2.54 0.004 2.79 0.10 Notes: L 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. A2 A θ e b b1 Seating Plane A1 y GD - 19 - Publication Release Date: March 1998 Revision A3 W29C102 Package Dimensions, continued 40-pin TSOP (10 mm × 14 mm) HD Dimension in Inches Symbol D c A A1 A2 1 M e b c E 0.10(0.004) b A θ A2 A1 L Y L1 Min. Nom. Max. Dimension in mm Min. Max. 1.20 0.15 0.002 0.006 0.05 0.037 0.039 0.041 0.95 1.00 1.05 0.007 0.009 0.011 0.17 0.22 0.27 0.004 0.006 0.008 0.10 0.15 0.20 12.30 12.40 12.50 D 0.484 0.488 0.492 E HD e L L1 0.390 0.394 0.398 0.543 0.551 0.559 13.80 0.020 0.024 Y θ Nom. 0.047 9.90 10 10.10 14.00 14.20 0.020 0.50 0.028 0.50 0.031 0.000 0 3 0.60 0.70 0.8 0.004 0.00 5 0 0.10 3 5 Controlling dimension: Millimeters 40-pin TSOP (10 mm × 20 mm) HD Dimension in Inches Min. c A1 A2 b c e E 0.10(0.004) b A θ A2 A1 L Y L1 Nom. Max. A 1 M Dimension in mm Symbol D Min. Max. 1.20 0.002 0.006 0.05 0.037 0.039 0.041 0.95 0.15 1.00 1.05 0.007 0.009 0.011 0.17 0.22 0.27 0.004 0.006 0.008 0.10 0.15 0.20 D 0.72 18.4 18.5 E HD e L L1 0.390 0.394 0.398 9.90 10 10.10 0.780 0.787 0.795 19.8 20.0 Y θ 0.724 0.728 18.3 0.020 0.020 0.024 0.028 0.50 0.031 0.000 0 3 20.2 0.50 0.60 0.70 0.8 0.004 0.00 5 0 Controlling dimension: Millimeters - 20 - Nom. 0.047 0.10 3 5 W29C102 VERSION HISTORY VERSION DATE PAGE A3 Mar. 1998 6 Add. pause 10 mS 7 Add. pause 50 mS 8 Correct the time from 10 mS to 10 µS 11 Change VDD from 5% to 10% for 70 nS Headquarters DESCRIPTION Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 21 - Publication Release Date: March 1998 Revision A3