WINBOND W29F102Q-50

W29F102
64K × 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29F102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K × 16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29F102 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
•
Single 5-volt operations:
Low power consumption
− 5-volt Read
− Active current: 25 mA (typ.)
− 5-volt Erase
− Standby current: 20 µA (typ.)
− 5-volt Program
•
•
•
Automatic program and erase timing with
internal VPP generation
•
End of program or erase detection
Fast Program operation:
− Word-by-Word programming: 50 µS (max.)
•
Fast Erase operation: 100 mS (typ.)
•
Fast Read access time: 45/50/55/70 nS
•
Endurance: 1K/10K cycles (typ.)
•
Ten-year data retention
•
Hardware data protection
•
8K word Boot Block with Lockout protection
− Toggle bit
− Data polling
•
Latched address and data
•
TTL compatible I/O
•
JEDEC standard word-wide pinouts
•
Available packages: 40-pin TSOP and 44-pin
PLCC
-1-
Publication Release Date: June 1999
Revision A4
W29F102
PIN CONFIGURATIONS
BLOCK DIAGRAM
VDD
A9
A10
A11
A12
A13
A14
A15
NC
WE
VDD
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
40-pin
TSOP
9
10
11
32
31
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VSS
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
CE
CONTROL
OE
WE
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
.
6
5
4
3
2
1
DECODER
.
39
A13
DQ11
8
38
A12
9
37
A11
DQ9
10
36
DQ8
11
35
A10
A9
GND
12
34
GND
NC
13
33
NC
DQ7
14
32
A8
15
31
A7
A6
A5
44-pin
PLCC
DQ5
16
30
DQ4
17
29
BootBlock
(8K Words)
PIN DESCRIPTION
SYMBOL
A0−A15
DQ0−DQ15
18 19 20 21 22 23 24 25 26 27 28
D D D D
Q Q Q Q
3 2 1 0
(56K Words)
44 43 42 41 40
7
DQ6
DQ15
A A
1 1
5 4
DQ12
DQ10
.
.
MAIN
MEMORY
A0
A15
V /
D D D /
Q Q Q C N N D W N
13 14 15 E C C D E C
OUTPUT
BUFFER
/ N A A
O C 0 1
E
A A A
2 3 4
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
VDD
Power Supply
GND
Ground
NC
-2-
PIN NAME
No Connection
W29F102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29F102 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will only affect the main memory.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the
output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the main
memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as
before the chip erase operation). The entire memory array (main memory and boot block) will be
erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not
activated. The device will automatically return to normal read mode after the erase operation
completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Main Memory Erase Operation
The main memory erase mode can be initiated by a six-word command sequence. After the
command loading cycle, the device enters the internal main-memory erase mode, which is
automatically timed and will be completed in a fast 100 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.
-3-
Publication Release Date: June 1999
Revision A4
W29F102
Program Operation
The W29F102 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will interally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 µS max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W29F102 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7 & DQ15)- Write Status Detection
The W29F102 includes a data polling feature to indicate the end of a program or erase cycle. When
the W29F102 is in the internal program or erase cycle, any attempt to read DQ7 or DQ15 of the last
word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 or DQ15 will show the true data. Note that DQ7 or DQ15 will show logical "0" during
the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6 & DQ14)- Write Status Detection
In addition to data polling, the W29F102 provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 or
DQ14 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling
between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address
0001H outputs the device code (002Fh). The product ID operation can be terminated by a three-word
command sequence or an altenate one-word command sequence (see Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.
-4-
W29F102
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 0.5V)
MODE
PINS
ADDRESS
DQ.
CE
OE
WE
Read
VIL
VIL
VIH
AIN
Dout
Write
VIL
VIH
VIL
AIN
Din
Standby
VIH
X
X
X
High Z
X
VIL
X
X
High Z/DOUT
X
X
VIH
X
High Z/DOUT
X
VIH
X
X
High Z
VIL
VIL
VIH
A0 = VIL; A1−A15 = VIL;
A9 = VHH
Manufacturer Code 00DA
(Hex)
VIL
VIL
VIH
A0 = VIH; A1−A15 = VIL;
A9 = VHH
Device Code
002F (Hex)
Write Inhibit
Output Disable
Product ID
TABLE OF COMMAND DEFINITION
Command
No. of
Description
Cycles
1st Cycle 2nd Cycle 3rd Cycle
Addr.
Data
4th Cycle
5th Cycle
6th Cycle
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Read
1
AIN
DOUT
Chip Erase
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
5555 10
Main Memory Erase
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
5555 30
Word Program
4
5555 AA
2AAA 55
5555 A0
AIN
Boot Block Lockout
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
5555 40
Product ID Entry
3
5555 AA
2AAA 55
5555 90
Product ID Exit
(1)
3
5555 AA
2AAA 55
5555 F0
Product ID Exit
(1)
1
XXXX F0
DIN
Note: Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex)
Either one of the two Product ID Exit commands can be used.
-5-
Publication Release Date: June 1999
Revision A4
W29F102
Command Codes for Word Program
WORD SEQUENCE
ADDRESS
DATA
0 Write
5555H
AAH
1 Write
2AAAH
55H
2 Write
5555H
A0H
3 Write
Programmed-Address
Programmed-Data
Word Program Flow Chart
Word Program
Command Flow
Load data
AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data Din
to
programmedaddress
Pause 50 µS
Exit
Notes for software program code:
Data Format: DQ15−DQ0 (Hex); XX = Don't Care
Address Format: A14−A0 (Hex)
-6-
W29F102
Command Codes for Chip Erase
BYTE SEQUENCE
ADDRESS
DATA
1 Write
5555H
AAH
2 Write
2AAAH
55H
3 Write
5555H
80H
4 Write
5555H
AAH
5 Write
2AAAH
55H
6 Write
5555H
10H
Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 1 Sec.
Exit
Notes for chip erase:
Data Format: DQ15-DQ8: Don't Care ; DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
-7-
Publication Release Date: June 1999
Revision A4
W29F102
Command Codes for Main Memory Erase
BYTE SEQUENCE
ADDRESS
1 Write
5555H
AAH
2 Write
2AAAH
55H
3 Write
5555H
80H
4 Write
5555H
AAH
5 Write
2AAAH
55H
6 Write
5555H
30H
Main Memory Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 30
to
address 5555
Pause 1 Sec.
Exit
Notes for chip erase:
Data Format: DQ15-DQ8: Don't Care ; DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
-8-
DATA
W29F102
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE
PRODUCTIDENTIFICATION/BOOT
BLOCK LOCKOUT DETECTION
ENTRY
ADDRESS
DATA
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK LOCKOUT
DETECTION EXIT (6)
ADDRESS
DATA
1 Write
5555
AA
5555H
AAH
2 Write
2AAA
55
2AAAH
55H
3 Write
5555
90
5555H
F0H
Pause 10 µS
Pause 10 µS
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
Entry (1)
Load data AA
to
address 5555
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Product
Identification Exit(6)
Load data AA
to
address 5555
(2)
Load data 55
to
address 2AAA
Read address = 0000
data = DA
Load data 90
to
address 5555
Read address = 0001
data = 2F
Pause 10 µS
Read address = 0002
data = FF/FE
(2)
(4)
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 µ S
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ15-DQ8 (Don't Care), DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is
inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
-9-
Publication Release Date: June 1999
Revision A4
W29F102
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE
BOOT BLOCK LOCKOUT FEATURE SET
ADDRESS
DATA
1 Write
5555H
AAH
2 Write
2AAAH
55H
3 Write
5555H
80H
4 Write
5555H
AAH
5 Write
2AAAH
55H
6 Write
5555H
40H
Pause 1 Sec.
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause 1 Sec.
Exit
Notes for boot block lockout enable:
Data Format: DQ15-DQ8 Don't Care), DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
- 10 -
W29F102
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
-0.5 to +7.0
V
0 to +70
°C
-65 to +150
°C
D.C. Voltage on Any Pin to Ground Potential except OE
-0.5 to VDD +1.0
V
Transient Voltage (<20 nS ) on Any Pin to Ground Potential
-1.0 to VDD +1.0
V
-0.5 to 12.5
V
Power Supply Voltage to Vss Potential
Operating Temperature
Storage Temperature
Voltage on OE Pin to Ground Potential
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
MIN. TYP.
Power Supply
Current
Standby VDD
ICC
ISB1
Current (TTL input)
Standby VDD
Current
UNIT
MAX.
CE = OE = VIL, WE = VIH, all 50, 55,
I/Os open Address inputs = 70 nS
VIL/VIH, at f = 5 MHz
45 nS
-
25
50
mA
-
25
70
mA
CE = VIH, all I/Os open
-
2
3
mA
-
20
100
µA
Other inputs = VIL/VIH
ISB2
CE = VDD -0.3V, all I/Os open
Other inputs = VDD -0.3V/GND
(CMOS input)
Input Leakage
Current
ILI
VIN = GND to VDD
-
-
10
µA
Output Leakage
Current
ILO
VOUT = GND to VDD
-
-
10
µA
Input Low Voltage
VIL
50, 55, 70 nS
-0.3
-
0.8
V
45 nS
-0.3
-
0.6
V
2.0
-
VDD
+0.5
V
-
Input High Voltage
VIH
-
Output Low Voltage
VOL
IOL = 2.1 mA
-
-
0.45
V
Output High Voltage
VOH
IOH = -0.4 mA
2.4
-
-
V
- 11 -
Publication Release Date: June 1999
Revision A4
W29F102
Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
µS
mS
Power-up to Read Operation
TPU. READ
100
Power-up to Write Operation
TPU. WRITE
5
CAPACITANCE
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
SYMBOL
I/O Pin Capacitance
Input Capacitance
CONDITIONS
CI/O
CIN
VI/O = 0V
VIN = 0V
MAX.
UNIT
12
6
pf
pf
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
Input Rise/Fall Time
0V to 3.0V
< 5 nS
Input/Output Timing Level
Output Load
1.5V/1.5V
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+5V
1.8KΩ
DOUT
30 pF
1.3KΩ
(Including Jig and
Scope)
Input
Output
3V
1.5V
1.5V
0V
Test Point
- 12 -
Test Point
W29F102
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V ±10%, TA = 0 to 70° C)
PARAMETER
SYM.
W29F10245
W29F10250
W29F10255
W29F10270
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
TRC
45
-
50
-
55
-
70
-
nS
Chip Enable Access Time
TCE
-
45
-
50
-
55
-
70
nS
Address Access Time
TAA
-
45
-
50
-
55
-
70
nS
Output Enable Access Time
TOE
-
25
-
25
-
30
-
35
nS
CE Low to Active Output
TCLZ
0
-
0
-
0
-
0
-
nS
OE Low to Active Output
TOLZ
0
-
0
-
0
-
0
-
nS
CE High to High-Z Output
TCHZ
-
20
-
20
-
25
25
nS
OE High to High-Z Output
TOHZ
-
20
-
20
-
25
-
25
nS
Output Hold from Address
Change
TOH
0
-
0
-
0
-
0
-
nS
Write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Address Setup Time
TAS
0
-
-
nS
Address Hold Time
TAH
50
-
-
nS
WE and CE Setup Time
TCS
0
-
-
nS
WE and CE Hold Time
TCH
0
-
-
nS
OE High Setup Time
TOES
0
-
-
nS
OE High Hold Time
TOEH
0
-
-
nS
CE Pulse Width
TCP
70
-
-
nS
WE Pulse Width
TWP
70
-
-
nS
WE High Width
TWPH
70
-
-
nS
Data Setup Time
TDS
50
-
-
nS
Data Hold Time
TDH
0
-
-
nS
Word Programming Time
TBP
-
10
50
µS
Erase Cycle Time
TEC
-
0.1
1
Sec.
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 13 -
Publication Release Date: June 1999
Revision A4
W29F102
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYM.
W29F10245
W29F10250
W29F10255
W29F10270
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
OE to Data Polling Output
Delay
TOEP
-
25
-
25
-
30
-
35
nS
CE to Data Polling Output
Delay
TCEP
-
45
-
50
-
55
-
70
nS
OE to Toggle Bit Output
Delay
TOET
-
25
-
25
-
30
-
35
nS
CE to Toggle Bit Output
Delay
TCET
-
45
-
50
-
55
-
70
nS
TIMING WAVEFORMS
Read Cycle Timing Diagram
TRC
Address A15-0
TCE
CE
TOE
OE
VIH
T OHZ
TOLZ
WE
TCLZ
TOH
TCHZ
High-Z
High-Z
DQ15-0
Data Valid
Data Valid
TAA
- 14 -
W29F102
Timing Waveforms, continued
WE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A15-0
CE
TCS
TCH
T OES
T OEH
OE
TWP
WE
T WPH
TDS
DQ15-0
Data Valid
TDH
CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A15-0
TCPH
TCP
CE
TOES
TOEH
OE
WE
TDS
DQ15-0
High Z
Data Valid
TDH
- 15 -
Publication Release Date: June 1999
Revision A4
W29F102
Timing Waveforms, continued
Program Cycle Timing Diagram
Word Program Cycle
Address A15-0
2AAA
5555
55
AA
DQ15-0
5555
Address
A0
Data-In
CE
OE
T WPH
TBP
TWP
WE
Word 0
Word 1
Word 2
Word 3
Internal Write Start
DATA Polling Timing Diagram
Address A15-0
WE
TCEP
CE
TOEH
TOES
OE
TOEP
DQ7/DQ15
X
X
X
T BP or T EC
- 16 -
X
W29F102
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A15-0
WE
CE
TOES
TOEH
OE
DQ6/DQ14
TBP or TEC
Boot Block Lockout Enable Timing Diagram
Six-word code for Boot Block
Lockout Feature Enable
Address A15-0
DQ15-0
5555
2AAA
XXAA
XX55
5555
5555
XX80
XXAA
2AAA
XX55
5555
XX40
CE
OE
TWP
TWC
WE
TWPH
SW0
SW1
SW23
SW3
- 17 -
SW4
SW5
Publication Release Date: June 1999
Revision A4
W29F102
Timing Waveforms, continued
Chip Erase Timing Diagram
Six-word code for 5V-only software
chip erase
Address A15-0
DQ15-0
5555
2AAA
XX55
XXAA
5555
5555
XX80
2AAA
XXAA
XX55
5555
XX10
CE
OE
TWP
TEC
WE
TWPH
SW0
SW1
SW2
SW3
SW4
SW5
Internal Erase starts
Main Memory Erase Timing Diagram
Six-word code for 5V-only software
Main Memory Erase
Address A15-0
DQ15-0
5555
2AAA
XXAA
XX55
5555
5555
XX80
XXAA
2AAA
XX55
5555
XX30
CE
OE
TWP
TEC
WE
TWPH
SW0
SW1
SW2
- 18 -
SW3
SW4
SW5
Internal Erase starts
W29F102
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
POWER
SUPPLY
CURRENT
MAX.
(mA)
STANDBY
VDD
CURRENT
MAX.
PACKAGE
CYCLE
(µA)
W29F102Q-45
45
70
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
1K
W29F102Q-50
50
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
1K
W29F102Q-55
55
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
1K
W29F102Q-70
70
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
1K
W29F102P-45
45
70
100 (CMOS)
44-pin PLCC
1K
W29F102P-50
50
50
100 (CMOS)
44-pin PLCC
1K
W29F102P-55
55
50
100 (CMOS)
44-pin PLCC
1K
W29F102P-70
70
50
100 (CMOS)
44-pin PLCC
1K
W29F102Q-45B
45
70
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
10K
W29F102Q-50B
50
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
10K
W29F102Q-55B
55
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
10K
W29F102Q-70B
70
50
100 (CMOS)
40-pin TSOP (10 mm × 14 mm)
10K
W29F102P-45B
45
70
100 (CMOS)
44-pin PLCC
10K
W29F102P-50B
50
50
100 (CMOS)
44-pin PLCC
10K
W29F102P-55B
55
50
100 (CMOS)
44-pin PLCC
10K
W29F102P-70B
70
50
100 (CMOS)
44-pin PLCC
10K
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
- 19 -
Publication Release Date: June 1999
Revision A4
W29F102
PACKAGE DIMENSIONS
44-pin PLCC
HD
D
6
1
44
Dimension in Inches
40
Symbol
7
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
39
E HE
17
GE
29
18
28
c
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.185
4.70
0.020
0.51
0.145 0.150 0.155
3.68
3.81
3.94
0.026 0.028 0.032
0.66
0.71
0.81
0.016 0.018 0.022
0.41
0.46
0.56
0.008 0.010 0.014
0.20
0.25
0.36
0.648 0.653 0.658 16.46 16.59 16.71
0.648 0.653 0.658 16.46 16.59 16.71
1.27 BSC
0.050 BSC
0.590 0.610 0.630 14.99 15.49 16.00
0.590 0.610 0.630 14.99 15.49 16.00
0.680 0.690 0.700 17.27 17.53 17.78
0.680 0.690 0.700 17.27 17.53 17.78
0.090 0.100 0.110
2.79
2.54
2.29
0.10
0.004
Notes:
L
1. Dimension D & E do not include interlead flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
A2 A
θ
e
b
b1
Seating Plane
A1
y
GD
40-pin TSOP (10 mm × 14 mm)
HD
Dimension in Inches
Symbol
D
c
e1
M
E
0.10(0.004)
A
A1
0.002
A2
0.037
b
c
0.007
0.004
D
E
b
A
θ
A2
A1
L
Y
L1
Min.
HD
e
L
L1
Y
θ
Nom.
Max.
Dimension in mm
Min.
1.20
0.05
0.039
0.041
0.95
1.00
0.009
0.011
0.17
0.22
0.27
0.006
0.008
0.10
0.15
0.20
12.30 12.40
12.50
0.484
0.488 0.492
0.390
0.394
0.543
0.551 0.559 13.80
0.398
9.90
0.020
0.020
0.024
0.000
3
0.15
1.05
10
10.10
14.00
14.20
0.50
0.028
0.50
0.031
0
Max.
0.006
0.60
0.70
0.8
0.004
0.00
5
0
Controlling dimension: Millimeters
- 20 -
Nom.
0.047
0.10
3
5
W29F102
VERSION HISTORY
VERSION
DATE
A1
Feb. 1998
A2
Apr. 1998
PAGE
Initial Issued
1, 13, 14, 19
Add 35 nS item and delete 50 nS item
6, 7, 8, 9, 10
Change address format from A15 to A14
6, 7, 8, 9
18
A3
Mar. 1999
DESCRIPTION
1, 13, 14, 19
Add the pause time
Correct the address from 2000 to 5555
Add 50/70 nS bining
Delete 35 nS bining
A4
Jun. 1999
11, 19
Change Icc 50 mA to 70 mA (only for 45 nS)
Change VIL 0.8V to 0.6V (only for 45 nS)
Headquarters
5
VHH = 12V ±0.5V
11, 13
VDD = 5.0V ±10%
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
No. 4, Creation Rd. III,
123 Hoi Bun Rd., Kwun Tong,
Science-Based Industrial Park,
Kowloon, Hong Kong
Hsinchu, Taiwan
TEL: 852-27513100
TEL: 886-3-5770066
FAX: 852-27552064
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 21 -
Publication Release Date: June 1999
Revision A4