74HC595 8-Bit Shift Registers W ith Latched 3-State Output GENERAL DESCRIPTION 74HC595 is fabricated with high-speed silicon gate CMOS technology. It contains an 8-bit serial-in, serial or parallel-out shift register and an 8-bit D-type storage register with parallel 3-state outputs. The shift and storage register have independent clock inputs. Both the shift register clock (SRCK) and storage register clock (RCK) are positive-edge triggered. The shift register has a direct overriding clear input (SRCL), serial data input (SER), and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. FEATURES • • • • • • • • • 8-bit serial-in, parallel-out shift register with storage Shift register has direct clear 8-bit D-type storage register with parallel 3-state outputs Two independent clocks for shift and storage register Wide operating power supply voltage 2-6V Low input current < 1µA Low power consumption, Max. 80µA (74HC595) Output driving capacity ± 6 mA at 5V Typical propagation delay 13nS LOGIC DIAGRAM Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 15 1 2 3 4 5 6 7 13 OE 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 12 RCK 11 SRCK 14 SER 1D C1 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 10 SRCL 1 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 9 Q8’ WS74HC595 FUNCTIONAL DESCRIPTION 1. Truth Table Inputs Function SER SRCK SRCL RCK OE X X X X X L X X X H L X Outputs Q1-Q8 are disabled. Outputs Q1-Q8 are enabled. Shift register is cleared. L X X X ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the latch. H = High Level (steady state). L= Low Level (steady state) X = Irrelevant (don’t care) ↑= Transition from low to high level. 2. Logic Waveform SRCK SER RCK SRCL OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q8' Note: implies that the outputs are in 3-state mode. 2 WS74HC595 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit - 0.5 ~ + 7.0 V DC input clamp current Iik (Vi<0 or Vi>Vcc) ±20 mA DC output clamp current Iok (Vo<0 or Vo>Vcc) ±20 mA DC Current Drain per pin, any output (Iout) ±35 mA DC supply Current, Vcc or GND (Icc) ±70 mA -65 ~ +150 ℃ 260 ℃ DC supply voltage Vcc Storage Temperature( TSTG) Lead Temperature(TL) (Soldering, 10seconds) Note: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITONS Parameter Power Supply Voltage (Vcc) VCC=2.0V VIH High-level input voltage VCC=4.5V VCC=6.0V Min. Normal Max. Unit 2 5 6 V 1.5 3.15 4.2 VCC=2.0V VIL Low-level Input Voltage VCC=4.5V VCC=6.0V VI Input Voltage VO Output Voltage Operating Temperature (TA) Input Rise/Fall Times (tr, tf) 74HC595 0 0 -40 VCC=2.0V VCC=4.5V VCC=6.0V V 0.5 1.35 1.8 V Vcc Vcc 85 V V ℃ 1000 500 400 ns Note: 2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. 3. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and Vcc = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 3 WS74HC595 DC ELECTRICAL CHARACTERISTICS (Apply across temperature range unless otherwise specified) PARAMETER VOH TEST CONDITIONS VI= VIH or VIL Vcc MIN 1.9 4.4 5.9 3.98 5.48 2 V IOH = -20uA 4.5V 6 V IOH = -6 mA 4.5V IOH = -7.8mA 6 V 2 V IOL =20uA 4.5V 6 V IOL = 6mA 4.5V IOL =7.8mA 6 V 6 V VOL VI= VIH or VIL II VI = Vcc or 0 IOZ Icc Ci VO = Vcc or 0, Q1-Q8 VI = Vcc or 0 IO = 0 6 V 6 V 2V ~ 6V TA = 25℃ 54HC595 TYP MAX MIN 1.998 1.9 4.499 4.4 5.999 5.9 4.3 3.84 5.8 5.34 0.002 0.1 0.001 0.1 0.001 0.1 0.17 0.26 0.15 0.26 ±100 ±0.1 ±0.01 ±0.5 8 3 10 74HC595 MAX UNIT V 0.1 0.1 0.1 V 0.33 0.33 ±1000 nA ±5 uA 80 uA 10 pF TIMING REQUREMENTS OVER RECOMMENED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted) Parameter Symbol Unit Clock frequency fclock MHz Pulse duration tw ns Setup time tsu ns Hold time, th ns Guaranteed Limit TA=25℃ 6 31 36 80 16 14 80 16 14 100 20 17 75 15 13 50 10 9 50 10 9 0 Test Condition -40~+85 5 Vcc=2.0V 25 Vcc=4.5V 29 Vcc=6.0V 100 Vcc=2.0V SRCK or LCK high or low 20 Vcc=4.5V 17 Vcc=6.0V 100 Vcc=2.0V SRCL low 20 Vcc=4.5V 17 Vcc=6.0V 125 Vcc=2.0V 25 Vcc=4.5V SER before SRCK↑ 21 Vcc=6.0V 94 Vcc=2.0V 19 Vcc=4.5V SRCK↑ before LCK↑ (Note 4) 16 Vcc=6.0V 65 Vcc=2.0V 13 Vcc=4.5V SRCL low before RCK↑ 11 Vcc=6.0V 60 Vcc=2.0V SRCL high(inactive) 12 Vcc=4.5V 11 before SRCK↑ Vcc=6.0V 0 Vcc=2~6V SER after SRCK↑ Note: . 4. This setup time allows the latch to receive stable data from the shift register. The clock can be connected together, in this case the shift register is one clock pulse ahead of the latch. 4 WS74HC595 AC ELECTRICAL CHARACTERISTICS (unless otherwise noted) Parameter Symbol Maximum clock frequency From To Unit (Input) (Output) MHz fmax SRCK Q8' Maximum Propagation Delay (Clock to Q) tpd LCK LCK Maximum Propagation Delay (SRCL to Q8' Maximum Propagation Delay (OE to Q) Q1-Q8 Q1-Q8 4.5V 17 32 ns 6V 2V 4.5V 6V 2V 14 50 17 27 150 30 4.5V 6V 2V tPHL SRCL ns QH' Ta = 25℃ Min Typ Max 2V 6 26 4.5V 31 38 6V 36 42 2V 50 160 ns ns 4.5V 6V 2V 4.5V 6V ten OE Q1-Q8 ns OE Q1-Q8 ns 2V 4.5V 6V 4.5V 6V 2V 6V 2V tt Q8' ns 4.5V 6V 2V 4.5V Q1-Q8 6V Power Dissipation Capacitance CPD 26 60 200 22 40 19 34 51 175 18 35 15 30 150 30 26 70 200 23 40 19 34 42 200 23 40 20 34 28 60 8 12 6 10 28 75 8 15 6 13 45 210 17 42 13 36 400 4.5V Q1-Q8 Maximum Output Rising and Falling Time 14 Parameter Min 5 25 29 Max CL=50pF 200 40 40 15 13 2V tdis 74HC595 Vcc pF 34 187 37 32 250 CL=50pF 50 43 219 CL=150pF 44 37 CL=50pF 187 37 32 CL=50pF 250 50 43 CL=150pF 250 50 43 75 CL=50pF 15 13 95 CL=50pF 19 16 265 53 CL=150pF 45 – – PARAMETER MEASUREMENT INFORMATION Vcc Test Point PARAMETER S1 ten RL From Output Under Test CL S2 tdis tPZH tPZL tPHZ tPLZ tpd or tt 5 RL CL 1 kΩ 50 pF 150 pF 1kΩ - or 50 pF 50 pF 150 pF S1 S2 Open Closed Closed Open Open Closed Closed Open Open Open or WS74HC595 AC SWITCHING WAVEFORM AND AC TEST CIRCUIT Voltage Waveforms 1. Propagation Delay and Output Transition Times Vcc Input 50% 50% 0V tPLH In-Phase Output tPHL VOH 50% 10% VOL tf tPLH VOH 90% 50% 10% VOL 90% 50% 10% 90% tr Out-of-Phase Output tPHL 90% 50% 10% tf tr Voltage waveforms 2. Enable And Disable Times For 3-State Outputs Output Control (Low-Level Enabling) 50% Vcc 50% 0V Output Waveform1 tPZL tPLZ ≈Vcc 50% 10% ≈Vcc VOL tPZH Output Waveform 2 90% 50% tPHZ VOH ≈0 V Voltage waveforms 3. Setup And Hold and Input Rise And Fall Times Reference Input Vcc 50% 0V tsu Data Input 50% 10% 90% th Vcc 90% 50% 10% tf tr 6 0V WS74HC595 Voltage waveforms 4. Pulse Durations High-Level Pulse 50% Vcc 50% 0V tw Vcc 50% 50% Low-Level Pulse 0V Note: 5. CL includes probe and test-fixture capacitance. 6. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. 7. For clock inputs, fmax is measured when the input duty cycle is 50%. 8. The outputs are measured one at a time, with one input transition per measurement. 9. tPLZ and tPHZ are the same as tdis. 10. tPZL and tPZH are the same as ten. 11. tPLH and tPHL are the same as tpd. PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 15, 1, 2, 3, 4, 5, 6, 7 Q1 – Q8 Parallel data outputs 9 Q8’ Serial data output 10 SRCL Shift register reset input (active low) 11, 12 SRCK, RCK Shift and storage register clock inputs (triggered at positive edge) 13 OE Output enable input (active low) 14 SER Serial data input 8 GND Ground (0V) 16 VCC Positive power supply Q2 1 Q3 Q1 Q4 SER Q5 OE Q6 RCK Q7 SRCK SRCK 14 SRCL Q8 GND 11 Vcc 16 8 9 SER SRCL Q8’ 10 Pin Configuration 12 RCK 9 Q8’ 15 Q1 Q2 1 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 Q8 7 OE 13 Logic Symbol 7 WS74HC595 PAD DIAGRAM SRCK The Coordinate of Each Pad Q8’ Q8 GND SRCL OE RCK Q7 (-615.1, -748.2) Q6 (479.8, 185.0) SER (-398.1, -748.2) Q7 (479.8, 379.6) Q1 Q8 (479.8, 635.4) (-243.3, -762.4) Q6 74HC595 Die Size = 57 mil X 74 mil VCC (118.3, -789.2) GND (105.8, 683.3) Q2 (479.8, -714.6) Q8’ (-199.4, 683.3) Q3 (479.8, -520.6) SRCL (-359.7, 673.2) Q4 (479.8, -264.8) SRCK (-581.0, 689.2) Q5 (479.8, -70.2) RCK Q5 Pad Size = 90 um X 90 um Q4 (-600.9, 534.4) Q3 Note: OE SER Q1 Q2 Substrate should be connected to Vcc or left it open. VCC 8