WS74HC164 8-Bit Serial-in/Parallel-out Shift Register GENERAL DESCRIPTION 74HC164 is fabricated in the high-speed silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices (LS-TTL). This 8-bit Shift Register has AND-gated serial inputs and clear. Each register bit is a D-type master-slave flip-flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables another input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only data meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive edge of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear (CL) input. 74HC164 logic is functionally as well as pin-out compatible with the standard LS164. All inputs are protected from ESD damage by internal diode clamps to Vcc and ground. FEATURES A • Wide operating supply voltage range: 2-6V. • Asynchronous master reset CL active at low • Date serially shifted at the positive edge of clock CK B Q8 Q1 Q7 14 1 Q2 • Low input current: < 1µA. • Low quiescent supply current: 80µA maximum • Output driving capability: standard Q6 WS74HC164 Q3 Q5 Q4 CL 7 GND LOGIC DIAGRAM VCC CK 8 8 CK SERIAL INPUTS A B 1 CK 2 D CK CK Q CK CK Q D CL CL CK CK CK Q D CK Q D CK CK CK Q D CK CK Q D CK Q D CL CL CL CL CL CK Q D CL 9 CL Q1 Q2 3 4 Q4 Q3 5 Q5 6 10 Q6 Q7 11 12 Q8 13 FUNCTIONAL DESCRIPTION 1. Truth Table Inputs CL L H H H H CK X L ↑ ↑ ↑ Outputs A X X H L X B X X H X L Q1 L Q1O H L L Q2 L Q2O Q1N Q1N Q1N … Q8 L Q8O Q7N Q7N Q7N H = High Level (steady state). L= Low Level (steady state) X = don’t care (any input, including transitions) ↑= Transition from low to high level. Q1O , Q2O , Q8O = the level of Q1 , Q2 , Q8 , respectively, before the indicated steady state input conditions were established. Q1N , Q7N = The level of Q1 or Q7 before the most recent ↑ transition of the clock; indicates a one-bit shift. 1 WS74HC164 2. Logic Waveform CL SERIAL INPUTS A B CK Q1 Q2 Q3 Q4 OUTPUTS Q5 Q6 Q7 Q8 CLEAR CLEAR ABSOLUTE MAXIMUM RATINGS Parameter Value Unit - 0.5 ~ + 7.0 V -0.5 to Vcc +0.5 V ±25 mA DC Current Vcc or GND (Icc) ±50 mA Storage Temperature( TSTG) -65 ~ +150 ℃ 500 mW DC supply voltage (Vcc) DC input or output Voltage (VIN, VOUT) DC Current Drain per pin, any output (Iout) Power Dissipation (PD ) Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITIONS Parameter DC Supply Voltage (Vcc) Min. 2 Input / output Voltage (VIN, VOUT) VIH High-level Input Voltage 0 Vcc = 2 V 1.5 Vcc = 4.5 V 3.15 Vcc = 6 V 4.2 Typ. 5 Max. 6 Unit V Vcc V V Vcc = 2 V 0.5 Vcc = 4.5 V Vcc = 6 V 1.35 1.8 Input Rise/Fall Times (tr/tf） Vcc = 2 V Vcc = 4.5 V Vcc = 6 V 1000 500 400 ns Operating Temperature (TA) 74HC164 +85 ℃ VIL Low-level Input Voltage Note 2: -40 V All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. 2 WS74HC164 DC ELECTRICAL CHARACTERISTICS ( apply across temperature range unless otherwise specified) o Parameter Test Conditions 2V 1.9 1.998 1.9 4.4 4.499 4.4 6V 5.9 5.999 5.9 IOH = -4mA 4.5V 3.98 4.3 3.84 IOH = -5.2mA 6V 5.48 5.8 5.34 VI=VIH or VIL Max. Unit V 2V 0.002 0.1 0.1 4.5V 0.001 0.1 0.1 6V 0.001 0.1 0.1 IOH = 4mA 4.5V 0.17 0.26 0.33 IOH = 5.2mA 6V 0.15 0.26 0.33 ±0.1 ±100 ±1000 nA 8 80 µA 10 10 pF IOH = 20uA VOL Min. 4.5V IOH = -20uA VOH TA=-40~85 ℃ TA＝25 C Min. Typ. Max. Vcc VI=VIH or VIL II VI = VCC or 0 6V ICC VI = VCC or 0, IO = 0 6V Ci 3 2V～6V V TIMING REQUIREMENTS OVER RECOMMENDED OPERATING TEMPERATURE RANGE (unless otherwise noted) o fclock Parameter Vcc Clock frequency 2V 4.5V 6V CL low tw Pulse duration CK High or low Data ts Setup time （before CK↑） CL inactive th Hold time （Data after CK↑） TA＝25 C Min. Max. TA=-40~85 ℃ Max. Unit 6 31 5 25 MHz 36 28 Min. 2V 100 125 4.5V 20 25 6V 17 21 2V 80 100 4.5V 16 20 6V 14 18 2V 100 125 4.5V 20 25 6V 17 21 2V 100 125 4.5V 20 25 6V 17 21 2V 5 5 4.5V 5 5 6V 5 5 3 ns ns ns WS74HC164 AC ELECTRICAL CHARACTERISTICS (CL=50pF) From （Input） Parameter To （Output） fmax tPHL CL tpd Any Q CK Any Q tt o Vcc TA＝25 C Min. Typ. Max. 2V 6 10 5 4.5V 31 54 25 6V 36 62 28 ℃ Max. 2V 140 205 255 28 41 51 6V 24 35 46 2V 115 175 220 4.5V 23 35 44 6V 20 30 38 2V 38 75 95 4.5V 8 15 19 6V 6 13 16 Test Conductions o TA=25 C, NO LOAD Typ. 135 CPD determines the no load dynamic power consumption , PD=CPD* Vcc load dynamic current consumption, Is = CPD * Vcc* fi + Icc. 2 * fi + Icc * Vcc, and the no 1/f MAX 50% 50% 10% tf VCC 90% GND tr tw (CK) VCC DATA 50% 50% GND th tw (CL) VCC 50% CLEAR 50% GND ts (CL) tPHL tPLH VOH 50% Q 50% 50% VOL tPHL AC Switching Waveform 4 ns Unit pF ts (DATA) 90% 50% 10% ns ns AC SWITCHING WAVEFORM AND AC TEST CIRCUIT CLOCK Unit MHz 4.5V Parameter Cpd Power Dissipation Capacitance Note 3 : TA=-40~85 Min. WS74HC164 Q1 Q2 A INPUTS Q3 B Q4 CL Q5 Q6 CK Q7 Q8 CL AC Testing Circuit PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 1, 2 A, B Data Inputs 3, 4, 5, 6, 10, 11, 12, 13 Q1 – Q8 Outputs 7 GND Ground (0V) 8 CK Clock input (active at rising edge) 9 CL Master reset input (active at Low) 14 VCC Positive power supply A 14 1 VCC B 1 2 Q8 Q1 Q7 Q2 Q6 Q3 Q5 8 Q4 CL 9 GND 7 A B Pin Configuration (DIP14) 3 Q2 4 Q3 5 Q4 6 Q5 10 CK Q6 11 CL Q7 12 Q8 13 CK 8 Q1 Logic Symbol PAD DIAGRAM Q7 Q8 CL HC164 Vcc The Coordinate of Each Pad Q5 Q6 CK Die Size = 46 mil x 49 mil GND A Pad size = 90 um x 90 um B Q1 Q4 Q2 Q1 (-395.1, -452.8) Q5 (305.0, 362.8) Q2 (-138.3, -452.8) Q6 ( 48.2, 362.8) Q3 ( 149.9, -452.8) Q7 (-240.0, 362.8) Q4 (355.4, -308.2) Q8 (-445.5, 214.6) GND (355.4, - 82.2) Vcc (-445.5, - 3.8) CK (338.7, 61.8) A (-428.8, -148.8) CL (340.6, 201.8) B (-430.7, -288.8) Q3 Note 4: 5 Substrate should be connected to Vcc or left it open.