0 XC95144 In-System Programmable CPLD R DS067 (v5.7) May 28, 2009 0 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block (FB) - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. • • • • • • • • • • • Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device. 600 nce orma erf igh P (480) H Typical ICC (mA) • Power Management 400 (320) wer w Po (300) Lo 200 (160) 0 50 100 Clock Frequency (MHz) DS067_01_110101 Figure 1: Typical ICC vs. Frequency for XC95144 © 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 1 R XC95144 In-System Programmable CPLD 3 1 JTAG Port JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O Fast CONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 18 I/O/GSR 2 Function Block 4 Macrocells 1 to 18 I/O/GTS 36 18 Function Block 8 Macrocells 1 to 18 DS067_02_110101 Figure 2: XC95144 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 2 R XC95144 In-System Programmable CPLD Absolute Maximum Ratings Symbol Description Value Units –0.5 to 7.0 V VCC Supply voltage relative to GND VIN Input voltage relative to GND –0.5 to VCC + 0.5 V VTS Voltage applied to 3-state output –0.5 to VCC + 0.5 V TSTG Storage temperature (ambient) –65 to +150 oC +150 oC TJ Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial TA = 0oC to 70oC Industrial TA = –40oC to +85oC Commercial TA = 0oC to 70oC Industrial TA = –40oC to +85oC Supply voltage for output drivers for 3.3V operation Min Max Units 4.75 5.25 V 4.5 5.5 4.75 5.25 4.5 5.5 3.0 3.6 V VIL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 VCCINT + 0.5 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter TDR Data Retention NPE Program/Erase Cycles (Endurance) Min Max Units 20 - Years 10,000 - Cycles DC Characteristic Over Recommended Operating Conditions Symbol Min Max Units IOH = –4.0 mA, VCC = Min 2.4 - V Output high voltage for 3.3V outputs IOH = –3.2 mA, VCC = Min 2.4 - V Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V IIL Input leakage current VCC = Max VIN = GND or VCC - ±10 μA IIH I/O high-Z leakage current VCC = Max VIN = GND or VCC - ±10 μA CIN I/O capacitance VIN = GND f = 1.0 MHz - 10 pF ICC Operating supply current (low power mode, active) VI = GND, No load f = 1.0 MHz 160 (Typical) VOH VOL Parameter Output high voltage for 5V outputs DS067 (v5.7) May 28, 2009 Product Specification Test Conditions mA www.xilinx.com 3 R XC95144 In-System Programmable CPLD AC Characteristics XC95144-7 Symbol Parameter XC95144-10 XC95144-15 Min Max Min Max Min Max Units - 7.5 - 10.0 - 15.0 ns 4.5 - 6.0 - 8.0 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - 4.5 - 6.0 - 8.0 ns 16-bit counter frequency 125.0 - 111.1 - 95.2 - MHz Multiple FB internal operating frequency 83.3 - 66.7 - 55.6 - MHz TPSU I/O setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns TPH I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns P-term clock output valid - 8.5 - 10.0 - 12.0 ns TOE GTS to output valid - 5.5 - 6.0 - 11.0 ns TOD GTS to output disable - 5.5 - 6.0 - 11.0 ns TPOE Product term OE to output enabled - 9.5 - 10.0 - 14.0 ns TPOD Product term OE to output disabled - 9.5 - 10.0 - 14.0 ns TWLH GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - ns Asynchronous preset/reset pulse width (High or Low) 7.0 - 7.5 - 8.0 - ns TCO fCNT(1) fSYSTEM(2) TPCO TAPRPW Notes: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type Device Output R2 VCCIO VTEST R1 R2 CL 5.0V 5.0V 3.3V 3.3V 160Ω 120Ω 35 pF 260Ω 360Ω 35 pF CL DS067_03_110101 Figure 3: AC Load Circuit DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 4 R XC95144 In-System Programmable CPLD Internal Timing Parameters XC95144-7 Symbol Parameter XC95144-10 XC95144-15 Min Max Min Max Min Max Units Buffer Delays TIN Input buffer delay - 2.5 - 3.5 - 4.5 ns TGCK GCK buffer delay - 1.5 - 2.5 - 3.0 ns TGSR GSR buffer delay - 4.5 - 6.0 - 7.5 ns TGTS GTS buffer delay - 5.5 - 6.0 - 11.0 ns TOUT Output buffer delay - 2.5 - 3.0 - 4.5 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 3.0 - 3.0 - 2.5 ns TPTSR Product term set/reset delay - 2.0 - 2.5 - 3.0 ns TPTTS Product term 3-state delay - 4.5 - 3.5 - 5.0 ns - 0.5 - 1.0 - 3.0 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 1.5 - 2.5 - 3.5 - ns THI Register hold time 3.0 - 3.5 - 4.5 - ns TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 ns TAOI Register async. S/R to output delay - 6.5 - 7.0 - 8.0 ns TRAI Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - ns TLOGI Internal logic delay - 2.0 - 2.5 - 3.0 ns Internal low power logic delay - 10.0 - 11.0 - 11.5 ns TLOGILP Feedback Delays TF FastCONNECT feedback delay - 8.0 - 9.5 - 11.0 ns TLF Function block local feedback delay - 4.0 - 3.5 - 3.5 ns Time Adders TPTA(1) Incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns TSLEW Slew-rate limited delay - 4.0 - 4.5 - 5.0 ns Notes: 1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 5 R XC95144 In-System Programmable CPLD XC95144 I/O Pins Function Block Macrocell 1 1 TQ100 PQ100 PQ160 – – 25 BScan Order Function Block Macrocell TQ100 429 3 1 – – 43 321 25[1] 35[1] 318[1] PQ100 PQ160 BScan Order 1 2 11 13 18 426 3 2 23[1] 1 3 12 14 19 423 3 3 – – 45 315 1 4 – – 27 420 3 4 – – 48 312 1 5 13 15 21 417 3 5 24 26 36 309 1 6 14 16 22 414 3 6 25 27 37 306 1 7 – – 32 411 3 7 – – 50 303 1 8 15 17 23 408 3 8 27[1] 29[1] 42[1] 300[1] 1 9 16 18 24 405 3 9 28 30 44 297 1 10 – – 34 402 3 10 – – 52 294 1 11 17 19 26 399 3 11 29 31 47 291 1 12 18 20 28 396 3 12 30 32 49 288 1 13 – – 38 393 3 13 – – 53 285 1 14 19 21 29 390 3 14 32 34 54 282 1 15 20 22 30 387 3 15 33 35 56 279 1 16 – – 39 384 3 16 – – 55 276 1 17 22[1] 24[1] 33[1] 381[1] 3 17 34 36 57 273 1 18 – – – 378 3 18 – – – 270 2 1 – – 158 375 4 1 – – 132 267 2 2 99[1] 1[1] 159[1] 372[1] 4 2 87 89 140 264 2 3 – – 3 369 4 3 – – 147 261 2 4 – – 5 366 4 4 – – 149 258 2 5 1[1] 3[1] 2[1] 363[1] 4 5 89 91 142 255 2 6 2[1] 4[1] 4[1] 360[1] 4 6 90 92 143 252 2 7 – – 7 357 4 7 – – 150 249 8 3[1] 5[1] 6[1] 354[1] 4 8 91 93 144 246 2 9 4[1] 6[1] 8[1] 351[1] 4 9 92 94 145 243 2 10 – – 9 348 4 10 – – 151 240 2 11 6 8 11 345 4 11 93 95 146 237 2 12 7 9 12 342 4 12 94 96 148 234 2 13 – – 14 339 4 13 – – 153 231 2 14 8 10 13 336 4 14 95 97 152 228 2 15 9 11 15 333 4 15 96 98 154 225 2 16 – – 16 330 4 16 – – 155 222 2 17 10 12 17 327 4 17 97 99 156 219 2 18 – – – 324 4 18 – – – 216 2 Notes: 1. Global control pin. Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are fixed. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 6 R XC95144 In-System Programmable CPLD XC95144 I/O Pins (Continued) Function Block Macrocell 5 1 – – 65 213 7 1 – – – 105 5 2 35 37 58 210 7 2 50 52 79 102 5 3 – – 66 207 7 3 – – 84 99 5 4 – – 67 204 7 4 – – 85 96 5 5 36 38 59 201 7 5 52 54 82 93 5 6 37 39 60 198 7 6 53 55 86 90 5 7 – – 74 195 7 7 – – 87 87 5 8 39 41 62 192 7 8 54 56 88 84 5 9 40 42 63 189 7 9 55 57 90 81 5 10 – – 76 186 7 10 – – 89 78 5 11 41 43 64 183 7 11 56 58 92 75 5 12 42 44 68 180 7 12 58 60 95 72 TQ100 PQ100 PQ160 BScan Order Function Block Macrocell TQ100 PQ100 PQ160 BScan Order 5 13 – – 78 177 7 13 – – 91 69 5 14 43 45 69 174 7 14 59 61 96 66 5 15 46 48 72 171 7 15 60 62 97 63 5 16 – – 83 168 7 16 – – 93 60 5 17 49 51 77 165 7 17 61 63 98 57 5 18 – – – 162 7 18 – – – 54 6 1 – – – 159 8 1 – – – 51 6 2 74 76 117 156 8 2 63 65 101 48 6 3 – – 119 153 8 3 – – 105 45 6 4 – – 123 150 8 4 – – 107 42 6 5 76 78 122 147 8 5 64 66 102 39 6 6 77 79 124 144 8 6 65 67 103 36 6 7 – – 125 141 8 7 – – 109 33 6 8 78 80 126 138 8 8 66 68 104 30 6 9 79 81 129 135 8 9 67 69 106 27 6 10 – – 128 132 8 10 – – 112 24 6 11 80 82 133 129 8 11 68 70 108 21 6 12 81 83 134 126 8 12 70 72 111 18 6 13 – – 130 123 8 13 – – 114 15 6 14 82 84 135 120 8 14 71 73 113 12 6 15 85 87 138 117 8 15 72 74 115 9 6 16 – – 131 114 8 16 – – 118 6 6 17 86 88 139 111 8 17 73 75 116 3 6 18 – – – 108 8 18 – – – 0 Notes: 1. Global control pin. Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are fixed. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 7 R XC95144 In-System Programmable CPLD XC95144 Global, JTAG, and Power Pins Pin Type TQ100 PQ100 PQ160 I/O/GCK1 22 24 33 I/O/GCK2 23 25 35 I/O/GCK3 27 29 42 I/O/GTS1 3 5 6 I/O/GTS2 4 6 8 I/O/GTS3 1 3 2 I/O/GTS4 2 4 4 I/O/GSR 99 1 159 TCK 48 50 75 TDI 45 47 71 TDO 83 85 136 TMS 47 49 73 VCCINT 5V 5, 57, 98 7, 59, 100 10, 46, 94, 157 VCCIO 3.3V/5V 26, 38, 51, 88 28, 40, 53, 90 1, 41, 61, 81, 121, 141 GND 100, 21, 31, 44, 62, 69, 75, 84 2, 23, 33, 46, 64, 71, 77, 86 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160 No Connects – – – DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 8 R XC95144 In-System Programmable CPLD Device Part Marking and Ordering Combination Information R XC95xxx TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XC95144-7PQ100C 7.5 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C XC95144-7PQG100C 7.5 ns Plastic Quad Flat Pack (PQFP); Pb-Free C Device Ordering and Part Marking Number PQG100 100-pin XC95144-7TQ100C 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC95144-7TQG100C 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C XC95144-7PQ160C 7.5 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) C XC95144-7PQG160C 7.5 ns Plastic Quad Flat Pack (PQFP); Pb-Free C PQG160 160-pin XC95144-10PQ100C 10 ns XC95144-10PQG100C 10 ns XC95144-10TQ100C 10 ns TQ100 XC95144-10TQG100C 10 ns XC95144-10PQ160C 10 ns XC95144-10PQG160C 10 ns XC95144-10PQ100I 10 ns XC95144-10PQG100I 10 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C Plastic Quad Flat Pack (PQFP); Pb-Free C 100-pin Thin Quad Flat Pack (TQFP) C TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C PQ160 160-pin PQG100 100-pin PQG160 160-pin PQ100 Plastic Quad Flat Pack (PQFP) C Plastic Quad Flat Pack (PQFP); Pb-Free C Plastic Quad Flat Pack (PQFP) I Plastic Quad Flat Pack (PQFP); Pb-Free I 100-pin PQG100 100-pin XC95144-10TQ100I 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I XC95144-10TQG100I 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I XC95144-10PQ160I 10 ns PQ160 160-pin Plastic Quad Flat Pack (PQFP) I XC95144-10PQG160I 10 ns Plastic Quad Flat Pack (PQFP); Pb-Free I PQG160 160-pin XC95144-15PQ100C 15 ns XC95144-15PQG100C 15 ns XC95144-15TQ100C 15 ns TQ100 XC95144-15TQG100C 15 ns XC95144-15PQ160C 15 ns XC95144-15PQG160C 15 ns XC95144-15PQ100I 15 ns XC95144-15PQG100I 15 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C Plastic Quad Flat Pack (PQFP); Pb-Free C 100-pin Thin Quad Flat Pack (TQFP) C TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C PQ160 160-pin PQG100 100-pin PQG160 160-pin PQ100 Plastic Quad Flat Pack (PQFP) C Plastic Quad Flat Pack (PQFP); Pb-Free C Plastic Quad Flat Pack (PQFP) I Plastic Quad Flat Pack (PQFP); Pb-Free I 100-pin PQG100 100-pin XC95144-15TQ100I 15 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I XC95144-15TQG100I 15 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 9 R XC95144 In-System Programmable CPLD Device Ordering and Part Marking Number Speed (pin-to-pin delay) XC95144-15PQ160I 15 ns XC95144-15PQG160I 15 ns Pkg. Symbol No. of Pins PQ160 160-pin Package Type PQG160 160-pin Operating Range(1) Plastic Quad Flat Pack (PQFP) I Plastic Quad Flat Pack (PQFP); Pb-Free I Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C Additional Information XC9500 data sheets and application notes. Packages Revision History The following table shows the revision history for this document. Date Version Revision 12/04/98 4.0 Update AC characteristics and internal parameters. 06/18/03 5.0 Updated format. 08/21/03 5.1 Updated Package Device Marking Pin 1 orientation. 11/06/03 5.2 Update pin count on PQ160 packages. 02/16/04 5.3 Correct GTS pin information by removing rows on GTS3 GTS4 from table on page 8. Add links to additional information. 04/15/05 5.4 Added asynchronous preset/reset pulse width specification (TAPRPW). 01/03/06 5.5 Added GTS3 and GTS4 pins to table on page 8. 04/03/06 5.6 Added Warranty Disclaimer. Added Pb-Free package ordering information. 05/28/09 5.7 Removed table note reference from Function Block 2, Macrocell 3 in XC95144 I/O Pins. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS067 (v5.7) May 28, 2009 Product Specification www.xilinx.com 10