0 XC9572XL High Performance CPLD R DS057 (v2.0) April 3, 2007 0 0 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) - Pb-free available for all packages Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package Product Specification cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for overview. Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f where: MCHS = # macrocells in high-speed configuration PTHS = average number of high-speed product terms per macrocell MCLP = # macrocells in low power configuration PTLP = average number of low power product terms per macrocell f = maximum clock frequency MCTOG = average % of flip-flops toggling per clock (~12%) This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx WARNING: Programming temperature range of TA = 0° C to +70° C Description The XC9572XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communi© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS057 (v2.0) April 3, 2007 Product Specification www.xilinx.com 1 XC9572XL High Performance CPLD R application note XAPP114, “Understanding XC9500XL CPLD Power.” 125 178 MHz Typical ICC (mA) 100 h Hig 75 50 P Low Pe ow rfor m e anc 104 MHz er 25 0 50 100 200 150 Clock Frequency (MHz) DS057_01_010102 Figure 1: Typical ICC vs. Frequency for XC9572XL 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 Function Block 1 18 I/O Macrocells 1 to 18 I/O Fast CONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 54 Function Block 2 18 Macrocells 1 to 18 54 Function Block 3 18 Macrocells 1 to 18 I/O 3 I/O/GCK 54 1 I/O/GTS Function Block 4 18 I/O/GSR 2 Macrocells 1 to 18 DS057_02_082800 Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification XC9572XL High Performance CPLD R Absolute Maximum Ratings(2) Symbol Description Value Units VCC Supply voltage relative to GND –0.5 to 4.0 V VIN GND(1) –0.5 to 5.5 V VTS Input voltage relative to Voltage applied to 3-state TSTG Storage temperature TJ Junction temperature output(1) (ambient)(3) –0.5 to 5.5 V –65 to +150 oC +150 oC Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Min Max Units 3.0 3.6 V 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V Commercial TA = 0oC to 70oC Supply voltage for internal logic and input buffers Industrial TA = –40oC to +85oC VIL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter Min Max Units 20 - Years TDR Data Retention NPE Program/Erase Cycles (Endurance) 10,000 - Cycles VESD Electrostatic Discharge (ESD) 2,000 - Volts DC Characteristic Over Recommended Operating Conditions Symbol VOH VOL Parameter Test Conditions Min Max Units Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V Output high voltage for 2.5V outputs IOH = –500 μA 90% VCCIO - V Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V Output low voltage for 2.5V outputs IOL = 500 μA - 0.4 V IIL Input leakage current VCC = Max; VIN = GND or VCC - ±10 μA IIH I/O high-Z leakage current VCC = Max; VIN = GND or VCC - ±10 μA IIH I/O high-Z leakage current VCC = Max; VCCIO = Max; VIN = GND or 3.6V - ±10 μA VCC Min < VIN < 5.5V - ±50 μA - 10 pF CIN I/O capacitance VIN = GND; f = 1.0 MHz ICC Operating supply current (low power mode, active) VIN = GND, No load; f = 1.0 MHz DS057 (v2.0) April 3, 2007 Product Specification www.xilinx.com 20 (Typical) mA 3 XC9572XL High Performance CPLD R AC Characteristics Symbol Parameter XC9572XL-5 XC9572XL-7 XC9572XL-10 Min Max Min Max Min Max Units - 5.0 - 7.5 - 10.0 ns 3.7 - 4.8 - 6.5 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - 3.5 - 4.5 - 5.8 ns fSYSTEM Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz TPSU I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns TPH I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns P-term clock output valid - 5.5 - 7.7 - 10.2 ns TOE GTS to output valid - 4.0 - 5.0 - 7.0 ns TOD GTS to output disable - 4.0 - 5.0 - 7.0 ns TPOE Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns TPOD Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns TAO GSR to output valid - 10.0 - 12.0 - 14.5 ns TPAO P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns TWLH GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns TPLH P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns TCO TPCO VTEST R1 Output Type VCCIO VTEST R1 R2 CL 3.3V 3.3V 320 Ω 360 Ω 35 pF 2.5V 2.5V 250 Ω 660 Ω 35 pF Device Output R2 CL DS058_03_081500 Figure 3: AC Load Circuit 4 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification XC9572XL High Performance CPLD R Internal Timing Parameters Symbol Parameter XC9572XL-5 XC9572XL-7 XC9572XL-10 Min Max Min Max Min Max Units Buffer Delays TIN Input buffer delay - 1.5 - 2.3 - 3.5 ns TGCK GCK buffer delay - 1.1 - 1.5 - 1.8 ns TGSR GSR buffer delay - 2.0 - 3.1 - 4.5 ns TGTS GTS buffer delay - 4.0 - 5.0 - 7.0 ns TOUT Output buffer delay - 2.0 - 2.5 - 3.0 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 1.6 - 2.4 - 2.7 ns TPTSR Product term set/reset delay - 1.0 - 1.4 - 1.8 ns TPTTS Product term 3-state delay - 5.5 - 7.2 - 7.5 ns - 0.5 - 1.3 - 1.7 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.3 - 2.6 - 3.0 - ns THI Register hold time 1.4 - 2.2 - 3.5 - ns TECSU Register clock enable setup time 2.4 - 2.6 - 3.0 - ns TECHO Register clock enable hold time 1.4 - 2.2 - 3.5 - ns TCOI Register clock to output valid time - 0.4 - 0.5 - 1.0 ns TAOI Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns TRAI Register async. S/R recover before clock TLOGI Internal logic delay - 1.0 - 1.4 - 1.8 ns Internal low power logic delay - 5.0 - 6.4 - 7.3 ns - 1.9 - 3.5 - 4.2 ns Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns TLOGILP 5.0 7.5 10.0 ns Feedback Delays TF Fast CONNECT II feedback delay Time Adders TPTA TSLEW DS057 (v2.0) April 3, 2007 Product Specification www.xilinx.com 5 XC9572XL High Performance CPLD R XC9572XL I/O Pins(4) Function Block Macrocell 1 1 - - - - 16 213 3 1 - - - - 41 105 1 2 1 39 D7 8 13 210 3 2 11 5 B5 22 32 102 1 3 - - D4 12 18 207 3 3 - - C4 31 49 99 1 4 - - - 13 20 204 3 4 - - - 32 50 96 1 5 2 40 D6 9 14 201 3 5 12 6 A4 24 35 93 1 6 3 41 C7 10 15 198 3 6 - - - 34 53 90 1 7 - - - - 25 195 3 7 - - - - 54 87 1 8 4 42 C6 11 17 192 3 8 13 7 B4 25 37 84 1 9 5(1) 43(1) B7(1) 15(1) 22(1) 189 3 9 14 8 A3 27 42 81 1 10 - - - 18 28 186 3 10 - - D3 39 60 78 1 11 6(1) 44(1) B6(1) 16(1) 23(1) 183 3 11 18 12 B2 33 52 75 1 12 - - - 23 33 180 3 12 - - - 40 61 72 1 13 - - - - 36 177 3 13 - - - - 63 69 1 14 7(1) 1(1) A7(1) 17(1) 27(1) 174 3 14 19 13 B1 35 55 66 1 15 8 2 A6 19 29 171 3 15 20 14 C2 36 56 63 1 16 - - - - 39 168 3 16 24 18 D2 42 64 60 1 17 9 3 C5 20 30 165 3 17 22 16 C3 38 58 57 1 18 - - - - 40 162 3 18 - - - - 59 54 2 1 - - - - 87 159 4 1 - - - - 65 51 2 2 35 29 F4 60 94 156 4 2 25 19 E1 43 67 48 2 3 - - - 58 91 153 4 3 - - - 46 71 45 2 4 - - - 59 93 150 4 4 - - - 47 72 42 2 5 36 30 G5 61 95 147 4 5 26 20 E2 44 68 39 2 6 37 31 F5 62 96 144 4 6 - - E4 49 76 36 PC44 VQ44 CS48 VQ64 BScan TQ100 Order Func -tion Block Macrocell PC44 VQ44 CS48 VQ64 TQ100 BScan Order 2 7 - - - - 3(2) 141 4 7 - - - - 77 33 2 8 38 32 G6 63 97 138 4 8 27 21 F1 45 70 30 2 9 39(1) 33(1) G7(1) 64(1) 99(1) 135 4 9 - - - - 66 27 2 10 - - - 1 1 132 4 10 - - - 51 81 24 2 11 40(1) 34(1) F6(1) 2(1) 4(1) 129 4 11 28 22 G1 48 74 21 2 12 - - - 4 6 126 4 12 - - - 52 82 18 2 13 - - - - 8 123 4 13 - - - - 85 15 2 14 42(3) 36(3) E6(3) 5(3) 9(3) 120 4 14 29 23 F2 50 78 12 2 15 43 37 E7 6 11 117 4 15 33 27 E3 56 89 9 2 16 - - - - 10 114 4 16 - - - - 86 6 2 17 44 38 E5 7 12 111 4 17 34 28 G4 57 90 3 2 18 - - - - 92 108 4 18 - - - - 79 0 Notes: 1. Global control pin. 2. GTS1 for TQ100. 3. GTS1 for PC44, VQ44, CS48, and VQ64. 4. The pin-outs are the same for Pb-free versions of packages. 6 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification XC9572XL High Performance CPLD R XC9572XL Global, JTAG and Power Pins(1) Pin Type PC44 VQ44 CS48 VQ64 TQ100 I/O/GCK1 5 43 B7 15 22 I/O/GCK2 6 44 B6 16 23 I/O/GCK3 7 1 A7 17 27 I/O/GTS1 42 36 E6 5 3 I/O/GTS2 40 34 F6 2 4 I/O/GSR 39 33 G7 64 99 TCK 17 11 A1 30 48 TDI 15 9 B3 28 45 TDO 30 24 G2 53 83 TMS 16 10 A2 29 47 VCCINT 3.3V 21, 41 15, 35 C1, F7 3, 37 5, 57, 98 VCCIO 2.5V/3.3V 32 26 G3 26, 55 26, 38, 51, 88 GND 10, 23, 31 4, 17, 25 A5, D1, F3 14, 21, 41, 54 21, 31, 44, 62, 69, 75, 84, 100 No Connects - - - - 2, 7, 19, 24, 34, 43, 46, 73, 80 Notes: 1. The pin-outs are the same for Pb-free versions of packages. DS057 (v2.0) April 3, 2007 Product Specification www.xilinx.com 7 XC9572XL High Performance CPLD R Device Part Marking and Ordering Combination Information R XC95xxxXL TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · · · · Device Ordering and Part Marking Number XC9572XL-5PC44C XC9572XL-5VQ44C XC9572XL-5CS48C XC9572XL-5VQ64C XC9572XL-5TQ100C XC9572XL-7PC44C XC9572XL-7VQ44C XC9572XL-7CS48C XC9572XL-7VQ64C XC9572XL-7TQ100C XC9572XL-7PC44I XC9572XL-7VQ44I XC9572XL-7CS48I XC9572XL-7VQ64I XC9572XL-7TQ100I XC9572XL-10PC44C XC9572XL-10VQ44C XC9572XL-10CS48C XC9572XL-10VQ64C XC9572XL-10TQ100C XC9572XL-10PC44I XC9572XL-10VQ44I XC9572XL-10CS48I XC9572XL-10VQ64I XC9572XL-10TQ100I Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = CS48, C2 = CSG48. Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns Pkg. Symbol PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 PC44 VQ44 CS48 VQ64 TQ100 No. of Pins 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin Package Type Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Operating Range(1) C C C C C C C C C C I I I I I C C C C C I I I I I Notes: C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C 8 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification XC9572XL High Performance CPLD R Device Ordering and Part Marking Number XC9572XL-5PCG44C XC9572XL-5VQG44C XC9572XL-5CSG48C XC9572XL-5VQG64C XC9572XL-5TQG100C XC9572XL-7PCG44C XC9572XL-7VQG44C XC9572XL-7CSG48C XC9572XL-7VQG64C XC9572XL-7TQG100C XC9572XL-7PCG44I XC9572XL-7VQG44I XC9572XL-7CSG48I XC9572XL-7VQG64I XC9572XL-7TQG100I XC9572XL-10PCG44C XC9572XL-10VQG44C XC9572XL-10CSG48C XC9572XL-10VQG64C XC9572XL-10TQG100C XC9572XL-10PCG44I XC9572XL-10VQG44I XC9572XL-10CSG48I XC9572XL-10VQG64I XC9572XL-10TQG100I Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns Pkg. Symbol PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 PCG44 VQG44 CSG48 VQG64 TQG100 No. of Pins 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin 44-pin 44-pin 48-ball 64-pin 100-pin Operating Range(1) C C C C C C C C C C I I I I I C C C C C I I I I I Package Type Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Plastic Lead Chip Carrier (PLCC); Pb-free Quad Flat Pack (VQFP); Pb-free Chip Scale Package (CSP); Pb-free Quad Flat Pack (VQFP); Pb-free Thin Quad Flat Pack (TQFP); Pb-free Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C Standard Example: XC9572XL -4 TQ Device Speed Grade Package Type Number of Pins Temperature Range DS057 (v2.0) April 3, 2007 Product Specification 144 C Pb-Free Example: XC9572XL -4 TQ G 144 C Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range www.xilinx.com 9 XC9572XL High Performance CPLD R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Further Reading The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down. Data Sheets, Application Notes, and White Papers. Packaging Revision History The following table shows the revision history for this document. 10 Date Version Revision 09/28/98 1.0 Initial Xilinx release. 08/28/01 1.1 Added VQ44 package. 06/20/02 1.2 Updated ICC equation, page 1. Updated Component Availability table. Added additional IIH test conditions and measurements to DC Characteristics table. 05/27/03 1.3 Updated TSOL from 260 to 220oC. Added Part Marking and updated Ordering Information. 08/21/03 1.4 Updated Package Device Marking Pin 1 orientation. 07/15/04 1.5 Added Pb-free documentation 09/15/04 1.6 Added TAPRPW specification to AC Characteristics. 04/29/05 1.7 No change to documentation. 07/15/05 1.8 Move to Product Specification 03/22/06 1.9 Add Warranty Disclaimer. 04/03/07 2.0 Add programming temperature range warning on page 1. www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification