AKM AK2307LV

ASAHI KASEI
[AK2307/LV]
AK2307/LV
SPEECH CODEC for Digital Key telephone (5.0V/3.3V)
FEATURES
GENERAL DISCREPTION
-
AK2307/LV is an integrated LSI with PCM CODEC,
Voice path control, MIC amplifier and Handset driver
suitable for PBX/KTS digital key telephone, VoIP
Telephone.
-
PCM CODEC is compliant to ITU specification, very
low noise, and low power dissipation CODEC. A-law
and u-law selectable through Serial I/F register.
PCM I/F provides Long/Short frame format and GCI.
The output is 8bit compressed data along with 16bit
linear format.
-
2 MIC AMP for the handset and microphone are
integrated.
A 150 ohm handset driver and an extra 150 ohm
driver for a headset receiver are provided.
Path control and volume control via serial CPU
I/F
programmable tone generator
5.0V+/-5%, 3.3V+/-0.3V single power supply
Low noise, low power consumption
Package
28pin VSOP package
Voice path block consists of Tone generator, Volume
for both TX and RX, Analog inputs, outputs for
Handset speaker and the speaker for hands-free
conversation, and the path control switch.
Side tone can be added internally and its volume
is controlled through serial I/F.
- Package size; 9.8*7.6mm(pin to pin)
- Pin pitch;
0.65mm
MS0190-E-05
2005/12
1
ASAHI KASEI
[AK2307/LV]
BLOCK DIAGRAM
Handset Mic
I/F HANDT4
upto +25dB
HANDT2
HANDT3
TX Digital
Attenuator
VOL1
HANDT1
+14dB SW1
+14dB SW2
SW3
Amp1
Amp3
16 steps
by 1dB
+7 to -8dB
AGC
A/D
8 steps
by 3dB
0 to -21dB
(Back ground
Noise ATT)
Linear
A/u
+0dB
External Mic
I/F
MIC3
MIC1
MIC2
PCM
Interface
16 Steps
Side Tone
by 3dB
Digital ATT
-12 to -57dB
Amp2
PCM CODEC
D/A
RAIN
VOL2
24 steps
by 1dB
0 to -23dB
Handset Receiver
output
0dB/+3dB
VOL3
24 steps
by 1dB
0 to -23dB
+
PAD
0/-9dB
8 steps
by 3dB
+6 to -21dB
DX
DR
FS
RX Digital
Volume
DAOUT
16bit Linear
or
A/u-law
BCLK
Linear
A/u
SW4
SW5
HANDR
-1
150ohm Driver
Tone Gen H
(DTMF-H)
VOL4
Headset Receiver
output
0dB/+3dB
SW6
SW7
Amp5
16 steps
by 3dB
0 to -45dB
HEADO
SW10
150ohm Driver
0dB/+3dB
Speaker output
Amp10
PLLCAP
+
L_ATT
-2.5dB
-1
PLL
Clock generator
Tone Gen L
(DMTF-L)
CPU Interface
VOL5
16 steps
by 2dB
0 to -30dB
CSN
SCLK
DATA
VREF
SW8
Voltage Reference
SW9
SPO
TAGND
RAGND
10K ohm Driver
AVDD
AVSS
DVDD
DVSS
EXRIN
MS0190-E-05
2005/12
2
ASAHI KASEI
[AK2307/LV]
PIN ASSIGNMENT
HANDR
HEADO
VSS
VDD
FS
DX
BCLK
DR
DATA
SCLK
CSN
AVDD
MIC2
MIC1
1
2 TOP VIEW
3
4
5
6
7
8
9
10
11
12
13
14
MS0190-E-05
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PLLCAP
SPO
EXRIN
RAIN
DAOUT
RAGND
VREF
AVSS
TAGND
HANDT3
HANDT2
HANDT1
HANDT4
MIC3
2005/12
3
ASAHI KASEI
[AK2307/LV]
PIN CONDITIONS
Pin types;
NIN:
Normal Input
NOUT: Normal Output
TOUT: Tri-state output
AOUT: Analog output
PWR:
Power supply
AIN:
Analog Input
Table 1
Name
HANDT2
HANDT3
HANDT1
HANDT4
HANDR
MIC3
MIC2
MIC1
DAOUT
RAIN
HEADO
SPO
EXRIN
DATA
SCLK
CSN
DR
DX
BCLK
FS
DVSS
DVDD
AVSS
AVDD
PLLCAP
TAGND
RAGND
VREF
Type
Max
MIn
Cap load Res load
Pin function
comment
AIN
AIN
AOUT
AIN
AOUT
AIN
AIN
AOUT
AOUT
AIN
AOUT
AOUT
AIN
I/O
Analog input for Handset microphone
Analog input for Handset microphone
OPamp output for Handset microphone
Analog input for A/D converter
Analog output for Handset receiver
1000pF 150ohm
nd
2 Analog input for A/D converter
Analog input for External microphone
Output of External microphone amplifier
Analog output of D/A converter
Analog input to RX voice path
RX output for Headset receiver
1000pF 150ohm
RX output for External Speaker Driver
20pF 10kohm
External input for Speaker pre-driver
Data input for internal register access
50pF
Serial data clock for internal register
NIN
access
NIN Chip select input
NIN RX PCM data serial input
TOUT TX PCM data serial output. Tri-state output 50pF
NIN Bit clock input for DR, DX
NIN 8KHz frame sync signal input for PCM I/F
PWR Power supply for digital block:0V
PWR Power supply for digital block: 3.3V
PWR Power supply for Analog block:0V
PWR Power supply for Analog block: 3.3V
Output to connect the PLL loop filter
1.0uF external
AOUT
Capacitance
capacitance
1.0uF external
AOUT TX side Analog ground output.
capacitance
1.0uF external
AOUT RX side Analog ground output
capacitance
1.0uF external
AOUT Voltage reference output
capacitance
MS0190-E-05
2005/12
4
ASAHI KASEI
[AK2307/LV]
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Power Supply Voltages
Analog/Digital Power Supply
VDD
-0.3
6.5
VSS Voltage
VSS
-0.1
0.1
Digital Input Voltage
VTD
-0.3
VDD+0.3
Analog Input Voltage
VTA
-0.3
VDD+0.3
Input current (except power supply pins)
IIN
-10
10
Storage Temperature
Tstg
-55
125
Warning: Exceeding absolute maximum ratings may cause permanent damage.
Normal operation is not guaranteed at these extremes.
Units
V
V
V
V
mA
o
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supplies
Analog/Digital power supply( AK2307LV)
VDD
Analog/Digital power supply( AK2307)
VDD
Ambient Operating Temperature
Ta
Frame Sync Frequency
FS
Note) All voltages reference to ground : VSS=0V
MS0190-E-05
Min
Typ
Max
Units
3.0
4.75
-10
-
3.3
5.0
3.6
5.25
85
-
V
V
o
C
kHz
8
2005/12
5
ASAHI KASEI
[AK2307/LV]
FUNCTIONAL
DISCRIPTIONS
1. SERIAL INTERFACE
The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN
pin.
1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write.
The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers.
Table1-A CPU I/F ADDRESS/DATA STRUCTURE
B15 B14 B13 B12 B11 B10
B9
B8
I2
I1
I0
A3
Instruction code
(3 bit )
A2
A1
A0
Address
(4bit)
*
B7
B6
B5
B4
B3
B2
B1
B0
D7
D6
D5
D4
D3
D2
D1
D0
*
Data for internal registers
(8bit)
*)Dummy bit for adjusting the I/O timing when reading register.
Table1-B
INSTRUCTION CODE
I2
I1
I0
1
1
0
1
1
1
Read/Write
Read
Write
No action
Others
1-2
Timing of the Serial Interface
SCLK and DATA timing in WRITE/READ operation
(1) Input data are loaded into the internal shift register at the rising edge of SCLK.
(2) The rising edge of SCLK is counted after the falling edge of CSN.
(3) When CSN is “L” and more than 16 SCLK pulses:
th
[WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse.
th
[READ] DATA pin becomes an input pin at the falling edge of the SCLK 16 pulse.
CSN timing and WRITE/READ CANCELLATION
th
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse.
th
(2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse.
SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE)
(1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and
st
data after 1 write or read operation.
st
nd
(2) It is not necessary to make CSN high between 1 operation and 2 operation.
MS0190-E-05
2005/12
6
ASAHI KASEI
[AK2307/LV]
WRITE
Continuous SCLK
Goes up anytime
after SCLK 16th pulse and before 32nd pulse
CSN
SCLK
1
Z
DATA
2
1
3
1
4
1
5
0
6
0
Instruction
Code
7
0
8
0
9
16
D7
*
Z
D0
Write data to
address”000”
Address
“0000”
1
2
1
WRITE at the rising
edge of SCLK 16th
pulse
1
3
4
8
1
9
D7
15
D1
16
D0
Z
Write data
Instruction
Code
Burst SCLK
SCLK can be stoped at “H” level or “L” level at anytime during the write cycle. After resuming the SCLK, write cycle is
retrieved normally.
Goes up anytime
after SCLK 16th pulse and 32nd pulse
CSN
SCLK
1
Z
DATA
2
1
3
1
4
1
5
0
6
0
Instruction
Code
7
0
8
0
9
16
D7
*
D0
Write data to
address “000”
Address
”0000”
Z
WRITE at the rising
edge of SCLK 16th
pulse
CANCELLATION
CSN goes “H” before the rising
edge of 16th SCLK pulse
CSN
SCLK
DATA
1
Z
1
2
1
3
1
Instruction
Code
4
0
5
0
6
0
Address
”0000”
7
0
8
*
9
D7
16
Z
D0
Write data to
address”000”
Write is not
Excuted
MS0190-E-05
Z
DATA pin: Input mode
(Hi-Z)
2005/12
7
ASAHI KASEI
[AK2307/LV]
SERIAL ACCESS
Serial access can be done by CSN staying “L” during the serise of write cycle.
CSN
SCLK
DATA
1
Z
1
2
1
3
1
4
0
5
0
6
0
7
0
8
D7
*
Address
”0000”
Instruction
Code
9
16
1
Z
D0
1
Write data to
Address”000”
2
3
1
1
8
4
1
9
15
16
Z
D1 D0
D7
Write data
Instruction
Code
EXCUTE!
EXCUTED!
READ
Continuous SCLK
Can be going up at anytime
after SCLK 16th pulse and before 32nd pulse
CSN
SCLK
DATA
1
Z
1
2
1
3
0
4
5
A3 A2
Read
Instruction
6
7
A1 A0
8
Z
9
D7
16
1
Z
D0
1
Read Data
Address
2
1
3
1
4
0
Read
Instruction
8
9
D7
15
16
D1 D0
Z
Read Data
Read period
until the earlier edge of either CSN rising or SCLK 16th pulse
falling
Data output starts at the falling edge of SCLK 8th pulse
Burst SCLK
Can be going up at anytime
after SCLK 16th pulse and before 32nd pulse
CSN
SCLK
DATA
1
Z
1
2
1
3
0
Read
Instruction
4
5
A3 A2
6
7
A1 A0
Address
8
Z
9
16
D0
D7
Z
Read Data
Read output starts at the falling edge of SCLK 8th pulse
MS0190-E-05
2005/12
8
ASAHI KASEI
[AK2307/LV]
SERIAL ACCESS
Serial access can be done by CSN staying “L” during the serise of read cycle
CSN
SCLK
DATA
1
Z
1
2
1
3
0
4
5
0
0
6
7
0
0
Z
9
D7
16
1
Z
D0
2
1
Read data
Address
”0000”
Read
Instruction
8
1
3
1
4
8
9
15
16
Z
0
Read
Instruction
READ
EXCUTED!
READ
EXCUTED!
DISCORD OF INSTRUCTION CODE
CSN
SCLK
DATA
Z
1
2
3
4
5
I2
I1
I0
IA3
A2
IInstructions except specified
0bb
10b
(b=0 or 1)
6
7
8
9
16
Z
A1 A0
Address
WRITE/READ
NOT EXCUTED!
Z
DATA pin: Input mode
(Hi-Z)
Register Map
Register Type : Read/ Write
Register Name
(Functions)
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
Path Control 1
RX_
RX Pad
Side
PCM_1
PCM_0
u/A-law SW10
SW9
Path Control 2 &
A_gain
-9dB
Tone
PCM Control
2
0
TX Attenuator
VOL1
TX Digital Volume Control
3
RX Volume
Side Tone Attenuator
RX Digital Volume Control
4
0
0
0
0
VOL4
Tone Volume Control
5
0
0
Tone Freq. Select
Tone Generator 1
6
0
L-ATT
Tone Freq. Select
Tone Generator 2
7
0
0
0
VOL2
RX Handset Volume Control
8
0
0
0
VOL3
RX Headset Volume Control
9
VOL5
RX Speaker Volume Control
A
AGC_ON
Falling time
Rising time
Threshold level
AGC Control
B–F
Reserved for test use
Address “1” ; PCM_1/2 ---- Selection of the PCM interface Mode(Long/Short frame, AK130-1,AK130-2, 16bit linear)
Address ”6” ; L-ATT ---- -6dB attenuation for Tone generator-L output in case of DTMF tone generation.
Add
(Hex)
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Bits in which “0” is filled are for test mode activation. Please fill the data “0” for the normal operation.
Bits in which “-“ is filled are for test use and can not write the data from CPU interface. In case the read
operation, data “0” are read from CPU interface.
MS0190-E-05
2005/12
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ASAHI KASEI
2. PCM Data Interface
[AK2307/LV]
AK2307/LV supports 4 PCM data interface modes.
- A/u-Law PCM data mode( Long or Short frame)
This mode is for interface of 64kbps PCM data which are compressed /extended by A -law or u-law. Both Long
frame
and short frame format data are acceptable. The PCM data occupies the first time slot of the PCM data bus which
is specified by the frame sync signal. Please refer to the format diagram.
- 16 bit Linear data Mode
This mode interfaces the 16 bit linear PCM data. PCM CODEC of AK2307/LV operates at 14 bit accuracy. The 2
bits
of the LSB are fixed in the 16 bit data stream.
- AK130 B1 Mode
This mode provides the PCM data Interface to AK130, the TCM transceiver for PBX/KTS system. PCM da ta format
is 64kbps A-law or u-law data. The timing between data and FS is different from the A/u -Law PCM data mode
written above. In this mode the PCM data are transmitted/received via B1 channel , one of the PCM data
channel of the AK130.
- AK130 B2 Mode
This mode provides the PCM data interface to AK130 B2 channel in as same manner as AK130 B1 Mode.
In every modes, the digital voice data are in and out from DR and DX pin and the bit clock and the 8KHz frame sync
signal will be fed via BCLK and FS, respectively. The order of PCM and linear data is MSB first .
Table 2-A Summary of PCM interface modes
Mode
PCM data
format
BCLK rate
frame
signal
Time
slot
A/u-Law PCM data
mode
16bit Linear data
mode
AK130 B1
mode
AK130 B2
mode
A/u-Law
A/u-Law
2.048MHz
LF/SF
auto select
SF
only
AK130 FS
signal
AK130 FS
signal
1 Time slot
16bit
Linear
A/u-Law
64K x N
(N: 1 to 32)
128K x N
(N: 1 to 16)
2.048MHz
st
first 16 bit after
FS signal
xxth time slot
of 2.048MHz(B1 channel)
xxth time slot
of 2.048MHz(B2 channel)
2-1. Selection of the interface mode
These four interface modes are selectable through the CPU register which specified below.
A/u-Law selection is also selectable from the same CPU register and it is effective in the u/ A-law interface mode and
AK130 B1/B2 modes.
Register Name; Path Control 2
ADD
D7
D6
RX
1
Default
0
Register Type : Read Write
D5
D4
D3
D2
D1
D0
PCM_1
PCM_0
u/A
law
SW10
SW9
Pad
Side
Tone
0
0
0
0
0
0
0
PCM_1、0 ; PCM interface mode select
PCM_1
PCM_0
Mode
0
0
A/u-Law PCM data mode
0
1
16bit Linear interface mode
1
0
AK130 B1 mode
1
1
AK130 B2 mode
u/A-law ; PCM compress/Extend format select
A/u-law
Compress/Extend
0
u-law
1
A-law
MS0190-E-05
2005/12
10
ASAHI KASEI
[AK2307/LV]
2-2 Timing and format of the PCM interface
2-2-1 u/A-Law PCM data Mode
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2307/LV occupies
first time slot as is indicated in figures below.
2-2-1-a Signals
- Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal
clock
of the LSI is generated based on this FS signal.
- Bit Clock (BCLK)
BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step.
- PCM data output (DX)
DX is an output signal of 64Kbps PCM u/A -law data. The data is synchronized to the BCLK which determines th e data
rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. In the long frame mode,
th
the LSB bit turns to Hi-impedance at the faster edge of ether FS falling edge or 9 rising edge of BCLK.
- PCM data input (DR)
DR is an input signal of 64Kbps PCM u/A -law data. The data is clocked by BCLK at the falling edge and fed into the D/A
block.
2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection
AK2307/LV monitors the duration of the “H” level of FS and automatically selects LF or SF interface format.
period of FS=”H”
Interface format
more than 2 clocks of BCK
LF
1 clock of BCK
SF
2-2-1-c Frame format of the interface
Long Frame format
1 2 5 u s (8 K H z )
FS
BCLK
DX
DR
7
D o n ’t
c a re
7
6
6
5
5
4
4
3
3
2
2
1
1
0
D o n ’t c a r e
0
Short Frame format
1 2 5 u s (8 K H z )
FS
BCLK
DX
DR
7
D o n ’t
c a re
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
MS0190-E-05
D o n ’t c a re
2005/12
11
ASAHI KASEI
[AK2307/LV]
2-2-2 16 bit Linear PCM data mode
In this mode the 16 bit linear PCM data are interfaced to the outside. This mode is useful to compress/extend the PCM
data by much higher compress rate algorithm than u/A -law algorithm by the external DSP. The AK2307/LV CODEC
operates at 14bit accuracy, thus the least 2 bits are output as fixed value.
2-2-2-a Signals
- Frame Sync signal (FS)
8kHz reference signal which is same as in u/A -law PCM data mode. How the FS pulse H level width should be 1 clo ck
period which is like the short frame FS signal.
- Bit Clock (BCLK)
BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 2.048MHz by 128kHz step which is different
from in the u/A-law PCM data mode.
- PCM data output (DX)
DX is an output signal of 128Kbps linear PCM data. The data is synchronized to the BCLK which determines the data
rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output.
- PCM data input (DR)
DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the
D/A
block.
16bti Linear Frame format
125us (8KHz)
FS
BCLK
DX
DR
Hi-Z
MSB First
1
2
3
12
13
14
*
MSB First
1
2
3
12
13
14
Hi-Z
*
*
*
Hi-Z
*
1
1
2-2-3 AK130 B1/B2 Mode
These modes are for connecting the PCM interface to AK130, AKM ’s TCM( ping-pong ) transceiver for PBX/KTS
system.
The PCM data format is A-law or u-law which can be selected by the register. The AK130 B1 mode interfaces the data
to B1 channel which is one of two B channels which AK130 provides, and the AK130 B2 mode interfaces to B2 chann el.
2-2-3-a Signals
- Frame Sync signal (FS)
___
Please feed the FS signal which is generated by AK130.( F0o , pin#3 )
- Bit Clock (BCLK)
BCLK defines the PCM data rate. Please use 2.048MHz clock which is generated by AK130 .( E2o,pin#5 )
- PCM data output (DX)
DX is an output signal of 128Kbps linear PCM data. Please connect to the PCM data input pin of AK130.( DSTi,pin#11 )
- PCM data input (DR)
DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the
D/A
block. Please connect to the PCM data output pin of AK130.( DSTo,pin#6 )
MS0190-E-05
2005/12
12
ASAHI KASEI
[AK2307/LV]
AK130 B1 Mode
244ns
125us(8kHz)
FS
BCLK
16CLK
8CLK
MSB First
Hi-Z
DX
DR
*
*
*
7
*
*
*
7
6
2
MSB First
6
1
Hi-Z
0
1
0
*
*
*
*
Note)*:Don't care
AK130 B2 Mode
244ns
125us(8kHz)
FS
BCLK
24CLK
8CLK
MSB First
Hi-Z
DX
DR
*
*
*
7
*
*
*
7
6
MSB First
6
2
1
1
Hi-Z
0
0
*
*
*
*
Note)*:Don't care
MS0190-E-05
2005/12
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ASAHI KASEI
3. Path and Gain Controls
[AK2307/LV]
Voice path, gain control of both RX and TX side, and the tone control are controlled from the CPU registers.
3-1. Path control switches;
AK2307/LV has 10 analog switches to control the RX and TX analog path. These switches are controlled
from
following 2 registers, Path control 1/2.
Path Control 1
Register Type : Read Write[Address:0000 D7-D0:(SW8-SW1)]
ADD
D7
D6
D5
D4
D3
D2
0
SW8
SW7
SW6
SW5
SW4
SW3
Default
0
0
0
0
0
0
D1
SW2
0
D0
SW1
0
Path Control 2
Register Type : Read Write[Address:0001
D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)]
ADD
D7
D6
D5
D4
D3
D2
D1
D0
1
RX
RX
Side
PCM_1 PCM_0
u-law
SW10
SW9
_Apad
_Pad
Tone
A-law
Default
0
1
0
0
0
0
0
0
Table3-a Switch function
SW Name
SW10
SW9
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
Function
External voice input enable for Speaker
RX Tone output enable for Speaker
RX Voice path enable for Speaker
RX Tone output enable for Headset
RX Voice path enable for Headset
RX Tone output enable for Handset
RX Voice path enable for Handset
TX Tone output enable
TX MIC path enable
TX Handset path enable
MS0190-E-05
Polarity
1: External input path 0: Internal Voice path
1: Tone output ON 0: Tone output OFF
1: Voice path ON 0: Voice path OFF
1: Tone output ON 0: Tone output OFF
1: Voice path ON 0: Voice path OFF
1: Tone output ON 0: Tone output OFF
1: Voice path ON 0: Voice path OFF
1: Tone output ON 0: Tone output OFF
1: MIC input ON
0: MIC input OFF
1: Handset path ON 0: Handset path OFF
2005/12
14
ASAHI KASEI
[AK2307/LV]
3-2 Voice path gain Controls
AK2307/LV provides the RX and TX voice gain control functions both in analog domain and in digital domain. These
gain
can be controlled from following five registers.
3-2-1. RX voice path gain controls
RX side voice path has three gain control blocks and two gain Pads. These gain stages are controlled
through following four registers, Path Control 2, RX digital Volume control, RX handset control, RX Headset
control and RX speaker control.
Path Control 2
Register Type : Read Write[Address:0001
D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)]
ADD
D7
D6
D5
D4
D3
D2
D1
D0
1
RX
RX
Side
PCM_1 PCM_0
u-law
SW10
SW9
_Apad
_Pad
Tone
A-law
Default
0
1
0
0
0
0
0
0
RX_Apad ; Analog +3dB gain pad at three RX voice output amps. This gain for to get the extra
gain in the RX level diagram. This means, for example, the analog output will be equivalent to
one correspond to –7dBm0 digital code when this gain is enabled. However, please notice
the maximum analog output can not exceed the one which is defined in analog characteristics
specification. The three gain stages at each output can not be changed individually.
Name
Porarity
Comment
RX_Apad
0
0dB
1
+3dB
default
RX_Pad; A digital –9dB gain pad at D/A digital domain. This gain pad is for a gain adjustment between
the in-system call and the external call.
Name
Porarity
Comment
RX_Pad
0
0dB
1
-9dB
default
MS0190-E-05
2005/12
15
ASAHI KASEI
[AK2307/LV]
RX Digital Volume Control
Register Type : Read Write[Address:0011
D7-D0(VTX3-VTX0, VSD_3-VSD_0)]
ADD
D7
D6
D5
D4
D3
D2
D1
D0
3
VRX3
VRX2
VRX1
VRX0
VSD_3 VSD_2 VSD_1 VSD_0
Default
0
1
1
1
1
1
1
1
VRX[3-0]; RX side digital volume from +6dB to –21dB by 3dB step.
when VRX3=1
Gain[dB]= 3 x VRX[2-0]
(VRX[2-0]=1 or 2)
VRX3=0
Gain[dB]= - 3×VRX[2-0]
VRX3
VRX2
VRX1
VRX0
RX digital Attenuator
Comment
0
0
0
0
0dB
Ref level=0dBm0
0
0
0
1
-3dB
0
0
1
0
-6dB
0
0
1
1
-9dB
0
1
0
0
-12dB
0
1
0
1
-15dB
0
1
1
0
-18dB
0
1
1
1
-21dB
1
0
0
0
NA
1
0
0
1
+3dB
1
0
1
0
+6dB
1
0
1
1
NA
1
1
0
0
NA
1
1
0
1
NA
1
1
1
0
NA
1
1
1
1
NA
default
NA ; Not applicable
MS0190-E-05
2005/12
16
ASAHI KASEI
[AK2307/LV]
RX Handset Volume Control ( Vol 2 )
Register Type : Read Write [Address:0111 D4-D0(V2_4-V2_0)]
ADD
D7
D6
D5
D4
D3
D2
7
V2_4
V2_3
V2_2
default
0
0
0
1
1
1
D1
V2_1
1
D0
V2_0
1
V2_[4-0]; Analog volume for the RX side Handset output. The gain is variable from 0dB to –23dB by 1 dB step.
Gain[ dB ] = -V2[dB] (when 0 <// V2<// 23)
V2_4
V2_3
V2_2
V2_1
V2_0
VOL2
Comment
ref level=0dBm0
0
0
0
0
0
0dB
0
0
0
0
1
-1dB
0
0
0
1
0
-2dB
0
0
0
1
1
-3dB
0
0
1
0
0
-4dB
0
0
1
0
1
-5dB
0
0
1
1
0
-6dB
0
0
1
1
1
-7dB
0
1
0
0
0
-8dB
0
1
0
0
1
-9dB
0
1
0
1
0
-10dB
0
1
0
1
1
-11dB
0
1
1
0
0
-12dB
0
1
1
0
1
-13dB
0
1
1
1
0
-14dB
0
1
1
1
1
-15dB
1
0
0
0
0
-16dB
1
0
0
0
1
-17dB
1
0
0
1
0
18dB
1
0
0
1
1
-19dB
1
0
1
0
0
-20dB
1
0
1
0
1
-21dB
1
0
1
1
0
-22dB
1
0
1
1
1
-23dB
1
1
X
X
X
NA
MS0190-E-05
default
NA ; Not applicable
2005/12
17
ASAHI KASEI
[AK2307/LV]
RX Headset Volume Control ( Vol 3 )
Register Type : Read Write [Address:1000 D4-D0(V3_4-V2_0)]
ADD
D7
D6
D5
D4
D3
D2
8
V3_4
V3_3
V3_2
default
0
0
0
1
1
1
D1
V3_1
1
D0
V3_0
1
V3_[4-0]; Analog volume for the RX side Headset output. The gain is variable from 0dB to –23dB by 1 dB step.
Gain[ dB ] = -V3[dB] (when 0 <// V2<// 23)
V3_4
V3_3
V3_2
V3_1
V3_0
VOL3
Comment
ref level=0dBm0
0
0
0
0
0
0dB
0
0
0
0
1
-1dB
0
0
0
1
0
-2dB
0
0
0
1
1
-3dB
0
0
1
0
0
-4dB
0
0
1
0
1
-5dB
0
0
1
1
0
-6dB
0
0
1
1
1
-7dB
0
1
0
0
0
-8dB
0
1
0
0
1
-9dB
0
1
0
1
0
-10dB
0
1
0
1
1
-11dB
0
1
1
0
0
-12dB
0
1
1
0
1
-13dB
0
1
1
1
0
-14dB
0
1
1
1
1
-15dB
1
0
0
0
0
-16dB
1
0
0
0
1
-17dB
1
0
0
1
0
18dB
1
0
0
1
1
-19dB
1
0
1
0
0
-20dB
1
0
1
0
1
-21dB
1
0
1
1
0
-22dB
1
0
1
1
1
-23dB
1
1
X
X
X
NA
default
NA ; Not applicable
MS0190-E-05
2005/12
18
ASAHI KASEI
[AK2307/LV]
RX Speaker Volume Control ( Vol 5 )
Register Type : Read Write [Address:1001 D4-D0(V5_4-V5_0)]
ADD
D7
D6
D5
D4
D3
D2
9
V5_3
V5_2
default
0
0
0
0
1
1
D1
V5_1
1
D0
V5_0
1
V5_[4-0]; Analog volume for the RX side Speaker output. The gain is variable from 0dB to –30dB by 2 dB step.
Gain[ dB ] = -2 x V5[dB] (when 0 <// V2<// 15)
V5_3
V5_2
V5_1
V5_0
VOL5
Comment
ref level=0dBm0
0
0
0
0
0dB
0
0
0
1
-2dB
0
0
1
0
-4dB
0
0
1
1
-6dB
0
1
0
0
-8dB
0
1
0
1
-10dB
0
1
1
0
-12dB
0
1
1
1
-14dB
1
0
0
0
-16dB
1
0
0
1
-18dB
1
0
1
0
-20dB
1
0
1
1
-22dB
1
1
0
0
-24dB
1
1
0
1
-26dB
1
1
1
0
-28dB
1
1
1
1
-30dB
MS0190-E-05
default
2005/12
19
ASAHI KASEI
[AK2307/LV]
3-2-2. TX voice path gain controls
TX side voice path has two gain control blocks. One is a analog volume and the other is a digital attenuator after D/A
converter. These voice path gains are controlled through the following regi ster.
TX Voice Path Gain Control (TX digital Attenuator, VOL 1)
Register Type : Read Write[Address:0010
D6-D0: (VTX2-VTX0, V1_3-V1_0)]
ADD
D7
D6
D5
D4
D3
D2
D1
2
VTX2
VTX1
VTX0
V1_3
V1_2
V1_1
default
0
1
1
1
0
0
0
D0
V1_0
0
VTX[2-0]; The digital attenuator for TX side voice path. The gain variation is from 0dB to –21dB by 3dB step.
Gain[dB]= - 3 x VTX( 3dB step )
VTX2
VTX1
VTX0
TX voice path digital Attenuator
Comment
0
0
0
0dB
ref level=0dBm0
0
0
1
-3dB
0
1
0
-6dB
0
1
1
-9dB
1
0
0
-12dB
1
0
1
-15dB
1
1
0
-18dB
1
1
1
-21dB
default
V1_[3-0]; An analog volume for TX side voice path. The variable range is from –8dB to +7dB by 1 dB.
Gain[dB] ; -8 + V1 ( 1dB step )
V1_3
V1_2
V1_1
V1_0
VOL1 TX voice path analog volume
Comment
0
0
0
0
-8dB
default
0
0
0
1
-7dB
0
0
1
0
-6dB
0
0
1
1
-5dB
0
1
0
0
-4dB
0
1
0
1
-3dB
0
1
1
0
-2dB
0
1
1
1
-1dB
1
0
0
0
0dB
1
0
0
1
+1dB
1
0
1
0
+2dB
1
0
1
1
+3dB
1
1
0
0
+4dB
1
1
0
1
+5dB
1
1
1
0
+6dB
1
1
1
1
+7dB
MS0190-E-05
ref level=0dBm0
2005/12
20
ASAHI KASEI
[AK2307/LV]
3-2-3. Side Tone path gain controls
AK2307/LV provides the side tone pass from TX to RX in digital domain. The activation of this
pass is set through Path Control 1 register( address=0) and the side tone attenuation is controled
through “RX Digital volume control” register( address=2).
Path Control 2
Register Type : Read Write[Address:0001
D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)]
ADD
D7
D6
D5
D4
D3
D2
D1
D0
1
RX
RX
Side
PCM_1 PCM_0
u-law
SW10
SW9
_Apad
_Pad
Tone
A-law
Default
0
1
0
0
0
0
Side Tone; A pass enable of the side tone from TX to RX.
Name
Porarity
Side
Tone
0
OFF
1
ON
0
0
Comment
default
Side Tone digital attenuator gain
Register Type : Read Write[Address;0011 D7-D0:(VTX3-VTX0, VSD_3-VSD_0)]
ADD
D7
D6
D5
D4
D3
D2
D1
D0
3
VRX3
VRX2
VRX1
VRX0
VSD_3 VSD_2 VSD_1 VSD_0
default
0
1
1
1
1
1
1
1
VSD_[3-0]; Side tone digital Attenuator. The gain variation range is from –12dB to –57dB.
Gain[dB]= -12 –3×VSD
VSD_3
VSD_2
VSD_1
VSD_0
Side Tone digital Attenuator gain
0
0
0
0
-12dB
0
0
0
1
-15dB
0
0
1
0
-18dB
0
0
1
1
-21dB
0
1
0
0
-24dB
0
1
0
1
-27dB
0
1
1
0
-30dB
0
1
1
1
-33dB
1
0
0
0
-36dB
1
0
0
1
-39dB
1
0
1
0
-42dB
1
0
1
1
-45dB
1
1
0
0
-48dB
1
1
0
1
-51dB
1
1
1
0
-54dB
1
1
1
1
-57dB
MS0190-E-05
Comment
default
2005/12
21
ASAHI KASEI
4. Tone generator
[AK2307/LV]
AK2307/LV has two tone generators to generate the service tone, DTMF tone and melody tone. Each generator can
select the 42 tone frequencies individ ually, and they are added each other before output from RX receiver amp or TX
A/D path.
After the adding stage there is a gain stage to attenuate the tone level from 0dB to –45dB by 3dB step. For the DTMF
low
frequency tone, there is another attenuator to attenuate by –2.5dB which can be set from the register.
The signal format is 64 stepwise pseudo sine wave. When the tone frequency is changed, the frequency is changed at
the 0 cross point of the tone to prevent the switching noise.
4-1. Tone frequency select
The 43 tone frequencies for the generator -H and the generator-L can be selected individually from
the different registers, ”Tone generator H-frequency select” and “Tone generator L-frequency select”.
There is two kind of parameters to select the tone frequency. One is to select the fundamental frequency and
another is to select the dividing ratio of the fundamental frequency to get the final tone frequency. For example,
when 1600Hz is selected as a fundamental frequency and the number 1/4 is selec ted as a dividing factor, then
the final tone frequency shall be 400Hz.
Tone generator H-frequency select
Register Type : Read Write[Address=0101:
ADD
5
default
D7
0
D6
0
D5
DIVH_1
0
Tone generator L-frequency select
Register Type : Read Write[Address=0110
ADD
6
default
D7
0
D6
LT_ATT
0
D5
DIVL_1
0
D5-D0:(DIVH_1-DIVH_0, TH_3-TH_0)]
D4
DIVH_0
0
D3
TH_3
0
D2
TH_2
0
D1
TH_1
0
D0
TH_0
0
D6-D0: (LT_ATT, DIVL_1-DIVL_0, TL_3-TL_0)]
D4
DIVL_0
0
D3
TL_3
0
D2
TL_2
0
D1
TL_1
0
D0
TL_0
0
TH_[3-0] / TL_[3-0]; The select bits of the fundamental frequency for the tone generator -H and the tone generator-L,
respectively.
Fundamental frequencies
Tx_3
Tx_2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Tx ;TH or TL
Tx_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Tx_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Fundamental frequency( Hz )
mute
1600.00
1471.26
1391.30
1333.33
1207.55
1174.31
1049.18
1000.00
941.18
888.89
853.33
785.28
771.08
727.27
571.43
MS0190-E-05
2005/12
22
ASAHI KASEI
[AK2307/LV]
DIVH_[1-0] / DIVL_[1-0]; The dividing factor of the fundamental frequency to get the final tone frequency.
Tone frequency = fundamental frequency x dividing factor.
Dividing factor
DIVx_1
0
0
1
1
DIVx_0
0
1
0
1
dividing factor
1
1/2
1/4
NA
DIVx ; DIVH or DIVL
Tone frequency list;
Fundamental Freq.
(TH,TL3-0)
Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Fundamental Freq(Hz)
Mute
1600.00
1471.26
1391.30
1333.33
1207.55
1174.31
1049.18
1000.00
941.18
888.89
853.33
785.28
771.08
727.27
571.43
Dividing factor(DIVH/L1-0)
1(Hz)
1600.00
1471.26
1391.30
1333.33
1207.55
1174.31
1049.18
1000.00
941.18
888.98
853.33
785.28
771.08
727.27
571.43
1/2(Hz)
800.00
735.63
695.65
666.67
603.78
587.16
524.59
500.00
470.59
444.49
426.67
392.64
385.54
363.64
285.72
MS0190-E-05
1/4(Hz)
400.00
367.82
347.83
333.33
301.89
293.58
262.30
250.00
235.30
222.25
213.33
196.32
192.77
181.82
142.86
2005/12
23
ASAHI KASEI
functional category of the tone
Category Nominal freq.
Fundamental
(Hz)
Freq(Hz)
Melody
1397
1391.3
1318
1333.33
1175
1174.31
1046
1049.18
988
1000
880
882.76
784
785.28
698
1391.3
659
1333.33
587
1174.31
523
1049.18
494
1000
440
882.76
392
785.28
DTMF
697
1391.3
770
771.08
852
853.33
941
941.18
1209
1207.55
1336
1333.33
1477
1471.26
Misc.
726
727.27
4k/n
4k/16=250
1000
4k/12=333.33
1333.33
4k/11=363.64
727.27
4k/10=400
1600
4k/9 =444.44
888.89
4k/8 =500
1000
4k/7 =571.43
571.43
4k/6 =666.67
1333.33
4k/5 =800
1600
4k/4 =1000
1000
Misc.
350
1391.3
440
882.76
600
1174.31
680
1391.3
1600
1600
[AK2307/LV]
Dividing
Factor
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
4
4
2
4
2
2
1
2
2
1
4
2
2
2
1
MS0190-E-05
Tx_[3-0]
Code
0011
0100
0110
0111
1000
1010
1100
0011
0100
0110
0111
1000
1010
1100
0011
1101
1011
1001
0101
0100
0010
1110
1000
0100
1110
0001
1010
1000
1111
0100
0001
1000
0011
1010
0110
0011
0001
DIVx_[1-0]
Code
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
00
00
00
00
00
00
00
10
10
01
10
01
01
00
01
01
00
10
01
01
01
00
error
(Typ)
-0.4%
+1.1%
-0.1%
+0.3%
+1.2%
+0.3%
+0.2%
-0.3%
+1.2%
0.0%
+0.3%
+1.2%
+0.3%
+0.2%
-0.2%
+0.1%
+0.2%
±0.0%
-0.1%
-0.2%
-0.4%
+0.2%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
-0.6%
+0.3%
-2.1%
+2.3%
0.0%
Comment
Fa’’
Mi’’
Re’’
Do’’
Si’
la’
So’
Fa’
Mi’
Re’
Do’
Si
la
So
Low
Low
Low
Low
High
High
High
2005/12
24
ASAHI KASEI
[AK2307/LV]
4-2 Tone volume control
The volume control of the tone is done through “Tone Volume Control” register. The gain is changed after two tones a re
added, thus the signal level of two tone is always same. Only L -ATT bit in “Tone generator L-frequency select” register
can change the signal level between two tones by -2.5dB.
Tone generator L-frequency select
Register Type : Read Write[Address=0110
ADD
6
default
D7
0
D6
LT_ATT
0
D5
DIVL_1
0
D6-D0: (LT_ATT, DIVL_1-DIVL_0, TL_3-TL_0)]
D4
DIVL_0
0
D3
TL_3
0
D2
TL_2
0
LT_ATT; Attenuation bit for the low frequency tone generator.
LT_ATT
DTMF Low frequency(Tone generator L)
0
D1
TL_1
0
D0
TL_0
0
Comments
0dB
default
1
-2.5dB
*) Gain error of the LT_ATT is +/-1.0dB at the worst case. In this case, LT_ATT is irregular from the DTMF standard.
Tone Volume Control (vol 4)
Register Type : Read Write[Address=0100:
ADD
4
default
D7
0
D6
0
D5
0
D3-D0: (V4_3-V4_0)]
D4
0
D3
V4_3
1
D2
V4_2
1
D1
V4_1
1
D0
V4_0
1
V4_[3-0]; Tone volume control.( Volume4 ) The gain range is from 0dB to –45dB by 3dB step.
Gain[dB]= - 3×V4
V4_3
V4_2
V4_1
V4_0
VOL4 Tone volume control
Comment
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0dB
-3dB
-6dB
-9dB
-12dB
-15dB
-18dB
-21dB
-24dB
-27dB
-30dB
-33dB
-36dB
-39dB
-42dB
-45dB
default
MS0190-E-05
2005/12
25
ASAHI KASEI
5. Power on Reset
[AK2307/LV]
Power on Reset
AK2307/LV automatically generates the internal reset pulse which resets all the circuit that is necessary to start the
initialization after the power on re set. The CPU registers are set to the default value.
After the internal reset pulse is generated, CODEC starts the initialization procedure by being fed FS signal, and it takes
150ms(typ.), 330ms(max) to complete the initialization after the detection of power on.
Power up slope to enable the Power-on Reset
When the power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally.
When the time is longer than 50ms, Power On Reset may not be activated and no internal regist ers are initialized. In
this case all registers must be written through CPU interface.
NOTE) For the stable operation after power up, we recommend to write all register value through CPU interface in any
case after the power up.
Recommended start up procedure
The following start up procedure is recommended when AK2307/LV is going to power up.
Power up
Wait 200ms
- FS=”L”
- BCLK=”L”
During this stage, FS and BCLK must be tied to
“L” not to receive or transmit the data from/to the
external devices.
*In case of VDD rising time
=50ms(=5tau)
Write data to the internal
register through serial I/F
- Write data to the internal register
before CODEC starts working.
Supply FS and BCLK
- CODEC Initialization starts.
Wait 250ms (min:130ms)
- CODEC Initialization complete.
CODEC starts working
MS0190-E-05
2005/12
26
ASAHI KASEI
[AK2307/LV]
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed for VDD=+5.0V+/-5%(AK2307), VDD=+3.3V+/-0.3V(AK2307LV), Ta =
o
–10 ~ +85 C, FS=8kHz.
DC Characteristics
Parameter
Power Consumption
BCLK=2048kHz
Output High Voltage
(CMOS level)
Output Low Voltage
(CMOS level)
Input High Voltage1
(CMOS level)
Input Low Voltage1
(CMOS level)
Input Leakage Current
Input Capacitance
Input Leakage Current
Output Leakage Current
Symbol
Conditions
Idd
* Note1)
VOH
IOH=-1.6mA
VOL
IOL=1.0mA
Min
Typ
Max
-
20
-
VDD-0.5
0.7VDD
VIL1
Ii
Ci
Ill
Ilt
-10
-10
-10
Tri-state mode
mA
V
0.4
VIH1
Units
V
V
0.3VDD
V
+10
5
10
10
uA
pF
uA
uA
*Note1) All the output pin are unloaded. [email protected] sine wave from HANDT2/3, A to A loopbacked.
All the volume gain are set to 0dB and two of the tone generator are off. The handset mic and receiver paths are only
active.
MS0190-E-05
2005/12
27
ASAHI KASEI
[AK2307/LV]
◆ AC Characteristics
Note) Otherwise specified, Ta=-10℃~+70 degree, VDD=5.0V +/- 5%(AK2307),VDD=3.3V +/0.3V(AK2307LV), VSS=0V, FS=8kHz are assumed. All the timing parameters are measured at
VOH=VDD-0.5, VOL=0.4V.
PCM Interface
u/A-law mode(Long Frame ,Short Frame) & Linear PCM mode
Items
FS frequency
BCLK frequency
Note1)
Clock width
Falling/rising time
Output delay
Pin Name
FS
BCLK
Parm.
FFS
FBCLK
Conditions
-
MIN
-
BCLK
FS,BCLK,DR
DX
DX
WP
TD
TDX
TDX2
Cl=50pF
Cl=50pF
FS
TFSS
DR
TDRS
Setup time
Hold time
FS Low level width
MAX
-
Unit
kHz
kHz
160
10
TYP
8
64×N
128K X N
-
40
60
-
ns
ns
ns
ns
-
70
-
-
ns
-
40
-
-
ns
FS
TFSH
-
40
-
-
ns
DR
TDRH
-
40
-
-
ns
FS
TWLFS
-
1
-
-
BCLK
Note1)Short Frame:64 x N kHz (N=1 to 32), Long Frame:64 x N kHz(N=1 to 32), Linear mode:128 x N kHz(N=1to 16)
AK130 B1ch/B2ch mode
Items
FS frequency
Clock frequency
Pulse width
Falling/Rising time
Output delay
Setup time
Pin Name
FS
BCLK
BCLK
FS,BCLK,DR
DX
DX
FS
Parm.
FFS
FBCLK
WP
TD
TDX
TDX2
TFSS
Conditions
CL=50pF
CL=50pF
-
MIN
-
TYP
8
MAX
-
-
2.048
244
-
10
70
-
40
60
60
-
Unit
kHz
kHz
ns
ns
ns
ns
ns
DR
TDRS
-
40
-
-
ns
FS
TFSH
-
40
-
-
ns
DR
TDRH
-
40
-
-
ns
Hold time
u/A-law PCM mode(Short Frame) & Linear PCM mode
FFS
TFSH
TFSS
TFSH
TFSS
FS
WP
WP
BCLK
FBCLK
TDX
TDX
TDX2
DX
TDRS
TDRH
DR
MS0190-E-05
2005/12
28
ASAHI KASEI
[AK2307/LV]
u/A law PCM mode(Long Frame)
FFS
FWLFS
TFSH
TFSS
TFSH
FS
BCLK
TDX
TDX
TDX
TDX2
DX
TDRS
TDRH
DR
AK130 B1ch/B2ch mode
FFS
TFSH
TFSS
TFSH
TFSS
FS
WP
WP
BCLK
FBCLK
TDX
TDX
TDX2
DX
TDRS
TDRH
DR
MS0190-E-05
2005/12
29
ASAHI KASEI
[AK2307/LV]
CPU I/F
Items
SCLK frequency
SCLK pulse width
Falling/rising time
Output delay
Pin Name
SCLK
SCLK
CSN,SCLK
DATA
DATA
Setup time
Hold time
Parm.
FSCLK
WPS
TD
TDA
TDA2
Conditions
CL=15pF
CL=15pF
MIN
40
-
TYP
-
MAX
4
100
60
60
Unit
MHz
ns
ns
ns
Ns
CSN
TCSS
-
40
-
-
ns
DATA
TDAS
-
40
-
-
ns
CSN
TCSH
-
80
-
-
ns
DATA
TDAH
-
40
-
-
ns
Data write cycle
TCS
S
TCSH
TCS
S
TCSH
CSN
WPS
WPS
SCLK
FSCLK
TDA
S
TDAH
DATA
Data read cycle
TCSH
TCS
S
CSN
WPS
TDA2
WPS
SCLK
FSCLK
TDA
S
TD
A
TDAH
TD
A
TD
A
DATA
Instruction code, Address write
Data read
MS0190-E-05
2005/12
30
ASAHI KASEI
[AK2307/LV]
CODEC
Absolute Gain (AK2307:VDD=5.0V +/-5%, AK2307LV:VDD=3.3V +/-0.3V )
Parameter
Conditions
Min
Analog Input Level
HANDT4 to DX
AK2307LV
MIC3 to DX
AK2307
1020Hz 0dBm0 input
Absolute Transmit Gain
u/A-law
-1.5
Analog Output Level
DR to DAOUT
AK2307LV
1020Hz 0dBm0 input
AK2307
Absolute Receive Gain
u/A-law
-1.5
Maximum Overload Level DR to DAOUT
AK2307LV
+3.14dBm0 input
AK2307
Gain Tracking
Parameter
Transmit Gain Tracking Error
( A to D )
Conditions
Reference Level: -51dBm0 ~-46dBm0
-10dBm0
-46dBm0 ~-36dBm0
1020Hz Tone
-36dBm0 ~ 0dBm0
Receive Gain Tracking Error
Reference Level: -51dBm0 ~-46dBm0
( D to A )
-10dBm0
-46dBm0 ~-36dBm0
1020Hz Tone
-36dBm0 ~ 0dBm0
The characteristics from MIC3 to DR path is guaranteed by the design.
Frequency Response
Parameter
Transmit Frequency Response
( A to D )
HANDT4 to DX
MIC3 to DX
Receive Frequency Response
( D to A )
DR to DAOUT
Conditions
Relative to:
0.06kHz
[email protected]
0.2kHz
0.3 ~3.0kHz
3.4kHz
3.78kHz
Relative to:
0.3K ~3.0kHz
[email protected]
3.4kHz
3.78kHz
Max
Units
Vrms
+1.5
dB
Vrms
+1.5
dB
Vrms
Units
Min
-0.9
-0.6
-0.4
-0.9
-0.6
-0.4
Typ
-
Max
0.9
0.6
0.4
0.9
0.6
0.4
Min
24
0
-0.3
0
6.5
-0.3
0
6.5
Typ
-
Max
2.5
0.3
0.8
0.3
0.8
-
Typ
-
Max
-
Distortion
Parameter
Conditions
Min
Transmit Signal to Distortion
1020Hz Tone
-36dBm0 ~-41dBm0
24
( D to A )
-26dBm0 ~-36dBm0
29
HANDT4 to DX
0dBm0 ~-26dBm0
35
MIC3 to DX
Receive Signal to Distortion
1020Hz Tone
-36dBm0 ~-41dBm0
24
( A to D )
-26dBm0 ~-36dBm0
29
DR to DAOUT
0dBm0 ~-26dBm0
35
Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law
Note) The characteristics from MIC3 to DR path is guaranteed by the design.
MS0190-E-05
Typ
0.101
0.162
0.482
0.771
0.694
1.107
-
-
dB
dB
Units
dB
dB
Units
dB
dB
2005/12
31
ASAHI KASEI
[AK2307/LV]
Noise
Parameter
Conditions
Min
Typ
Max
Units
1)
Idle Channel Noise
u-law, C-message
8
16 dBrnC0
A!D
HANDT2,3 to DX
A-law, Psophometric
-82
-74 dBm0p
MIC2 to DX
2)
Idle Channel Noise
u-law, C-message
2
9
dBrnC0
A-law, Psophometric
-88
-81 dBm0p
D!A
DR to DAOUT
2)
Idle Channel Noise
u-law, C-message
3
16 dBrnC0
A-law, Psophometric
-87
-74 dBm0p
D!A
DR to HANDR1
Note 1) Analog Input = Analog Ground. The gain of Handset MIC and MIC input is assumed as +25dB.
SCLK is not supplied. The specification of MIC to DX pass is guaranteed by the design.
Note 2) Digital Input(DR) = +0 Code
Interchannel Crosstalk
Parameter
Transmit to Receive
Conditions
[email protected], Idle PCM [email protected]
HANDT4 to DAOUT
MIC3 to DAOUT
Receive to Transmit
0dBm0 [email protected], HANDT4 = 0 Vrms
RX voice path Volume
Parameter
Step margin
Volume
VOL2
VOL3
VOL5
0 to –22dB
VOL5
-22 to
–30dB
Conditions
1020Hz 0dBm0 input at DR
Relative to: 0dB
1020Hz 0dBm0 input at DR
Relative to: 0dB
1020Hz 0dBm0 input at DR
Relative to: 0dB
1020Hz 0dBm0 input at DR
Relative to: 0dB
Min
-
Typ
-70
Max
-
-
-70
-
Min
typ
-1.0
0
+1.0*) dB
-1.0
0
+1.0*) dB
-1.0
0
+1.0
-1.5
0
+1.5*) dB
max
Units
dB
dB
Unit
dB
*)Monotonus increase/decrease is guaranteed
TX voice path Volume
Parameter
Step margin
Volume
VOL1
Conditions
1020Hz 0dBm0 input at DR
Relative to: 0dB
Min
typ
-1.0
0
max
Unit
+1.0*) dB
*)Monotonus increase/decrease is guaranteed
Tone Volume
Parameter
Step margin
Volume
VOL4
Gain error
L-ATT
Conditions
Output; HANDR1
1600Hz tone , Ref level;VOL4=0dB
L-ATT=-2.5dB
Min
typ
-1.0
0
+1.0 dB
-27 to –45dB -2.0
0
+2.0*) dB
-1.0
0
+1.0 dB
0 to –24dB
max
Unit
*)Monotonus increase/decrease is guaranteed
MS0190-E-05
2005/12
32
ASAHI KASEI
[AK2307/LV]
OP-AMPs
Note) Otherwise specified, the VOL2 ,3 and 5 is 0dB gain.
RX Amp for Handset receiver
Conditions
MIN
TYP
MAX
Unit
RAIN
AK2307LV (150ohm load)
2.0
Vp-p
(75ohm load)
1.5
→HANDR1
3.2
SINAD<40d AK2307 (150ohm load)
B, 1020Hz
(75ohm load)
2.4
Note) when HANDR1 and HEADO are used as a differential output for 150 ohm receiver, the load
impedance for the each output is calculated as 75 ohm.
Maximum output
level
RX Amp for Headset receiver
Conditions
MIN
TYP
MAX
Unit
AK2307LV (150ohm load)
2.0
Vp-p
(75ohm load)
1.5
AK2307 (150ohm load)
3.2
(75ohm load)
2.4
Note) when HANDR1 and HEADO are used as a differential output for 150 ohm receiver, the load
impedance for the each output is calculated as 75 ohm.
RX Amp for Speaker output
Conditions
MIN
TYP
MAX
Unit
Maximum output RAIN, EXRIN
AK2307LV
2.0
Vp-p
level
→SPO*)
SINAD<40dB,
AK2307
3.2
1020Hz
*Note)A Characteristics from EXRIN input is guaranteed by the design.
Maximum output
level
RAIN
→HEADO
SINAD<40d
B, 1020Hz
TX Amp for Handset MIC input
Maximum
output level
Maximum gain
HANDT1
SINAD<40
dB
Mic
gain=25dB
at 1020Hz
Conditions
AK2307LV
MIN
0.411
TYP
-
MAX
-
AK2307
0.660
-
-
0
-
25
dB
MIN
0.411
TYP
-
MAX
-
Unit
Vp-p
0.660
-
-
0
-
25
Inverting amplify
Unit
Vp-p
TX Amp for MIC input
Maximum
output level
Maximum gain
Conditions
MIC1
AK2307LV
SINAD<40
dB
AK2307
Gain=25dB
at 1020Hz Inverting amplify
MS0190-E-05
dB
2005/12
33
ASAHI KASEI
[AK2307/LV]
Tone signal
Output level
Output level
to RX path
Output level
to TX path
Conditions
HANDR
AK2307LV
HEADO
SPO
AK2307
1600Hz VOL4=0dB
DX
AK2307/LV
1049Hz VOL4=0dB
Input Impedance
Pin
EXRIN、RAIN
HANDT4、MIC3
MIN
70K
TYP
100K
MAX
150K
7K
10K
15K
MIN
420
TYP
500
MAX
595
672
800
952
0
Unit
mVrms
dBm0
Unit
ohm
MS0190-E-05
2005/12
34
ASAHI KASEI
[AK2307/LV]
APPLICATION CIRCUIT EXAMPLE
l
Handset Input Stage
HANDT4
0.1uF
100pF
1.0uF
20K
1.2K
1.0uF
1.2K
HANDT1
HANDT2
HANDT3
100pF
20K
TAGND
1.0uF
l
MIC amp Input Stage
MIC3
0.1uF
1.0uF
100pF
20K
1.2K
MIC1
MIC2
VSS
TAGND
l
Handset Receiver output Stage
DAOUT
Single End Output
HANDR
RAIN
Differential Output
0.1uF
0.001uF
10uF
HANDR
VSS
-1
HEADO
0.001uF
VSS
VSS
MS0190-E-05
2005/12
35
ASAHI KASEI
[AK2307/LV]
Speaker Amp Output Stage
100pF
100K
SPO
10K
0.1uF
Internal
RAGND
l
Analog Ground, PLLCAP
VREF
1.0uF以上
TAGND
1.0uF以上
RAGND
1.0uF以上
PLLCAP
1.0uF以上
l
Power Supplies
VDD
10uF
0.1uF
VSS
AVDD
10uF
0.1uF
AVSS
MS0190-E-05
2005/12
36
ASAHI KASEI
[AK2307/LV]
PACKAGE
28pin VSOP
Marking
(1) Pin#1 indicator
(2) Date code:
(3) Marketing code:
(4) AKM Logo
XXXXX(5digit)
AK2307LV/AK2307
AK2307LV
AKM
AK2307LV
XXXXX
XXXXX:
Date Code and Lot#
AK2307
AKM
AK2307
XXXXX
XXXXX:
MS0190-E-05
Date Code and Lot#
2005/12
37
ASAHI KASEI
[AK2307/LV]
Package dimensions
28pin VSOP (Unit: mm)
*9.8±0.2
28
15
5.6
7.6±0.2
A
14
1
0.15+0.10
-0.05
0.65
0.22+0.10
-0.05
0.12
M
0.10±0.05
1.15± 0.10
Seating Plane
0.5±0.2
Detail A
0.08
NOTE: Dimension "*" does not include mold flash.
MS0190-E-05
0-10°
2005/12
38
ASAHI KASEI
[AK2307/LV]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to res ult in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0190-E-05
2005/12
39