AKM AK2301A

ASAHI KASEI
AK2301A
AK2301A
3.3V Single channel PCM CODEC LSI
FEATURE
GENERAL DESCRIPTION
The AK2301A is a single channel PCM CODEC
for speech processing 8kHz sampling PCM data by
DSP. The AK2301A interfaces with 14bit linear
data (16bit format).
- Single PCM CODEC and filtering
- Mute function
- PCM interface; 14bits linear data
systems
(16bit format, serial interface)
Frame / Short Frame are selected
automatically
- PCM data rate
256kHz/512kHz
- Op-Amp for the external gain adjustment
- Dual universal op-amps
- Single power supply voltage
+3.3±0.3V
- Low power consumption
- Small package
- Long
It includes Band limiting filter, A/D and D/A
converter, and universal op-amps for construction
of the output filter. All functions are provided in
small 24pin VSOP package and it is good for
reducing the mounting space.
PACKAGE
- 24pin VSOP
・Pin to pin 7.9mm x 7.6mm
・Pin pitch 0.65mm
BLOCK DIAGRAM
GST
VFTN
VFTP
AAF
A/D
AMPT
PCM I/F
VR
VFR
SMF
DX
DR
FS
BCLK
D/A
AMPR
CODEC Core
GSR
Internal
Main Clock
TAGND
VREF
PLL
PLLC
MUTEN
RSTN
BGREF
VDD
AMP1
VSS
TEST1
TEST2
TEST3
AMP2
AK2301A
AMP1O
<MS0300-E-00>
AMP1I
1
AMP2O
AMP2I
2004/3
ASAHI KASEI
AK2301A
CONTENT
ITEMS
<MS0300-E-00>
PAGE
-
BLOCK DIAGRAM…………………………………… 1
-
PIN CONDITION……………………………………… 3
-
PIN FUNCTION……………………………………….. 4
-
ABSOLUTE MAXIMUM RATINGS………………… 5
-
RECOMMENDED OPERATING CONDITIONS…... 5
-
ELECTRICAL CHARACTERISTICS………………...5
-
PACKAGE INFORMATION…………………………. 10
-
PIN ASSIGNMENT…………………………………… 11
-
MARKING……………..………………………………. 11
-
CIRCUIT DESCRIPTION….……………………….
-
FUNCTIONAL DESCRIPTION……………………… 13
-
PCM CODEC………….…………………………. 13
-
PCM INTERFACE…………...…………………... 14
-
Long Frame / Short Frame…....……………... 14
-
MUTE……………………………….…………….. 16
-
RESET SEQUENCE……………………….……. 17
-
Universal op-amps……………………………. 18
-
APPLICATION CIRCUIT EXAMPLE ………………. 19
2
12
2004/3
ASAHI KASEI
AK2301A
PIN CONDITION
Pin#
AC load
(MAX.)
I/O
Pin type
VFTN
VFTP
I
I
Analog
Analog
GST
O
Analog
50pF
GSR
O
Analog
40pF
8
9
VFR
I
Analog
VR
O
Analog
6
19
5
3
2
4
23
22
18
VDD
VSS
FS
BCLK
DX
DR
MUTEN
RSTN
I
I
O
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
VREF
O
Analog
PLLC
O
Analog
TAGND
O
Analog
11
AMP2I
I
Analog
12
AMP1I
I
Analog
AMP1O
O
Analog
40pF
AMP2O
O
Analog
40pF
15
16
14
7
Name
DC load
(MIN.)
Output
status
(mute)
AC load
10kΩ (*1)
AC load
8kΩ (*1)
AC load
8KΩ (*1)
40pF
50pF
Analog
ground
Hi-Z
- External
capacitance
1.0µF or more
- External
capacitance
0.33µF±40%
(Includes
temperature
characteristic)
- External
capacitance
1.0µF or more
- 150uA load max
20
17
13
10
Remarks
AC load
8kΩ (*1)
AC load
8kΩ (*1)
-
-
-
-
-
-
-
-
-
- Tie to the VSS
- Tie to the VSS
- Tie to the VSS
*1) AC load is a load against AGND. This value includes a feedback resistance of input/output op -amp.
21
24
1
Test1
Test2
Test3
<MS0300-E-00>
I
I
I
CMOS
CMOS
CMOS
3
2004/3
ASAHI KASEI
AK2301A
PIN FUNCTION
Pin types
NIN:
Normal input
AIN:
Analog input
Type
Pin# Name
15 VFTN
AIN
16 VFTP
14 GST
AIN
AOUT
7
GSR
AOUT
8
9
6
VFR
VR
VDD
AIN
AOUT
PWR
19 VSS
5 FS
PWR
NIN
NIN
3
BCLK
2
DX
TOUT
4
DR
NIN
23 MUTEN
NIN
22 RSTN
NIN
18 VREF
AOUT
20 PLLC
AOUT
17 TAGND AOUT
11
12
13
10
21
24
1
TOUT: Try state output
AOUT: Analog output
PWR: Power / Ground
Function
Neagative analog input of the transmit OP amp.
Diffelential or single amplifire is composed with the VFTP and the external
registers. Transmit gain is defined by the ratio of the external registers.
Positive analog input of the transmit OP amp.
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTP.
Output of the receive OP amp.
Receive gain is defined by the ratio of the external registers.
The differential output can be composed with using the VR.
Negative analog input of the receive OP amp.
Analog output of the D/A convertor equivalent to the received PCM code.
Positive supply voltage
+3.3V supply
Ground (0V)
Frame sync input
This clock is input for the internal PLL which gerenates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK and do not stop
feeding.
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 256kHz or 512kHz and do not stop feeding.
Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the high
impedance except for the period in which PCM data is transmitted.
Serial input of PCM data
The PCM data is synchronized with BCLK.
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
Reset signal input pin
Reset operation starts by low input. This pin is used for the initialization at the
power up. Please use MUTEN pin together to avoid the popping sound output
until the LSI finish the initialaization after the power up.(Refer to P.13)
Analog ground output
External capacitance (1.0µF or more) should be connected between this pin and
VSS. Please do not connect external load to this pin.
PLL loop filter output
External capacitance (0.33µF±40%: Includes temperature characteristic) should
be connected between this pin and VSS.
Analog ground output for transmitte OP amp
150uA load max. External capacitance (1.0µF or more) should be connected
between this pin and VSS. This pin is used as an analog ground for transmit OP
amp (AMPT).
Negative input of the universal OP amp
AIN
AMP1I
AMP2I
AMP1O AOUT Output of the universal OP amp
AMP2O
TEST1 NIN Test pins (”H”=test mode)
Please tie to VSS
TEST2
TEAT3
<MS0300-E-00>
4
2004/3
ASAHI KASEI
AK2301A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Power supply voltage
Analog/Digital power supply
VDD
-0.3
Digital input voltage
VTD
-0.3
Analog input voltage
VTA
-0.3
Input current (except power supply pins)
IIN
-10
Storage temperature
Tstg
-55
Warnig: Exceeding absolute maximum ratings may causepermanent damage.
Normal operation is not guranteed at these extermes.
Max
Units
4.6
VDD+0.3
VDD+0.3
10
125
V
V
V
mA
℃
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Power supply voltage
VDD
3.0
Analog/Digital power supply
Ambient operating temperature
Ta
-40
Frame sync frequency *)
FS
-1.0%
Note) All voltages reference to ground: VSS = 0V
*) All the characteristics of the CODEC is definied by 8kHz FS.
Typ
3.3
Max
3.6
Units
V
8
85
+1.0%
℃
kHz
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed for VDD = +3.3V±0.3V, Ta = -40~+85℃, FS=8kHz, VSS=0V
DC Characteristics
Parameter
Power Consumption
BCLK=512kHz
Symbol
PDD1
Conditions
All output unloaded
*1)
Output high voltage
VOH
IOH=-1.6mA
Output low voltage
VOL
IOL=1.6mA
Input high voltage
VIH
Input low voltage
VIL
Input leakage current
ILL
Anarog ground output VRG
voltage
Output leakage current ILT
Min
Typ
10
Max
Unit
15
mA
0.8VDD
V
0.4
0.7VDD
V
-10
1.4
Tri-state mode
-10
V
1.5
0.3VDD
V
+10
µA
1.6
V
+10
µA
*1) [email protected] input, [email protected] Code input
<MS0300-E-00>
5
2004/3
ASAHI KASEI
AK2301A
PCM INTERFACE (Lomg Frame, Short Frame)
All timing parameters of the output pins are measured at VOH = 0.8VDD and VOL = 0.4V. Input pins
are measured at VIH = 0.7VDD and VIL = 0.3VDD.
AC Characteristics
Parameter
Symbol
Min
Typ
Max
FS Frequency
fPF
-1.0%
8
+1.0%
kHz
BCLK Frequency
fPB
-
32FS/
64FS
-
kHz
1.563
1.953
2.344
µs
0.781
0.977
1.172
µs
40
ns
BCLK Pulse Width (High/Low) (BCLK=32×FS=256kHz)
BCLK Pulse Width (High/Low) (BCLK=64×FS=512kHz)
Rising/Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1)
tWBH
tWBL
tWBH
tWBL
tRB
tFB
Unit Ref Fig
Hold Time: BCLK Low to FS High
tHBF
60
ns
Setup Time: FS High to BCLK Low
tSFB
60
ns
Setup Time: DR to BCLK Low
tSDB
60
ns
Hold Time: BCLK Low to DR
tHBD
60
ns
Delay Time: BCLK High to DX valid
Note1)
tDBD
60
ns
Delay Time: BCLK High to DX High-Z
Note1)
tDZC
60
ns
Fig1, 2
Long Frame
nd
Hold Time: 2 period of BCLK Low to FS Low
tHBFL
Delay Time: FS or BCLK High, whichever is later,to DX valid
注1)
tDZFL
FS Pulse Width Low
tWFSL
1
BCLK
Hold Time: BCLK Low to FS Low
tHBFS
60
ns
Setup Time: FS Low to BCLK Low
tSFBS
60
ns
60
ns
60
ns
Fig1
Short Frame
Fig2
Note1) Measured with 50pF load capacitance and 0.2mA drive.
<MS0300-E-00>
6
2004/3
ASAHI KASEI
AK2301A
Interface Timing
tFB
tRB tWBL
tWBH
1/fPB
BCLK
tSFB
FS
tHBF
tHBFL
tDZFL
tDBD
DX
MSB
2
3
4
tSDB
DR
MSB
2
3
tDZC
5
6
7
14
5
6
7
14
tHBD
4
FS
1/fPF
tWFSL
Fig1. Long Frame
tFB
tRB
tWBL
tWBH
1/fPB
BCLK
tSFB
tHBFS
FS
tHBF
DX
tSFBS
tDBD
MSB
tDBD
2
3
4
tSDB
DR
MSB
2
3
tDZC
5
6
7
14
5
6
7
14
tHBD
4
Fig2. Short Frame
<MS0300-E-00>
7
2004/3
ASAHI KASEI
AK2301A
CODEC
* The receive and transmit op-amp’s characteristics are measured at the 0dB gain.
The frequency specifications when FS deviation from 8kHz are as follows:
Used FS
× noted frequency specification = Effective frequency specification
8k[Hz]
Absolute Gain
Parameter
Conditions
Analog input level
VFTP,VFTN [email protected] input
→
Absolute transmit gain
DX
Maximum overload level
3.14dBm0
Analog output level
[email protected] input
DR
→
Absolute receive gain
VR
Maximum overload level
3.14dBm0
Min
-
-0.6
-
-
-0.6
-
Typ
0.531
-
0.762
0.531
-
0.762
Max
-
0.6
-
-
0.6
-
Unit
Vrms
dB
Vrms
Vrms
dB
Vrms
Frequency response
Parameter
Conditions
Transmit frequency response Relative to:
0.05kHz
[email protected]
(A→D)
0.06kHz
0.2kHz
VFTP,VFTN → DX
0.3~3.0kHz
3.4kHz
4.0kHz
Receive frequency response Relative to:
0~3.0kHz
[email protected]
(D→A)
3.4kHz
DR → VR
4.0kHz
Min
30
26
0
-0.15
0
14
-0.15
0
14
Typ
-
-
-
-
-
-
-
-
-
Max
-
-
1.8
0.15
0.8
-
0.15
0.8
-
Unit
Condtions
Min
Typ
Max
0dBm0
70
75
-
dB
0dBm0
70
75
-
dB
dB
dB
Distortion
Parameter
Transmit signal to Distortion
(A→D)
VFTP,VFTN → DX
Receive signal to Distortion
(D→A)
DR → VR
<MS0300-E-00>
Unit
1020Hz Tone
C-message
1020Hz Tone
C-message
8
2004/3
ASAHI KASEI
AK2301A
Noise
Parameter
Condtions
Idle channel noise A→D (*1)
C-message
VFTP,VFTN → DX
Idle channel noise D→A(*2)
C-message
DR → VR,GSR
PSRR
VDD=3.3V/±66mVop
Transmit path
f=0~10kHz
PSRR
VDD=3.3V/±66mVop
Receiver path
f=0~10kHz
(*1) Analog input is set to the analog ground level
(*2) Digital input is set to the +0 CODE
Unit
dBrnC0
Min
Typ
Max
-
8
13
-
5
10
-
55
-
-
55
-
Min
Typ
Max
-
-
-75
dB
-
-
-75
dB
Min
Typ
Max
Unit
10
-
-
-
-
50
kΩ
pF
-12
-
6
dB
Min
Typ
Max
Unit
PCM +0 code input
-
1.5
-
V
AC load
8
-
-
-
-
40
kΩ
pF
Min
Typ
Max
Unit
8
-
-
-
-
40
kΩ
pF
dBrnC0
dB
dB
Crosstalk
Parameter
Transmit to receive
VFTP,VFTN → VR,GSR
Receive to transmit
DR → DX
Condtions
VFTP,[email protected]
DR=0-Code
[email protected] code level
VFTP,VFTN=0 Vrms
Transmit op-amp characteristics:AMPT
Parameter
Conditions
Load resistance
Load capacitance
AC load, Including feedback registance
Gain
Inverting amplifire
Receive signal output characteristics:VR
Parameter
Output voltage (AGND
level)
Load resistance
Load capacitance
Receive op-amp characteristics:AMPR
Parameter
Load resistance
Load capacitance
Conditions
Conditions
AC load, Including feedback registance
Unit
70
75
-
dB
Gain
0dB setting, [email protected] input
VR,GSR differential output
With C-message
Inverting amplifire
-12
-
6
dB
Output voltage swing
DR = 3.14dBm0 digital code input
-
2.15
-
Vp-p
Min
Typ
Max
Unit
8
-
-
-
-
40
kΩ
pF
SINAD
Universal op-amp characteristics:AMP1,2
Parameter
Load resistance
Load capacitance
Conditions
AC load, Including feedback registance
62
87
-
dB
Gain
+6dB setting, [email protected] input
5Hz~30kHz measurment
Inverting amplifire
-12
-
6
dB
Output voltage swing
+6dB setting, [email protected] input
2.1
2.25
-
Vp-p
SINAD
<MS0300-E-00>
9
2004/3
ASAHI KASEI
AK2301A
PACKAGE INFORMATION
+0.03
0.17-0.05
1.0±0.2
7.8±0.1
0.5±0.2
24PIN VSOP
13
1
12
5.6
7.60±0.20
24
0.08
M
0゜~10゜
0.10
0.08
<MS0300-E-00>
0.10
0.22±0.05
1.15
1.25 +0.20
-
0.65
10
2004/3
ASAHI KASEI
AK2301A
PIN ASSIGNMENT
24PIN VSOP
TEST3
DX
BCLK
DR
FS
VDD
GSR
VFR
VR
AMP2O
AMP2I
AMP1I
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TEST2
MUTEN
RSTN
TEST1
PLLC
VSS
VREF
TAGND
VFTP
VFTN
GST
AMP1O
TEST1, TEST2 and TEST3 are test pins.
Please tie them to the VSS.
MARKING
(1)
(2)
(3)
(4)
1pin sign
Date Code: 5digit XXXXX
Marketing Code: AK2301A
AKM logo
(4)
(3)
AKM
AK2301A
XXXXX
(2)
(1)
<MS0300-E-00>
11
2004/3
ASAHI KASEI
AK2301A
CIRCUIT DESCRIPTION
BLOCK
AMPT
AMPR
AAF
CODEC
A/D
CODEC
D/A
SMF
BGREF
PCM I/F
AMP1、AMP2
<MS0300-E-00>
FUNCTION
Op-amp for input gain adjustment. This op-amp is used as an inverting or
differential amplifier. Adjusting the gain with external resistors. The resistor
should be larger than 10kΩ for the feedback resistor.
VFTN: Negative op-amp input.
VFTP: Positive op-amp input.
GST: Op-amp output.
Op-amp for output gain adjustment. This op-amp is used as an inverting
amplifier. Adjusting the gain with external resistors. The combined resistor larger
than 8kΩ is recommended for the feedback and the output load
VFR: Negative op-amp input.
GSR: Op-amp output.
VR and GSR can be used as the differential output.
Integrated anti-aliasing filter which prevents signals around the sampling rate
from folding back into the voice band. AAF is a 2 nd order RC active low-pass filter.
Converting the analog signal to 14bit PCM data.
The band limiting filter is also integrated.
Converting the 14bit PCM data from the DR to the analog signal.
Output of the D/A converter is fed into the SMF to suppress the high frequency
element.
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of the
D/A output.
Provide the stable analog ground voltage using an on-chip band-gap reference
circuit which is temperature compensated. The output voltage is 1.5V for 3.3V
An external capacitor of 1.0uF or larger should be connected between VREF and
VSS to stabilize analog ground (VREF). Please do not connect external load to
this pin. TAGND pin is used as the analog ground level output for the AMPT. An
external capacitor of 1.0uF or larger should be connected between TAGND and
VSS to stabilize analog ground.
For the PCM data rate, both 256kHz or 512kHz are available.
The 14bit PCM data is input/output by the 2’s compliment 16bit serial data
format. Two kinds of serial data format (Long Frame/Short Frame) are available.
Each data format is automatically detected by AK2301A.
PCM data is input to DR pin and output from DX pin.
Universal op-amp for the filter of the external voice path.
The maximum load is 8kΩ (including the feedback resistor and AC load).
These op-amps are assumed as using for the inverting LPF with 20kHz cut off
frequency.
12
2004/3
ASAHI KASEI
AK2301A
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin with MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is 2’s compliment 2digit data and full scale is defined as
3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter which Frequency response is designated in
page8, and converted analog signal. This analog signal is removed the high frequency element with
SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is 2's compliment 2digit data and
full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output
signal becomes 0.762Vrms.
- PCM digital code
The relation ship between the analog signal and the 14 bit linear code.
Signal level
14bit linear CODE (MSB First)
+ Full scale
01 1111 1111 1111
Peak value of the PCM 0dBm0 CODE
01 0110 0100 1010
PCM 0-CODE
00 0000 0000 0000
- Full scale
10 0000 0000 0000
<MS0300-E-00>
13
2004/3
ASAHI KASEI
AK2301A
PCM Data Interface
AK2301A supports the following 2 PCM data formats
- Long Frame Sync (LF)
- Short Frame Sync (SF)
PCM data is interfaced through the pin (DX, DR).
In each case, PCM data is interfaced by the 2’s compliment 2digit data with 16bit MSB first format.
However, internal CODEC is 14bit format operation, then the lowest 2bits output become to “L” level.
For the input, the lowest 2 bits are ignored.
Selection of the interface format
The AK2301A automatically selects the Long Frame/Short frame by means of detecting the length
frame signal.
LONG FRAME (LF) / SHORT FRAME (SF)
-Automatic LF/SF detection
AK2301A monitors the duration of the “H” level of FS and automatically selects LF or SF interface
format.
Period of FS=”H”
Frame type
More than 2clocks of BCLK
LF
1clock of BCLK
SF
Timing of the interface
16bit PCM data is accommodated in 1 flame (125µs) defined by 8kHz frame sync signal. Although there
are 4time slot at maximum in 8kHz frame (when BCLK = 512kHz), PCM data for AK2301A occupies
first time slot.
<MS0300-E-00>
14
2004/3
ASAHI KASEI
AK2301A
- Frame sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
All the internal clock of the LSI is generated based on this FS signal.
-Bit clock (BCLK)
BCLK defines the PCM data rate. BCLK rate is 256kHz or 512kHz. This clock must be synchronized
with FS.
Long Frame
FS
BCLK
DX
DR
Don't
care
1
2
3
4
5
6
7
8
9 10 11 12 13 14 L
L
1
2
3
4
5
6
7
8
9 10 11 12 13 14
1
2
3
4
5
6
7
8
9 10 11 12 13 14 L
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Don't care
Short Frame
FS
BCLK
DX
DR
Don't care
L
Don't care
Important notice!
Please don’t stop feeding FS and BCLK.
Both FS and BCLK is used as the internal reference clock. LSI does not work when the FS and BCLK are not
provided.
<MS0300-E-00>
15
2004/3
ASAHI KASEI
AK2301A
MUTE
The output of the PCM CODEC can be muted by pin control.
MUTEN pin
MUTEN pin
Operation
DX pin
0
Mute
High-Impedance
1
Normal
PCM data output
VR pin
CODEC analog
ground
CODEC analog
output
[DX pin]
When the MUTEN pin turns to “L” during the data output, the mute function becomes available at the
top of the next FS.
[VR pin]
When the MUTEN pin turns to “L”, 0 code is fed to the D/A converter and VR becomes at analog ground
level.
<MS0300-E-00>
16
2004/3
ASAHI KASEI
AK2301A
RESET and Start up sequence
Reset operation starts by low input.
This function is used for the initialization at the power up. Please use MUTEN together with RSTN to
avoid the popping sound from the output until the AK2301A moves into the stable operation.
- Start up sequence
(1) After the power on, please set the RSTN pin to low level for 10msec or more.
(2) Before the first sequence or less than 250µs after the cancellation of reset, please provide the FS and
the BCLK.
(3) Please set the MUTEN pin to low level during the period of the AK2301A’s initialization which is
less than 200msec after the FS and the BCLK provided. The CODEC voice path is established by
releasing the mute function.
less than250usec
10msec or more
VDD
RSTN
200msec or more
0.9VDD
(1)
(2)
FS
BCLK
MUTEN
<MS0300-E-00>
(3)
17
2004/3
ASAHI KASEI
AK2301A
Universal op-amps
The op-amps for construction of the external filter.
The AMP1(2)I is negative input and the AMP1(2)O is output of the op-amp.
- Circuit example
Please design output load may become 8kΩ or more. The output load includes a feedback resistor and
AC load. These op-amps are assumed to be used for 20kHz max cut off frequency LPF. And please
design the gain may become -12~6dB.
The following figure shows the circuit example.
C1
AMP1(2)I
R1
R2
C2
C3
AMP1(2)O
Load Z
VSS
Each parameter is calculated as is shown below.
LPF cut-off frequency fcL[Hz]: fcL=1/(2πR2C2)
Output load L[Ω]: L= R2Z/( R2+Z)
Gain A[dB]: A=20log (R2/ R1 )
HPF cut-off frequency fcH[Hz]: fcH=1/(2πR1C1)
<MS0300-E-00>
18
2004/3
ASAHI KASEI
AK2301A
APPLICATION CIRCUIT EXAMPLES
Analog input circuit
Analog output circuit
GST
20kohm
1uF
1uF
VR
100pF
10kohm
load
10kohm
VFTN
1uF
40kohm
1uF
VFR
VFTP
10kohm
100pF
40kohm
20kohm
TAGND
1uF
100pF
GSR
1uF
10kohm
load
VSS
Power supply, PLL loop filter
capacitor and analog ground
stabillization capacitor
Universal op-amps
1uF
20kohm
40kohm
AMP1I
200pF
VREF
VREF
PLLC
PLL
1uF
1uF
AMP1O
10kohm
load
VSS
VSS
0.33uF
1uF
20kohm
40kohm
AMP2I
200pF
VSS
1uF
VDD
AMP2O
10kohm
load
10uF
0.1uF
VSS
VSS
<MS0300-E-00>
19
2004/3
ASAHI KASEI
AK2301A
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.
(AKM) sales office or authorized distributor concerning their current status.
l AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
l Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
l AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet very
high standards of performance and reliability.
l It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in advance
of the above content and conditions, and the buyer or distributor agrees to assume any and
all responsibility and liability for and hold AKM harmless from any and all claims arising
from the use of said product in the absence of such notification.
<MS0300-E-00>
20
2004/3