APU0071 80 Segment / 16 Common Controller for Dot Matrix LCD FEATURES DOT MATRIX LCD CONTROLLER & DRIVER Internal Memory APU0071 is a dot matrix LCD driver & controller LSI that is fabricated by low power CMOS technology. It is capable of displaying 1-line 16 - Character Generator ROM (CGROM) : 7840bits (224 characters × 5 × 7dot) - Character Generator RAM (CGRAM) : 160 bit (4- characters or 2 line 16 characters with 5 × 8 dots characters × 5 × 8 dot) format. - Display Data RAM (DDRAM) : 256bits (32 FUNCTIONS characters × 8bits) • Low power operation • • • • • • - Power supply voltage range : 2.7 ~ 5.5V (VDD) Character type dot matrix LCD driver & controller. - LCD drive voltage range : 3.0 ~ 7.0 (VDD-V5) • Easy interface with 4-bit or 8-bit MPU. • Internal driver : 16 common and 80 segment CMOS process Duty cycle : 1/16 signal output. • Display character pattern : 5 × 7 dots format Built-in oscillator Low power consumption (224 kinds) • Direct programming of the special character Internal divide resistor for LCD driving voltage Available for COG patterns by character Generator RAM. • Mask open for programming customer character patterns • Various instructions function. • Automatic power on reset. ORDERING INFORMATION APU0071 R O M Code 001 : Standard 002 : Customer E Handling Code Package Type W : COG Package Type Handling Code TY : Tray ROM Code ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 1 www.anpec.com.tw APU0071 BLOCK DIAGRAM TEST Oscillator Power On Reset (POR) EXTCLK Timing generator EXT_INT RESETB 8 DB0 ~DB7 8 Instruction register (IR) Input buffer Address counter RS RW E 8 16-bit shift register Instruction Decoder Data register (IR) 8 Character generator RAM (CGRAM) 160 bits Display data RAM (DDRAM) 32*8 bits 80-bit shift register (Bidir.) 8 Character generator RAM (CGROM) 7840 bits Common driver 80-bit latch circuit Segment driver Cursor blink control circuit Parallel to Serial converter C1 ~ C16 S1 ~ S80 V DD V1 V2 V3 V4 V DD GND (V SS) Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 V5 2 www.anpec.com.tw APU0071 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 31 32 33 34 35 36 37 38 DB5 27 DB4 26 DB3 25 DB2 24 DB1 23 DB0 22 E 21 R_NW 20 RS 19 EXT_RST 18 CLK1_TS 17 M_TS 16 VDD 15 VDD 14 VDD 13 V2 12 Dummy 11 V3 10 V5 9 V5 8 V5 7 V SS 6 V SS 5 V SS 4 EXT_INT 3 EXTCLK 2 OSC_TS 1 POR_TS 126 125 124 123 121 122 3 PAD NO. : 1 ~ 30 PAD PITCH : ≥ 120 AL PAD SIZE : 96 × 96 AL PAD WINDOW: 70 × 70 AU PAD SIZE : 84 × 84 UNIT : µm DB6 28 PAD NO. : 31 ~ 126 PAD PITCH : 80 AL PAD SIZE : 62 × 102 AL PAD WINDOW: 36 × 76 AU PAD SIZE : 50 × 90 UNIT : µm DB7 29 AP Chip size¡G 6500 x 1140 (0,0) C8 C7 C6 C5 C4 C3 C2 C1 30 C16 C15 C14 C13 C12 C11 C10 C9 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 120 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 119 APU0071 PAD Diagram PAD DIAGRAM www.anpec.com.tw APU0071 PAD LOCATION Pad Name 1 POR_TS 2 OSC_TS 3 EXTCLK 4 EXT_INT 5 VSS 6 VSS 7 VSS 8 V5 9 V5 10 V5 11 V3 12 DUMMY 13 V2 14 VDD 15 VDD 16 VDD 17 M_TS 18 CLK1_TS 19 EXT_RST 20 RS 21 R_NW 22 E 23 DB0 24 DB1 25 DB2 26 DB3 27 DB4 28 DB5 29 DB6 30 DB7 31 C1 32 C2 33 C3 34 C4 35 C5 36 C6 37 C7 38 C8 39 S1 40 S2 41 S3 42 S4 X -2650.9 -2530.9 -2410.9 -2290.9 -2158.65 -2038.65 -1918.65 -1728.70 -1608.70 -1488.70 -1305.75 -1119.15 -940.20 -749.60 -629.60 -509.60 -333.50 -102.10 131.70 358.80 594.20 821.30 1054.80 1286.80 1518.40 1750.40 1982.00 2214.00 2445.60 2631.91 3149.01 3149.01 3149.01 3149.01 3149.01 3149.01 3149.01 3149.01 3163.35 3083.35 3003.35 2923.35 Y Pad Name -429.84 43 S5 -429.84 44 S6 -429.84 45 S7 -429.84 46 S8 -480.84 47 S9 -480.84 48 S10 -480.84 49 S11 -480.84 50 S12 -480.84 51 S13 -480.84 52 S14 -480.84 53 S15 -480.84 54 S16 -480.84 55 S17 -480.84 56 S18 -480.84 57 S19 -480.84 58 S20 -480.84 59 S21 -480.84 60 S22 -480.84 61 S23 -480.84 62 S24 -480.84 63 S25 -480.84 64 S26 -480.84 65 S27 -480.84 66 S28 -480.84 67 S29 -480.84 68 S30 -480.84 69 S31 -480.84 70 S32 -480.84 71 S33 -429.84 72 S34 -475.85 73 S35 -395.85 74 S36 -315.85 75 S37 -235.85 76 S38 -155.85 77 S39 -75.85 78 S40 4.15.00 79 S41 84.15 80 S42 404.67 81 S43 404.67 82 S44 404.67 83 S45 404.67 84 S46 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 X 2843.35 2763.35 2683.35 2603.35 2523.35 2443.35 2363.35 2283.35 2203.35 2123.35 2043.35 1963.35 1883.35 1803.35 1723.35 1643.35 1563.35 1483.35 1403.35 1323.35 1243.35 1163.35 1083.35 1003.35 923.35 843.35 763.35 683.35 603.35 523.35 443.35 363.35 283.35 203.35 123.35 43.35 -36.65 -116.65 -196.65 -276.65 -356.65 -436.65 4 Y 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 Pad Name 85 S47 86 S48 87 S49 88 S50 89 S51 90 S52 91 S53 92 S54 93 S55 94 S56 95 S57 96 S58 97 S59 98 S60 99 S61 100 S62 101 S63 102 S64 103 S65 104 S66 105 S67 106 S68 107 S69 108 S70 109 S71 110 S72 111 S73 112 S74 113 S75 114 S76 115 S77 116 S78 117 S79 118 S80 119 C16 120 C15 121 C14 122 C13 123 C12 124 C11 125 C10 126 C9 X -516.65 -596.65 -676.65 -756.65 -836.65 -916.65 -996.65 -1076.65 -1156.65 -1236.65 -1316.65 -1396.65 -1476.65 -1556.65 -1636.65 -1716.65 -1796.65 -1876.65 -1956.65 -2036.65 -2116.65 -2196.65 -2276.65 -2356.65 -2436.65 -2516.65 -2596.65 -2676.65 -2756.65 -2836.65 -2916.65 -2996.65 -3076.65 -3156.65 -3137.66 -3137.66 -3137.66 -3137.66 -3137.66 -3137.66 -3137.66 -3137.66 Y 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 404.67 95.82 15.82 -64.18 -144.18 -224.18 -304.18 -384.18 -464.18 www.anpec.com.tw APU0071 PIN DESCRIPTION PIN VDD VSS (GND) V2,V3,V5 S1 ~ S80 C1 ~ C16 Input / Output P Output Output EXTCLK Input EXT_INT Input RS Input R_NW Input E Input DB0 ~ DB3 Input / Output DB4 ~ DB7 EXT_RST Input OSC_TS POR_TS M_TS CLK1_TS Output Output Output Output Name Description Interface For logical circuit (+3v,+5v) Power supply & LCD Power 0V (GND) Bias pin Supply Bias voltage level for LCD driving Segment output Segment signal output for LCD driving LCD Common output Common signal output for LCD driving LCD When using external clock, used as clock input pin. External External clock Input clock When using internal oscillator, connect to VDD or VSS. External / Internal When EXT_INT = “High”, external clock is used. MPU oscillator clock select When “Low”, instruction oscillator is used. Used as register selection input. Register select When RS = “High”, data register is selected. When RS = “Low”, instruction register is selected. Used as read / write selection input. Read / Write When RW = “High”, read operation. When RW = “Low”, write operation. Read / Write enable Used as read / write enable signal. When 8-bit bus mode, used as low order bi-directional MPU data bus. During 4-bit bus mode open these pins. When 8-bit bus mode, used as high order bi-directional Data Bus 0 ~ 7 data bus. In case of 4-bit bus mode, used as both high and low order. DB7 is used for Busy Flag output during read instruction operation. If it is necessary to initialize the system by hardware, Reset force “Low”, level signal to this terminal about 1.2 ms. Test Pin Internal oscillator test pin. Open this pin. Test Pin Internal test pin. Open this pin. Test Pin Internal test pin. Open this pin. Test Pin Internal test pin. Open this pin. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 5 www.anpec.com.tw APU0071 FUNCTION DESCRIPTION 1. SYSTEM INTERFACE This chip consists of two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit of function set in the instruction register. During read or write operation, two 8-bit registers are used. One is the data register (DR); the other is the instruction register (IR) . The data register (DR) is used as a temporary data storage place for being written into or read from DDRAM / CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next DDRAM / CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM / CGRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot read data from instruction register. Table 1. Various kinds of operation according to RS and R / W bits. RS 0 0 1 1 R/L 0 1 0 1 Operation Instruction Write operation (MPU Writes Instruction into IR) Read Busy flag (DB7) and address counter (DB0 ~ DB6) Data Write operation (MPU Writes data into DR) Data Read operation (MPU Writes data into DR) The register selection depends on RS input pin setting in both 4-bit bus mode. 2. BUSY FLAG (BF) BF = “High” it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R / W = High (Read instruction Operation) , through DB7 port. Before exciting the next instruction, be sure that BF is not High. 3. ADDRESS COUNTER (AC) Address Counter (AC) stores the address of DDRAM / CGRAM that are transferred from IR. After writing into (reading from) DDRAM / CGRAM data, AC is increased (decreased) by 1 automatically. When RS = “Low”, and R / W = “High”, AC value can be read through DB0 ~ DB6 ports. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 6 www.anpec.com.tw APU0071 4. DISPLAY DATA RAM (DDRAM) DDRAM stores 8bits character code in CGROM / CGRAM and its maximum number is 32 (32 Characters) . DDRAM address is set by the address counter (AC) as a hexadecimal number. MSB AC6 LSB AC5 AC4 AC3 AC2 HEX AC1 AC0 HEX 4-1. DDRAM addressing mode 0 (A = 0) (1 Line) In this addressing mode, the address range of DDRAM is 00H ~ 0FH. 1 Display Position 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DDRAM Address COM1~COM8 COM9~COM16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 After shift left COM1~COM8 COM9~COM16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E After shift right COM1~COM8 COM9~COM16 4-2. DDRAM addressing mode 1 (A = 1) (2 Line) In this addressing mode, the address range of DDRAM is 00H ~ 0FH and 40H ~ 4FH. 1 Display Position COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DDRAM Address 1 Display Position COM9 COM16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F DDRAM Address 1 COM1 COM8 COM9 COM16 COM9 COM16 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1 After shift right 4 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 00 1 COM1 COM8 3 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 1 After shift left 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 7 www.anpec.com.tw APU0071 5. CHARACTER GENERATOR RAM (CGRAM) CGRAM is used for user defined character pattern. The format of the character pattern is 5 × 7 dots except for the cursor position and has a maximum of 4 characters. To use the character pattern in CGRAM write the character code into DDRAM as shown in table 2. Table 2. Relationship between character Code (DDRAM) and Character Pattern (CGRAM) Character Code ( DDRAM data ) CGRAM address Pattern CGRAM data 2 1 0 4 3 2 1 0 4 3 2 1 0 0 0 0 0 ∗ ∗ 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 ∗ ∗ 0 0 Number Pattern 1 cursor position ................. 3 ................. 4 ................. 5 ................. 6 ................. 7 Pattern 4 cursor position Note : The asterisk means "don't care". Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 8 www.anpec.com.tw APU0071 6. CHARACTER GENERATOR ROM (CGROM) CGROM generates 5 × 5 × 7 character pattern from character generate code in DDRAM. CGROM has 5 × 7-dot 224-character pattern excluding cursor position. The relationship between character code and character pattern can be referred to Table 5. 7. TIMING GENERATION CIRCUIT Timing generation circuit generates clock signals for the internal operations. 8. LCD DRIVER CIRCUIT LCD driver circuit has 16 common and 80 segment output signals for LCD driving. Data from CGRAM / CGROM is transferred to 80-bit segment shift register in a serially, which is then it is stored to 80-bit segment output latch. When each COM is selected by a 16-bit common register, the segment data also outputs through segment driver from 40-bit segment output latch. 9. CURSOR / BLINK CONTROL CIRCUIT It controls cursor / blink ON / OFF at the cursor position. INSTRUCTION DESCRIPTION 1. OUTLINE To overcome the speed difference between the internal clock of APU0071 and the MPU clock, the APU0071 per-forms an internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read / write and data bytes. Instruction can be divided into four types : 1-1. APU0071 function set instructions (set display methods, set data length, etc.) 1-2. Address set instructions to internal RAM 1-3. Data transfer instructions with internal RAM 1-4. Others The address of internal RAM is automatically increased or increased by 1. Note : During an internal operation, the Busy Flag (DB7) is High. Busy Flag check must precede the next instruction. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 9 www.anpec.com.tw APU0071 Table 3. Instruction Table Instruction Code Instruction RS R / W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Return Home 0 0 0 0 0 0 0 0 1 ∗ Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Display ON / OFF Control 0 0 0 0 0 0 1 D C B Cursor or Display Shift 0 0 0 0 0 1 ∗ ∗ Function Set 0 0 0 0 1 DL M1 M0 Set CG RAM Address 0 0 0 1 ∗ Set DD RAM Address 0 0 1 Read Busty DDRAM Flag and Address CGRAM 0 1 BF Write Data to RAM DDRAM Read Data from RAM DDRAM CGRAM CGRAM S/ R/L C A ∗ AC4 AC3 AC2 AC1 AC0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 1 1 D7 ∗ D7 ∗ ∗ ∗ D6 ∗ D6 ∗ D5 ∗ D5 ∗ AC4 AC3 AC2 AC1 AC0 D4 D4 D4 D4 D3 D3 D3 D3 I / D = 1 : Increment, S = 1 : Shift enable, S / C = 1 : Display shift, R / L = 1 : Shift right, D / L = 1 : 8 bit interface, A = 0 : DDRAM addressing mode 0, M0 = 0 : Bottom view, M1 = 0 : No Rotate, BF = 1 : System is in operation Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 D2 D2 D2 D2 D1 D1 D1 D1 Description Write “20H” to DDRAM and set DDRAM address to “00H” from AC. Set DDRAM address to “00H” from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction and enable entire display shift. All display (D) , cursor (C) , and blinking of cursor position character on / off control bit (B) . Cursor and Display shift and their direction control without changing DDRAM data. Set interface data length (DL) , DDRAM addressing mode (A) and COM / SEG output pattern (M0, M1) . Set CGRAM address in address counter. Set DDRAM address in address counter. Whether in internal operation or not can be known by reading BF. The contents of address counter can also be read. Write data into internal RAM (DDRAM / CGRAM) . D0 D0 D0 Read data from internal D0 RAM (DDRAM / CGRAM) . Execution time (fOSC=270 kHz) 629µs 629µs 37µs 37µs 37µs 37µs 37µs 37µs 0µs 43µs 43µs I / D = 0 : Decrement S = 0 : Shift disable S / C = 0 : Move cursor R / L = 0 : Shift left D / L = 0 : 4-bit interface A = 1 : DDRAM addressing mode1 M0 = 1 : Top view M1 = 1 : Rotate BF = 0 : System is ready 10 www.anpec.com.tw APU0071 1-1. Clear Display Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing “20H” (space code of CGROM) to all DDRAM address, and set DDRAM address to “00H” into AC (Address Counter) . For this instruction, the CGROM address ”20H” has to be set to space code. Shifting of the display position returns it to the original position. Namely, when display data is disappeared and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to increment (I / D = 1) 1-2. Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 ∗ Code " ∗ " : Don't care Set DDRAM address to ”00H” into the address counter. Shifting of the display position returns it to the original position. When cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. The data in DDRAM does not change. 1-3. Entry Mode Set Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S Set the moving direction of cursor and display. I / D : Increment / decrement of DDRAM / CGRAM address (cursor or blink) When I / D = “High”, cursor / blink moves to right and DDRAM address is increased by 1. When I / D = “Low”, cursor / blink moves to left and DDRAM address is decreased by 1. S : Shift of entire display When DDRAM read (CGRAM read / write) operation or S = “Low”, entire display is not shifting. If S = “High”, and DDRAM write operation, entire display is sifted according to I / D value (I / D = “1” : shift left, I / D = “0” : shift right) . Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 11 www.anpec.com.tw APU0071 1-4. Display ON / OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B Code Control display / cursor / blink ON / OFF 1 bit register. D : Display ON / OFF control bit When D = “High”, entire display is turned on. When D = “Low”, entire display is turned off, but display data is remains in DDRAM. C : Cursor ON / OFF control bit When C = “High”, cursor is turned on. When C = “Low”, cursor is disappeared in current display, but I / D register preserves its data. B : Cursor Blink ON / OFF control bit When B = “High”, cursor blink is on, performs alternately between all high data (black pattern) and display character at the cursor position. When B = “Low”, blink is off. 1-5. Cursor or Display Shift Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L ∗ ∗ " ∗ " : Don't care Without writing or reading of display data, shift right / left the cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 16th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of address counter are not changed. Table 4. Shift patterns according to S / C and R / L bits Operation S / C R/ L 0 0 Shift cursor to the left, AC is decreased by 1 0 1 Shift cursor to the right, AC is increased by 1 1 0 Shift all the display to the left, cursor moves according to the display 1 1 Shift all the display to the right, cursor moves according to the display Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 12 www.anpec.com.tw APU0071 1-6. Function Set Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL A ∗ M1 M0 " ∗ " : Don't care DL : Interface data length control bit When DL = “High”, 8-bit bus mode with MPU. When DL = “Low”, 4-bit bus mode with MPU. Thus, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, the 4-bit data is transferred twice. A : Set the display data-addressing mode When A = “Low”, DDRAM addressing mode 0. (1 Line) When A = “High”, DDRAM addressing mode 1. (2 Line) M0 : Set COM / SEG output rotation When M0 = “Low”, Bottom view. When M0 = “High”, Top view. M1 : Set display line and character mode When M1 = “Low”, LCD module Rotation mode A. When M1 = “High”, LCD module Rotation mode B. (Refer to Application information) 1-7. Set CGRAM Address Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ∗ AC4 AC3 AC2 AC1 AC0 MSB LSB " ∗ " : Don't care Set CGRAM address to AC. This instruction allows the MPU to access CGRAM data for user defined character pattern. Available CGRAM Address is lower 5 bits (DB4 ~ DB0) . Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 13 www.anpec.com.tw APU0071 1-8. Set DDRAM Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Code Set DDRAM address to AC. This instruction allows the MPU to access DDRAM data. When DDRAM addressing mode 1 (A = 0) , DDRAM address is from “00H” to “0FH”. In DDRAM addressing mode 2 (A = 1) , DDRAM address range of the 1st 16 character is “00H” to “0FH”, and DDRAM address range of the 2nd 16 character is “40H” to “4FH”. 1-9. Read Busy Flag & Address Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 LSB MSB Code DDRAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 BF ∗ ∗ AC4 AC3 AC2 AC1 AC0 MSB CGRAM LSB " ∗ " : Don't care This instruction shows whether APU0071 is in internal operation or not. If the resultant BF is High, The internal operation is in progress and should wait until BF to be Low, which by then the next instruction can be performed. In the instruction you can read also the value of address counter. 1-10. Write data to RAM Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB Code DDRAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 ∗ ∗ ∗ D4 D3 D2 D1 D0 MSB CGRAM LSB " ∗ " : Don't care Write binary 8/5 bit data to DDRAM / CGRAM. The selection of RAM from DDRAM / CGRAM is set by the previous address set instruction (DDRAM address set, CGRAM address set) . After writing operation, the address is automatically increased / decreased by 1, according to the entry mode. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 14 www.anpec.com.tw APU0071 1-11. Read data from RAM Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB Code DDRAM RS R/W DB7 DB6 1 0 ∗ ∗ DB5 ∗ DB4 DB3 DB2 DB1 DB0 D4 D3 D2 D1 D0 MSB CGRAM LSB " ∗ " : Don't care Read BINARY 8 / 5 bit from DDRAM / CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, data that was read first becomes invalid, as the direction of AC is not determined. If RAM data is read several times without RAM address set instruction before read operation, the correct RAM data can be detained from the second, but the first data would be incorrect, as there is no time margin to transfer the RAM data. In case of DDRAM reading operation, the cursor shift instruction plays the same role as DDRAM address set instruction also transfers RAM data to output data register. After read operation address counter is automatically increased / decreased by 1 according to the entry mode. After CGRAM read operation is, the display shift may not be executed correctly. ∗ In case of RAM write operation, AC is increased / decreased by 1 like read operation (after this operation) . In this time, AC indicates the next address position, but only the previous data can be read by read instruction. 2. INTERFACE with MPU 2-1. Interface with 8-bit MPU With 8-bit interfacing data length transfer is performed at a time through 8 ports, from DB0 to DB7. Example of timing sequence is shown below. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 15 www.anpec.com.tw APU0071 RS R / W E Internal operation Internal signal DB7 DATA INSTRUCTION Busy Busy Busy Flag Check No Busy DATA Busy Flag Check Busy Flag Check INSTRUCTION Fig 1. Example of 8-bit Bus Mode Timing Diagram 2-2. Interface with 4-bit MPU When interfacing data lengths are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4-DB7) are transferred, then the lower 4bit (in case of 8-bit bus mode, the contents of DB0-DB3) are transferred. So transfer is performed twice. Busy Flag outputs “High” after the second transfer are ended. Example of timing sequence is shown below. RS R/W E Internal signal DB7 Internal operation D7 D3 INSTRUCTION Busy No Busy A C 3 AC3 D7 D3 Busy Flag Check Busy Flag Check INSTRUCTION Fig 2. Example of 4-bit Bus Mode Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 16 www.anpec.com.tw APU0071 APPLICATION INFORMATION 1. COM / SEG output rotation mode A 1-1. DDRAM address mode 1 (A = 1) (2 Line) ................ C1 ................ C9 APU0071 BOTTOM VIEW C16 C8 S80 ..................................................... S21 S20 ..................................................... S1 S80 S21 S20 S1 (M0 = 0, M1 = 0) 1-2. DDRAM address mode 1 (A = 1) (2 Line) S1 S20 S21 S80 APU0071 BOTTOM VIEW C1 .................... .................... S1 ...................................................... S20 S21 ...................................................... S80 C8 C16 C9 (M0 = 0, M1 = 1) Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 17 www.anpec.com.tw APU0071 2. COM / SEG output rotation mode B 2-1. DDRAM address mode 1 (A = 1) (2 Line) ................ C9 ................ C1 APU0071 TOP VIEW C8 C16 S1 ........................................................ S20S21 ....................................................... S80 S1 S20 S21 S80 (M0 = 1, M1 = 0) 2-2. DDRAM address mode 1 (A = 1) (2 Line) S80 S21 S20 S1 APU0071 TOP VIEW C9 ................. ................. S80 ..................................................... S21 S20 ........................................................ S1 C16 C8 C1 (M0 = 1, M1 = 1) Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 18 www.anpec.com.tw APU0071 3. POWER SUPPLY for DRIVING LCD PANEL APU0071 VDD R V1 R V2 R V3 R V4 R V5 ∗R = 1.5KΩ(Typ) ± 5 0 % Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 19 www.anpec.com.tw APU0071 INTIALIZING 1. INITIALIZE BY INTERNAL POWER-ON-RESET CIRCUIT When the power is turned on, APU0071 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept “High” (busy state) up to the end of initialization. 2. POWER ON INITIALIZE FLOW 2-1 . Display Clear Write “20H” to all DDRAM 2-2 . Set Functions DL = 1 : 8-bit bus mode A = 1 : 2 Line M0 = 0 : No Rotation M1 = 1 : Bottom view mode 2-3 . Control Display ON / OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF 2-4 . Set Entry Mode I / D = 1 : Increment by 1 S = 0 : No entire display shift 3. INITIALIZE BY EXTERNAL HARDWARE RESET If the “Low” signal is forced to reset terminal over a period of 1.2 ms then system will be initialized. And BF (Busy Flag) is kept “High” (busy state) for 629 us after releasing the initializing sequence. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 20 www.anpec.com.tw APU0071 4. INITIALIZING BY INSTRUCTION 4-1. 8-bit interface mode Power on Wait for more than 20ms after V D D rises to 4.5V Condition : f O S C = 270kHz DL Function set RS 0 RW 0 DB7 0 DB6 0 DB5 DB4 A DB3 1 DL A DB2 DB1 0 4-bit interface 1 8-bit interface 0 DDRAM Addressing mode 1 1 DDRAM Addressing mode 2 0 COM / SEG output rotation mode A 1 COM / SEG output rotation mode B 0 1line 16 character display mode 1 2line 8 character display mode DB0 ∗ M1 M0 M0 M1 Wait for more than 37 µs D Display ON/OFF Control RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B C B 0 display off 1 display on 0 cursor off 1 cursor on 0 blink off 1 blink on Wait for more than 37 µs Display Clear RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Wait for more than 629 µs Entry Mode Set 0 decrement mode 1 increment mode 0 entire shift off 1 entire shift on I/D RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 0 0 0 0 1 I/D DB0 S S Initialization End Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 21 www.anpec.com.tw APU0071 4-2. 4-bit interface mode Power on Wait for more than 20ms after V D D rises to 4.5V Function set RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 X Condition : f O S C = 2 7 0 k H z DB2 X DB1 X DB0 X DL Wait for more than 37µs A Function set M0 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X 0 0 A X M1 M0 X X X X M1 Wait for more than 37µs D Display ON/OFF Control C RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 1 D C B X X X X B 0 4-bit interface 1 8-bit interface 0 DDRAM Addressing mode 1 1 DDRAM Addressing mode 2 0 COM / SEG output rotation mode A 1 COM / SEG output rotation mode B 0 1line 16 character display mode 1 2line 8 character display mode 0 display off 1 display on 0 cursor off 1 cursor on 0 blink off 1 blink on 0 decrement mode Wait for more than 37µs Display Clear RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 0 0 1 X X X X Entry Mode Set I/D RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 increment mode 0 0 0 0 0 0 X X X X 0 entire shift off 0 0 0 1 I/D SH X X X X 1 entire shift on S Initialization End Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 22 www.anpec.com.tw APU0071 Frame frequency 1/16 duty cycle 1-line selection period 1 2 3 ............. 4 15 16 1 2 3 ............. 15 16 VCC COM1 ....... V1 V4 V5 1 FRAME 1 FRAME 1-Line selection period = 160 clocks One Frame = 40 × 16 × 3.7µs × 4 = 9.472ms (1 CLOCK = 3.7µs at fosc=270KHz) Frame frequency = 1 / 9.472ms = 105.6Hz Maximum absolute limit Maximum absolute Power Ratings ∗Voltage greater than above may damage to the circuit (VDD ≥ V2 ≥ V3 ≥ V5 , VLCD = VDD - V5) Item Symbol Unit Value Power supply voltage (1) V DD V -0.3 to +7.0 Power supply voltage (2) V LCD V -0.3 to +7.0 Input voltage V IN V -0.3 to VD D +0.3 Item Symbol Unit Operation temperature Topr oC -30 to +85 Storage temperature Tstg oC -55 to +125 Temperature Characteristics Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 23 Value www.anpec.com.tw APU0071 Electrical characteristics DC Characteristics (VDD = 4.5V to 5.5V, Ta = -30 to +85°C) Item Operating Voltage Supply Current Symbol VDD IDD Condition Internal oscillation (VDD = 5.0V, fOSC = 270KHz) VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG IIL IOH = -0.205 (mA) Low Input Current LCD Driving Voltage Input Voltage (1) (EXTCLK) Input Voltage (2) (EXTCLK) Input Voltage (2) (E pin) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0 to DB7) Voltage Drop Input Leakage Current Divide Resistor Internal Clock (internal Rf) LCD Driving Voltage IOL = 1.6 (mA) Min 4.5 Typ Max 5.5 Unit V 1.0 1.8 mA 0.7VDD -0.3 VDD -1.0 -0.2 0.8 VDD VDD 0.8 VDD 1.0 VDD 0.2 VDD 0.4 ¡V 2.4 ¡V IO = -40 (µA) 0.9 VDD IO = 40 (µA) VIN = 0V to VDD -1 IIN VIN = 0V, VDD = 5V (PULL UP) V2 V3 RB fIC VLCD Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 ¡V V V V V V 0.1 VDD 1 1 1 µA -50 -125 -250 µA VDD = 5V, V5 = 0V SEG output port 2.7 1.7 3.0 2.0 3.3 2.3 V VDD - V5 = 5V RB = (VDD - V5) / IB IB = Divide Resistor Current 3.7 7.5 11.5 KΩ 190 3.0 270 350 7.0 KHz V IO = ±0.1 (mA) VDD = 5V VDD - 5V 24 V www.anpec.com.tw APU0071 o (VDD = 2.7V to 4.5V, Ta = -30 to +85 C) Item Operating Voltage Supply Current Symbol VDD IDD Condition Max 4.5 Unit V 0.5 1.2 mA 0.7VDD -0.3 VDD -1.0 -0.2 0.8 VDD VDD 0.4 VDD 0.2 VDD VDD 0.4 IOH = -0.1 (mA) 0.75 VDD IOL = 1.1 (mA) 0.2 VDD IO = -40 (µA) 0.8 VDD IO = 40 (µA) µA Internal oscillation (VDD = 3.0V, fOSC = 270KHz) Min 2.7 Typ VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOH1 VOH2 VOH2 VdCOM VdSEG IIL IO = ±0.1 (mA) VLCD = 5V VIN = 0V to VDD -1 0.2 VDD 1 1 1 Low Input Current IIN VIN = 0V, VDD = 3V (PULL UP) -10 -50 -120 µA LCD Driving Voltage V2 V3 VDD = 3V, V5 = -2V SEG output port 0.7 -1.7 1.0 0 1.3 0.3 V RB VDD - V5 = 5V RB = (VDD - V5) / IB IB = Divide Resistor Current 3.7 7.5 11.5 KΩ 190 3.0 270 350 7.0 KHz V Input Voltage (1) (except OSC1) Input Voltage (2) (OSC1) Input Voltage (2) (E pin) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0 to DB7) Voltage Drop Input Leakage Current Divide Resistor Internal Clock (internal Rf) LCD Driving Voltage fIC VLCD VDD = 3V VDD - 5V V V V V V V Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 25 www.anpec.com.tw APU0071 AC Characteristics (VDD = 4.5V to 5.5V, Ta = -30 to +85°C) Mode Item E Cycle Time E Rise / Fall Time E Pules Width (High, Low) Write Mode R / W and RS Setup Time (Refer to Fig-3) R / W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time E Pules Width (High, Low) Read Mode R / W and RS Setup Time (Refer to Fig-4) R / W and RS Hold Time Data Setup Time Data Hold Time Symbol tC tr , tf tW tSU1 th1 tSU2 th2 tC tr , tf tW tSU th tD tDH Min 500 Typ Max 20 230 40 10 80 10 500 20 230 40 10 120 20 Unit ns ns (VDD = 2.7V to 4.5V, Ta = -30 to +85°C) Mode Item E Cycle Time E Rise / Fall Time E Pules Width (High, Low) Write Mode R / W and RS Setup Time (Refer to Fig-3) R / W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time E Pules Width (High, Low) Read Mode R / W and RS Setup Time (Refer to Fig-4) R / W and RS Hold Time Data Setup Time Data Hold Time Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 26 Symbol tC t r , tf tW tSU1 th1 tSU2 th2 tC t r , tf tW tSU th tD tDH Min Typ 1000 Max Unit 25 450 60 20 195 10 1000 25 450 60 20 360 5 ns ns www.anpec.com.tw APU0071 RS V IL1 V IH1 V IH1 V IL1 tS U 1 R / W t h1 V IL1 t h1 tW E V IL1 V IH1 V IL1 t h2 tS U 2 tr V IH1 DB0 ~ DB7 tf V IL1 V IH1 Valid Data V IL1 V IL1 tC Fig-3. Write Mode Timing Diagram V IH1 RS V IL1 R / W tS U th V IH1 E tW V IL1 tr DB0 ~ DB7 th V IH1 tf V IH1 V IL1 tD H tD VOH1 Valid Data VOL1 V IH1 tC V IL1 VOH1 VOL1 Fig-4. Read Mode Timing Diagram Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 27 www.anpec.com.tw APU0071 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 28 www.anpec.com.tw