OPA2690 SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable FEATURES DESCRIPTION D FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply ±2.5V to ±6V Dual Supply D D D D D D WIDEBAND +5V OPERATION: 220MHz (G = 2) HIGH OUTPUT CURRENT: 190mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 1800V/µs LOW SUPPLY CURRENT: 5.5mA/ch LOW DISABLED CURRENT: 100µA/ch APPLICATIONS D D D D D D D The OPA2690 represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full-power bandwidth previously found only in wideband, current-feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These give exceptional single-supply operation. Using a single +5V supply, the OPA2690 can deliver a 1V to 4V output swing with over 120mA drive current and 150MHz bandwidth. This combination of features makes the OPA2690 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. The low 5.5mA/ch supply current of the OPA2690 is precisely trimmed at +25°C. This trim, along with low temperature drift, ensures lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, will operate the OPA2690I-14D normally. If pulled LOW, the OPA2690I-14D supply current drops to less than 200µA/ch while the output goes to a high-impedance state. VIDEO LINE DRIVING xDSL LINE DRIVER/RECEIVER HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS OPA2690 RELATED PRODUCTS +5V 100Ω 2kΩ +2.5V +2.5V 0.1µF +5V 100pF 1 /2 O P A 2 6 90 2kΩ REFB 499Ω REFT Voltage-Feedback Current-Feedback Fixed Gain SINGLES DUALS TRIPLES OPA2690 OPA691 OPA692 OPA2680 OPA2691 — OPA3690 OPA3691 OPA3692 0.1µF 499Ω 1kΩ 35Ω HARMONIC DISTORTION vs FREQUENCY FOR THE SINGLE−SUPPLY ADC DRIVER IN 10pF 2.5VCM 2VPP VIN 35Ω 499Ω ADS825 − 50 10−Bit 40MSP S − 55 10pF 1 /2 O P A 2 6 90 +2.5V Harmonic Distortion (dBc) IN 1kΩ 499Ω Clock Single-Supply Differential ADC Driver 2VPP Differential Output − 60 − 65 − 70 − 75 − 80 3rd−Harmonic − 85 − 90 2nd−Harmonic − 95 −100 1 10 20 Frequency (MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2002−2004, Texas Instruments Incorporated ! ! www.ti.com "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 ABSOLUTE MAXIMUM RATINGS(1) Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . See Thermal Analysis Section Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range: D, 14D . . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Resistance: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) OPA2690 SO-8 D −40°C to +85°C OPA2690 OPA2690 SO-14 D −40°C to +85°C OPA2690 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA2690ID Rails, 100 OPA2690IDR Tape and Reel, 2500 OPA2690I-14D Rails, 58 OPA2690I-14DR Tape and Reel, 2500 (1) For the most current specification and package information, refer to our web site at www.ti.com. PIN ASSIGNMENTS Top View SO Out A 1 − In A 2 +In A 3 −VS 4 A B 8 +VS 7 Out B 6 − In B 5 +In B Top View SO − In A 1 14 Out A +In A 2 13 NC DIS A 3 12 NC −VS 4 11 +VS DIS B 5 10 NC +In B 6 9 NC − In B 7 8 Out B NC = No Connection 2 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Mode Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 165 20 200 160 19 190 150 18 180 1400 1200 900 −68 −77 −70 −81 5.5 3.1 0.06 0.03 −85 −64 −70 −68 −78 −62 −68 −66 −76 69 ±1.0 58 ±4.5 +5 ±11 ±0.1 ±1.0 VCM = ±1V ±3.5 65 ±3.4 60 VCM = 0V VCM = 0V 190 0.6 3.2 0.9 No Load 100Ω Load VO = 0V VO = 0V VO = 0V G = +2, f = 100kHz ±4.0 ±3.9 +190 −190 ±250 0.04 CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = 25Ω G = +2, VO = 0.5VPP G = +10, VO = 0.5VPP G ≥ 10 G = +2, VO < 0.5VPP VO < 0.5VPP G = +2, VO = 5VPP G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 5V Step G = +2, VO = 5V Step G = +2, VO = 5V Step G = +2, f = 5MHz, VO = 2VPP RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4VP, RL = 150Ω G = +2, NTSC, VO = 1.4VP, RL = 150Ω f = 5MHz, Input-Referred 500 220 30 300 30 4 200 1800 1.4 2.8 12 8 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±3.8 ±3.7 +160 −160 UNITS MIN/ MAX TEST LEVEL(3) MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns typ min min min typ typ typ min typ typ typ typ C B B B C C C C C C C C −60 −66 −64 −75 dBc dBc dBc dBc nV/√Hz pA/√Hz % deg dBc max max max max typ typ typ typ B B B C C C C 56 ±5.0 ±12 ±12 ±20 ±1.4 ±1.0 54 ±5.2 ±12 ±13 ±40 ±1.6 ±1.5 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B ±3.3 57 ±3.2 56 V dB min min A A kΩ pF MΩ pF typ typ C C V V mA mA mA Ω min min min min typ typ A A A A C C ±3.7 ±3.6 +140 −140 ±3.6 ±3.3 +100 −100 (1) Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. (2) (3) 3 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP PARAMETER DISABLE (SO-14 Only) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) CONDITIONS Disabled LOW VDIS = 0, Both Channels VIN = 1VDC VIN = 1VDC G = +2, RL = 150Ω, VIN = 0 G = +2, RL = 150Ω, VIN = 0 VDIS = 0, Each Channel MIN/MAX OVER TEMPERATURE +25°C +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVEL(3) −200 200 25 70 4 ±50 ±20 3.3 1.8 75 −400 −480 −520 µA ns ns dB pF mV mV V V µA max typ typ typ typ typ typ min max max A C C C C C C A A A 3.5 1.7 130 3.6 1.6 150 3.7 1.5 160 ±6.0 11.6 10.6 68 ±6.0 12.4 9.2 66 ±6.0 13.2 8.6 64 V typ C V mA mA dB max max min min A A A A −40 to +85 °C typ C 125 100 °C/W °C/W typ typ C C POWER SUPPLY ±5 Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current (2 Channels) Minimum Quiescent Current (2 Channels) Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specified Operating Range: D, 14D Thermal Resistance, qJA D SO-8 14D SO-14 (1) VS = ±5V VS = ±5V Input-Referred 11 11 75 Junction-to-Ambient Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. (2) (3) 4 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP PARAMETER AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Mode Common-Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance (1) (2) (3) (4) (5) MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 150 18 180 145 17 170 140 16 160 700 670 550 UNITS MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns typ min min min typ typ typ min typ typ typ typ C B B B C C C B C C C C −56 −66 −60 −70 dBc dBc dBc dBc nV/√Hz pA/√Hz % deg max max max max typ typ typ typ B B B B C C C C 54 ±4.8 ±10 ±12 ±20 ±1.4 ±7 52 ±5.2 ±10 ±13 ±40 ±1.6 ±9 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B 1.7 3.3 56 1.8 3.2 54 V V dB max min min A A A kΩ pF MΩ pF typ typ C C V V V V mA mA mA Ω min min max max min min typ typ A A A A A A C C CONDITIONS +25°C G = +1, VO < 0.5VPP, RF = ±25Ω G = +2, VO < 0.5VPP G = +10, VO < 0.5VPP G ≥ 10 G = +2, VO < 0.5VPP VO < 0.5VPP G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2VPP RL = 100Ω to VS/2 RL ≥ 500Ω to VS/2 RL = 100Ω to VS/2 RL ≥ 500Ω to VS/2 f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4VP, RL = 150 to VS/2 G = +2, NTSC, VO = 1.4VP, RL = 150 to VS/2 400 190 25 250 20 5 220 1000 1.6 2.0 12 8 −65 −75 −68 −77 5.6 3.2 0.06 0.02 −60 −70 −64 −73 −59 −68 −62 −71 VO = 2.5V, RL = 100Ω to VS/2 VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V 63 ±1.0 56 ±4.5 +5 ±11 ±0.3 ±1.0 VCM = 2.5V ± 0.5V 1.5 3.5 63 1.6 3.4 58 VCM = 2.5V VCM = 2.5V 92 1.4 2.2 1.5 No Load RL = 100Ω to 2.5V No Load RL = 100Ω to 2.5V 4 3.9 1 1.1 +160 −160 ±250 0.04 G = +2, f = 100kHz 3.8 3.7 1.2 1.3 +120 −120 TEST LEVEL MIN/ MAX 3.6 3.5 1.4 1.5 +100 −100 3.5 3.4 1.5 1.7 +80 −80 (3) Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Current is considered positive out-of-node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ± CMIR limits. 5 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 2 for AC performance only), unless otherwise noted. OPA2690ID, I-14D TYP PARAMETER DISABLE (SO-14 Only) Power-Down Supply Current (+VS) Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (VDIS) CONDITIONS Disabled LOW VDIS = 0, Both Channels G = +2, 5MHz G = +2, RL = 150Ω, VIN = VS/2 G = +2, RL = 150Ω, VIN = VS/2 VDIS = 0, Each Channel MIN/MAX OVER TEMPERATURE +25°C +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) −200 65 4 ±50 ±20 3.3 1.8 75 −400 −480 −520 3.5 1.7 130 3.6 1.6 150 3.7 1.5 160 12 10.88 8.96 12 11.44 8.0 12 12.1 7.72 TEST LEVEL UNITS MIN/ MAX µA dB pF mV mV V V µA max typ typ typ typ min max typ A C C C C A A C V typ C V mA mA dB max max min typ B A A C −40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C (3) POWER SUPPLY Specified Single-Supply Operating Voltage Maximum Single-Supply Operating Voltage Maximum Quiescent Current (2 Channels) Minimum Quiescent Current (2 Channels) Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, 14D Thermal Resistance, qJA D SO-8 14D SO-14 (1) 5 VS = +5V VS = +5V Input-Referred 9.8 9.8 72 Junction-to-Ambient Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. (2) 6 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. SMALL−SIGNAL FREQUENCY RESPONSE 6 VO = 0.5VPP 3 6 0 G=2 G=5 −3 −6 Gain (3dB/div) Normalized Gain (3dB/div) LARGE−SIGNAL FREQUENCY RESPONSE 9 G = +1 RF = 25Ω G = 10 −9 VO = 2VPP 3 VO = 1VPP 0 VO = 4VPP −3 −12 VO = 7VPP −15 0.7 10 100 −6 0.5 700 Frequency (MHz) SMALL−SIGNAL PULSE RESPONSE 100 500 LARGE−SIGNAL PULSE RESPONSE G = +2 VO = 0.5VPP G = +2 VO = 5VPP 3 Output Voltage (1V/div) 300 Output Voltage (100mV/div) 10 Frequency (MHz) 4 400 200 100 0 −100 −200 2 1 0 −1 −2 −3 −300 −4 −400 Time (5ns/div) Time (5ns/div) CHANNEL−TO−CHANNEL CROSSTALK COMPOSITE VIDEO dG/dP +5V No Pull−Down With 1.3kΩ Pull−Down Video In 0.175 75Ω 1 /2 O P A 26 90 0.150 402Ω −55 −60 −65 Optional 1.3kΩ Pull−Down Crosstalk (5dB/div) 0.200 dG/dP (%/degree) 1 dG 402Ω 0.125 dG 0.100 − 5V dP 0.075 0.050 dP −70 −75 −80 −85 −90 0.025 −95 0 −100 1 2 3 Number of 150ΩLoads 4 Input Referred 1 10 100 Frequency (MHz) 7 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE HARMONIC DISTORTION vs LOAD RESISTANCE −60 VO = 2VPP RL = 100Ω f = 5MHz VO = 2VPP f = 5MHz −65 −70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −60 2nd−Harmonic −75 3rd−Harmonic −80 −85 −65 2nd−Harmonic −70 3rd−Harmonic −75 −80 −90 100 2.0 1000 2.5 3.0 Resistance ( Ω ) Harmonic Distortion (dBc) Harmonic Distortion (dBc) −60 2nd−Harmonic −70 −80 3rd−Harmonic −90 5.5 6.0 2nd−Harmonic −65 −70 3rd−Harmonic −75 −80 0.1 1 10 0.1 20 1 5 Output Voltage Swing (VPP) Frequency (MHz) HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN −40 −40 VO = 2VPP RL = 100Ω f = 5MHz −50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 5.0 RL = 100Ω f = 5MHz −100 −60 2nd−Harmonic 3rd−Harmonic −70 −80 VO = 2VPP RL = 100Ω f = 5MHz −50 −60 2nd−Harmonic 3rd−Harmonic −70 −80 −90 1 10 Noninverting Gain (V/V) 8 4.5 −60 VO = 2VPP RL = 100Ω −50 4.0 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY −40 3.5 Supply Voltage (±VS ) 20 1 10 Inverting Gain (V/V) 20 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. 2−TONE, 3RD−ORDER INTERMODULATION SPURIOUS INPUT VOLTAGE AND CURRENT NOISE DENSITY −30 3rd−Order Spurious Level (dBc) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 100 10 Voltage Noise 5.5nV/√Hz Current Noise 3.1pA/√Hz 1 100 1k 10k 100k 1M −35 −45 −50 20MHz −55 −60 −65 10MHz −70 −75 10M 50MHz −40 Frequency (Hz) −8 −6 Load Power at Matched 50Ω Load, see Figure 1 −4 −2 0 2 4 RECOMMENDED R S vs CAPACITIVE LOAD 8 10 FREQUENCY RESPONSE vs CAPACITIVE LOAD 80 9 G = +2 Gain−to−Capacitive Load (dB) 70 60 50 RS ( Ω ) 6 Single−Tone Load Power (dBm) 40 30 20 10 CL = 10pF 6 CL = 100pF 3 CL = 22pF 0 CL = 47pF −3 V IN RS 1 /2 VOU T O PA 2 6 90 CL 1k Ω 402Ω −6 402 Ω 1kΩ is optional. −9 0 10 100 1000 0 20 40 Capacitive Load (pF) 0 2.0 Output Voltage Each Channel SO−14 Package Only 0.4 0 G = +2 VIN = +1V −45 −50 160 180 200 VDIS = 0 −60 −65 −70 −75 −80 −85 −90 −95 Time (50ns/div) 140 −55 Feedthrough (5dB/div) Output Voltage (0.4V/div) 2 VDIS (2V/div) 4 VDIS 0.8 100 120 DISABLE FEEDTHROUGH vs FREQUENCY 6 1.2 80 Frequency (20MHz/div) LARGE−SIGNAL DISABLE/ENABLE RESPONSE 1.6 60 −100 100k Reverse Forward 1M 10M 100M Frequency (Hz) 9 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OUTPUT VOLTAGE AND CURRENT LIMITATIONS TYPICAL DC DRIFT OVER TEMPERATURE 3 One Ch ann el Only VO (V) 1 0 25Ω Load Line −1 50Ω Load L ine −2 100 Ω Lo ad Line −3 −4 −5 −300 −200 −100 0 100 200 0.5 Input Offset Current (IOS) 0 −0.5 −1.0 −2.0 300 −20 −50 −25 0 25 50 75 100 125 Ambient Temperature (_C) COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 250 14 100 Sourcing Output Current Supply Current (2mA/div) −PSRR 80 CMRR 70 PSRR (dB) CMRR (dB) −10 Input Offset Voltage (VOS) IO (mA) 90 10 0 −1.5 1W Internal Pow er L im it Outp ut Curren t Lim it Input Bias Current (IB) 1.0 60 +PSRR 50 40 30 20 200 12 Sinking Output Current 150 10 Quiescent Supply Current 8 100 6 50 Output Current (50mA/div) 2 20 1.5 Input Offset Voltage (mV) 4 2.0 Ou tpu t Current L im ited 1 W In ternal P ower Limit Input Bias and Offset Currents (µA) 5 10 4 0 100k 1M 10M 100M −50 −25 25 50 CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY Open−Loop Gain (dB) Output Impedance ( Ω ) 1 /2 O PA2 69 0 ZO −5V 402Ω 402Ω 0.1 0 100k 1M Frequency (Hz) 10 10M 100M −30 Open−Loop Gain 50 Open−Loop Phase −60 40 −90 30 −120 20 −150 10 −180 0 −210 −10 −240 −20 0.01 10k 0 125 OPEN−LOOP GAIN AND PHASE 60 200Ω 100 70 +5V 1 75 Ambient Temperature (_C) Frequency (MHz) 10 0 1k 10k 100k 1M 10M Frequency (MHz) 100M −270 1G Open−Loop Phase (_) 10k "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. SMALL−SIGNAL FREQUENCY RESPONSE LARGE−SIGNAL FREQUENCY RESPONSE 6 9 VO = 2VPP G = +1 RF = 25Ω 3 6 G = +2 Gain (3dB/div) Normalized Gain (3dB/div) VO = 0.5VPP 0 G = +5 −3 VO = 3VPP 3 VO = 1VPP 0 G = +10 −6 −3 −9 −6 0.7 1 10 100 700 0.5 1 10 Frequency (Hz) SMALL−SIGNAL PULSE RESPONSE G = +2 VO = 0.5VPP 2.8 2.7 2.6 2.5 2.4 2.3 Output Voltage (400mV/div) 4.1 2.2 G = +2 VO = 2VPP 3.7 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 50 9 CL = 10pF Gain−to−Capacitive Load (dB) 45 40 35 RS ( Ω ) 500 LARGE−SIGNAL PULSE RESPONSE 2.9 Output Voltage (100mV/div) 100 Frequency (MHz) 30 25 20 15 10 5 6 CL = 100pF 3 0 +5V −3 VIN 0.1µF CL = 22pF 714Ω RS 1/2 58Ω 714Ω 714Ω VOUT O PA 2 69 0 CL −6 CL = 47pF 402Ω +5V 402Ω −9 0 1 10 100 Capacitive Load (pF) 1000 0 20 40 60 80 100 120 140 160 180 200 Frequency (20MHz/div) 11 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY −60 −40 Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2VPP f = 5MHz −65 −70 2nd−Harmonic 3rd−Harmonic −75 −80 1000 −60 2nd−Harmonic −70 −80 3rd−Harmonic −90 0.1 HARMONIC DISTORTION vs OUTPUT VOLTAGE 2−TONE, 3RD−ORDER INTERMODULATION SPURIOUS 20 −30 3rd−Order Spurious Level (dBc) 3rd−Harmonic −70 2nd−Harmonic −75 −80 0.1 10 Frequency (MHz) R L = 100Ωto 2.5V f = 5MHz −65 1 Resistance ( Ω ) −60 Harmonic Distortion (dBc) −50 −100 100 1 Output Voltage Swing (VPP) 12 VO = 2VPP RL = 100Ωto 2.5V 3 −35 50MHz −40 −45 −50 20MHz −55 −60 −65 10MHz −70 −75 Load Power at Matched 50Ω Load, see Figure 2 −14 −12 −10 −8 −6 −4 −2 Single−Tone Load Power (dBm) 0 2 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 The OPA2690 provides an exceptional combination of high output power capability in a dual, wideband, unity-gain stable, voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage-feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA2690 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This provides very high slew rate (1800V/µs) while consuming relatively low quiescent current (5.5mA/ch). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 5.5nV/√Hz input voltage noise for the OPA2690 is exceptionally low for this type of input stage. Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. This is for one channel; the other channel is connected similarly. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the electrical characteristics are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω 804Ω. The disable control line (SO-14 package only) is typically left open for normal amplifier operation. Two optional components are included in Figure 1. An additional resistor (175Ω) is included in series with the noninverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power-supply pins. In practical PC board layouts, this optional-added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA2690 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It will deliver a 3VPP output swing on a single +5V supply with > 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings +5V +VS 0.1µF 50Ω Source VI 6.8µF + 175Ω DIS VD 50Ω VO 1/2 OPA2690 0.1µF 50Ω 50Ω Load RF 402Ω RG 402Ω 6.8µF − VS 0.1µF −5V Figure 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit +5V +VS + WIDEBAND VOLTAGE-FEEDBACK OPERATION within the useable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698Ω resistors). Separate bias networks would be required at each input. The input signal is then AC-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (59Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. + APPLICATIONS INFORMATION 0.1µF 6.8µF 698Ω 0.1µF 50Ω DIS VD VI 698Ω 59Ω 1/2 OPA2690 VO 100Ω VS/2 RF 402Ω RG 402Ω 0.1µF Figure 2. DC-Coupled, G = +2, Single-Supply, Specification and Test Circuit 13 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 Again, an additional resistor (50Ω in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the DC source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies ( > 500MHz) using the input parasitic capacitance. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) on the output as well. The output voltage can swing to within 1V of either supply pin while delivering > 100mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA2690 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the +5V supply harmonic distortion plots. The OPA2690 in the circuit of Figure 4 provides > 200MHz bandwidth for a 2VPP output swing. Minimal 3rd-harmonic distortion or 2-tone, 3rd-order intermodulation distortion will be observed due to the very low crossover distortion in the OPA2690 output stage. The limit of output Spurious-Free Dynamic Range (SFDR) will be set by the 2nd-harmonic distortion. Without RB, the circuit of Figure 4 measured at 10MHz shows an SFDR of 57dBc. This can be improved by pulling additional DC bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5V for Figure 4). Adjusting IB gives the improvement in SFDR shown in Figure 3. SFDR improvement is achieved for IB values up to 5mA, with worse performance for higher values. Using the dual OPA2690 in an I/Q receiver channel will give matched AC performance through high frequencies. SINGLE-SUPPLY ADC INTERFACE 70 Most modern, high-performance ADCs (such as the TI ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA2690 make it an ideal single-supply ADC driver. The circuit on the front page shows one possible interface paricularly suited to differential I/O, AC-coupled requirements. Figure 4 shows the test circuit of Figure 2 modified for a capacitive (ADC) load and with an optional output pull-down resistor (RB). This circuit would be suitable to dual-channel ADC driving with a single-ended I/O. 68 V O = 2V PP , 10MHz 66 SFDR (dBc) 64 62 60 58 56 54 52 50 0 1 2 3 4 5 6 7 Output Pull−Down Current (mA) Figure 3. SFDR versus IB +5V Power−supply decoupling not shown. 698Ω 0.1µF 50Ω VI RS 30Ω 1 /2 1VPP 59Ω 698Ω 50pF 402Ω 402Ω 0.1µF RB IB Figure 4. SFDR versus IB 14 2.5V DC ± 1V AC O PA 269 0 ADC Input 8 9 10 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER 50Ω 1/2 OPA2690 High-frequency DDS Digital-to-Analog Converters (DACs) require a low distortion output amplifier to retain their SFDR performance into real-world loads. Figure 5 shows a single-ended output drive implementation. The diagram shows the signal output current(s) connected into the virtual ground summing junction(s) of the OPA2690, which is set up as a transimpedance stage or I-V converter. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA2690. The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD in Figure 5) will produce a zero in the noise gain for the OPA2690 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to: 1 + 2pR FCF GBP Ǹ4pR C F High−Speed DAC GBP Ǹ2pR C F CF2 −IO CD2 1/2 −VO = −I O R F OPA2690 50Ω GBP →Gain Bandwidth Product (Hz) for the OPA2690 Figure 5. DAC Transimpedance Amplifier WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OP2690I-14D (SO-14 package only), as shown in Figure 6. (2) D CD1 R F2 which will give a cutoff frequency f−3dB of approximately: f *3dB + R F1 CF1 IO (1) D VO = IO RF +5V 2kΩ VDIS +5V 146Ω DISA Video 1 1 /2 75Ω O PA 2 690 340Ω 402Ω −5V 82.5Ω 75Ω Cable 340Ω 402Ω RG−59 75Ω Load +5V 82.5Ω 1 /2 146Ω Video 2 O PA 2 690 DISB 75Ω 2kΩ −5V Figure 6. 2-Channel Video Multiplexer (SO-14 package only) 15 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The make-before-break disable characteristic of the OPA2690 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 6. As both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (see Figure 6) also ensures that the maximum differential voltage across the inputs of the unselected channel does not exceed the rated ±1.2V maximum for standard video signal levels. See the Disable Operation section for the turn-on and turn-off switching glitches using a 0V input for a single channel is typically less than ±50mV. Where two outputs are switched (see Figure 6), the output line is always under the control of one amplifier or the other due to the make-before-break disable timing. In this case, the switching glitches for two 0V inputs drops to < 20mV. HIGH-SPEED DELAY CIRCUIT The OPA2690 makes an ideal amplifier for a variety of active filter designs. Shown in Figure 7 is a circuit that uses the two amplifiers within the dual OPA2690 to design a 2-stage analog delay circuit. For simplicity, the circuit uses a dual-supply (±5V) operation, but it can also be modified to operate on a signal supply. The input to the first filter stage is driven by the OPA692 wideband buffer amplifier to isolate the signal input from the filter network. For a more accurate analysis of the circuit, consider the group delay for the amplifiers. For example, in the case of the OPA2690, the group delay in the bandwidth from 1MHz to 100MHz is approximately 1.0ns. To account for this, modify the transfer function, which now comes out to be: t GR + 2 (2RC ) T D) (4) with TD = (1/360) × (dφ/df) = delay of the op amp itself. The values of resistors RF and RG should be equal and low to avoid parasitic effects. If the all-pass filter is designed for very low delay times, include parasitic board capacitances to calculate the correct delay time. Simulating this application using the PSPICE model of the OPA2690 will allow this design to be tuned to the desired performance. DIFFERENTIAL RECEIVER/DRIVER A very versatile application for a dual operational amplifier is the differential amplifier configuration detailed in Figure 8. With both amplifiers of the OPA2690 connected for noninverting operation, the circuit provides a high input impedance whereas the gain can easily be set by just one resistor, RG. When operated in low gains, the output swing may be limited as a result of the common-mode input swing limits of the amplifier itself. An interesting modification of this circuit is to place a capacitor in series with the RG. Now the DC gain for each side is reduced to +1, whereas the AC gain still follows the standard transfer function of G = 1 + 2RF/RG. This might be advantageous for applications processing only a frequency band that excludes DC or very low frequencies. An input DC voltage resulting from input bias currents is not amplified by the AC gain and can be kept low. This circuit can be used as a differential line receiver, driver, or as an interface to a differential input ADC. Each of the two filter stages is a 1st-order filter with a voltage gain of +1. The delay time through one filter is given by Equation 3. t GR0 + 2RC (3) C VIN OPA692 C 1/2 OP A26 90 1/2 OPA 269 0 R R RG 402Ω RF 402Ω RG 402Ω Figure 7. 2-Stage, All-Pass Network 16 RF 402Ω V OUT "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 SINGLE-SUPPLY MFB DIFFERENTIAL ACTIVE FILTER: 10MHz BUTTERWORTH CONFIGURATION 50Ω VI 1 /2 O P A2 6 9 0 RO The active filter circuit shown in Figure 9 can be easily implemented using the OPA2690. In this configuration, each amplifier of the OPA2690 operates as an integrator. For this reason, this type of application is also called infinite gain filter implementation. A Butterworth filter can be implemented using the following component ratios: RF 402Ω RG VDIFF = 1 + RF 402Ω 2RF RG VI − (−VI) 1 2 p R R 1 + R2 + 0.65 fO + 50Ω −VI 1 /2 O P A2 6 9 0 RO R 3 + 0.375 (cutoff frequency) C R R C1 + C C2 + 2 Figure 8. High-Speed Differential Receiver C +12V 6kΩ 50Ω VCM 1 /2 OP A 2 6 90 1000pF 6kΩ C1A 100pF R3A 60Ω R1A 102Ω R2A 102Ω C2 200pF VIN R2B 102Ω R1B 102Ω R3B 60Ω VOUT C1B 100pF 1 /2 50Ω OP A 2 6 90 VCM Figure 9. Single-Supply, MFB Active Filter, 10MHz LP Butterworth 17 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 1 0 −1 6 3 CF = 8.6pF 0 −3 −6 −9 −2 Gain (dB) 9 Differential Gain (dB) The frequency response for a 10MHz Butterworth filter is shown in Figure 10. One advantage for using this type of filter is the independent setting of WO and Q. Q can be easily adjusted by changing the R3A, B resistors without affecting WO. −3 −12 −4 0.1 1 −5 10 100 500 Frequency (MHz) −6 −7 Figure 11. Single-Supply Differential ADC Driver −8 −9 0.1 1 10 20 Frequency (MHz) Figure 10. Multiple Feedback Filter Frequency Response The single-supply differential ADC driver shown on the front page is ideal for driving high-frequency ADCs. As shown in the plot on the front page, Harmonic Distortion vs Frequency for the Single-Supply Differential ADC Driver, the 2nd-harmonic reacts as expected and drops to a −95dBc at 1MHz and −87dBc at 5MHz—a significant improvement in going to differential from single-ended. The circuit shown on the front page has a 195MHz, −3dB bandwidth that can be easily bandlimited by using a capacitor in parallel with the feedback resistors. Refer to Figure 11 for more details. The −3dB frequency is given by Equation 5. 18 1 2pRFC F DESIGN-IN TOOLS DEMONSTRATION BOARDS SINGLE-SUPPLY DIFFERENTIAL ADC DRIVER f *3dB + For example, CF = 8.6pF in parallel with RF = 402Ω will control the −3dB frequency to 18MHz. (5) Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA2690 in its two package styles. Both of these are available, free, as unpopulated PC boards delivered with descriptive documentation. The summary information for each board is shown below: PRODUCT PACKAGE BOARD PART NUMBER OPA2690ID OPA2690IDBV SO-8 SO-14 DEM-OPA268xU DEM-OPA268xN LITERATURE REQUEST NUMBER SBOU003 SBOU002 Consult the Texas Instruments web site (www.ti.com) to request either of these boards. "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 MACROMODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2690 (use two OPA690 SPICE models) is available through the Texas Instruments web page (http://www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES As the OPA2690 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA2690. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor can cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 1) to be less than approximately 300Ω. The combined impedance RF RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF RG < 300Ω will keep this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. BANDWIDTH vs GAIN: NONINVERTING OPERATION Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA2690 is compensated to give a slightly peaked response in a noninverting gain of 2 (see Figure 1). This results in a typical gain of +2 bandwidth of 220MHz, far exceeding that predicted by dividing the 300MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 300MHz. The frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the +2 signal gain, is to add an 804Ω resistor across the two inputs in the circuit of Figure 1. A similar technique may be used to reduce peaking in unity-gain (voltage follower) applications. For example, by using a 402Ω feedback resistor along with a 402Ω resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of Figure 2. Reducing the value of the resistor across the op amp inputs will further limit the frequency response due to increased noise gain. The OPA2690 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared with ±5V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. INVERTING AMPLIFIER OPERATION Since the OPA2690 is a general-purpose, wideband voltage-feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. See Figure 12 for a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration. In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PC board trace, or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of −2, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω 19 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the noninverting circuits considered in the previous section. The amplifier output, however, will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values (see Figure 8), and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. +5V + 0.1µF 6.8µF 0.1µF VO 1 /2 RB 146Ω 50Ω Source RO 50Ω O PA 269 0 50Ω Load VO = −2 VI RF 402Ω RG 200Ω VI RM 67Ω 0.1µF + 6.8µF − 5V Figure 12. Gain of −2 Example Circuit The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 12, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω 67Ω = 28.6Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.8 for Figure 12, as opposed to only 2 if RM could be eliminated as discussed above. The bandwidth will therefore be slightly lower for the gain of −2 circuit of Figure 12 than for the gain of +2 circuit of Figure 1. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to (Input Offset Current) × RF. If the 50Ω source impedance is DC-coupled in Figure 10, the total resistance to ground on the inverting input will be 228Ω. 20 Combining this in parallel with the feedback resistor gives the RB = 146Ω used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350Ω, the capacitor is not required because the total noise contribution of all other terms will be less than that of the op amp input noise voltage. As a minimum, the OPA2690 requires an RB value of 50Ω to damp out parasitic-induced peaking—a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. OUTPUT CURRENT AND VOLTAGE The OPA2690 provides exceptional output voltage and current capabilities in a low-cost monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1V to either supply rail; the specified swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it will deliver more than ±160mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2690 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation for each channel separately. Superimposing resistor load lines onto the plot shows that the OPA2690 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability (see the Electrical Characteristics). The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the over-temperature specifications because the output stage junction temperatures will be higher than the minimum specified operating ambient. To protect the output stage from accidental shorts to ground and the power supplies, output short-circuit protection is included in the OPA2690. The circuit acts to limit the maximum source or sink current to approximately 250mA. "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 DRIVING CAPACITIVE LOADS The Typical Characteristics show the recommended RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2690. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2690 output pin (see the Board Layout Guidelines section). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA2690 operating in a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will reduce the peaking as described previously. The circuit of Figure 13 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load. +5V 50Ω 175Ω 50Ω Power−supply decoupling not shown. R RNG 1/2 OP A26 90 VO C LOAD 402Ω 402Ω − 5V Figure 13. Capacitive Load Driving with Noise Gain Tuning This gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique will reduce the required RS resistor for a given capacitive load, it does increase the noise at the output. It also will decrease the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 14 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 13 with RNG adjusted to increase the noise gain (increasing the phase margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA2690 operated at higher signal gains without RNG. 100 90 80 70 RS ( Ω ) One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA2690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the open-loop output resistance of the amplifier is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. NG = 2 60 50 40 30 20 NG = 3 10 NG = 4 0 1 10 100 1000 Capacitive Load (pF) Figure 14. Required RS vs Noise Gain 21 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 DISTORTION PERFORMANCE The OPA2690 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 1), this is sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply-decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). Operating differentially also lowers 2nd-harmonic distortion terms (see the plot on the front page). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The new output stage used in the OPA2690 actually holds the difference between fundamental power and the 2nd- and 3rd-harmonic powers relatively constant with increasing output power until very large output swings are required ( > 4VPP). This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2VPP for each tone at the load, which requires 8VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show 46dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This exceptional performance improves further when operating at lower frequencies or powers. NOISE PERFORMANCE High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 5.5nV/√Hz input voltage noise for the OPA2690 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 15 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. 22 ENI 1/2 OPA2690 RS EO IBN ERS RF √ 4kTR S RG 4kT RG √ 4kTRF I BI 4kT = 1.6E − 20J at 290_K Figure 15. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 6 shows the general form for the output noise voltage using the terms shown in Figure 15. EO + Ǹǒ Ǔ E NI ) ǒI BNRSǓ ) 4kTRS NG 2 ) ǒI BIR FǓ ) 4kTRFNG 2 2 2 (6) Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 7. EN + Ǹ ENI ) ǒIBNR SǓ ) 4kTRS ) 2 2 ǒ Ǔ IBIRF NG 2 ) 4kTRF NG (7) Evaluating these two equations for the OPA2690 circuit and component values (see Figure 1) gives a total output spot noise voltage of 12.3nV/√Hz and a total equivalent input spot noise voltage of 6.1nV/√Hz. This is including the noise added by the bias current cancellation resistor (175Ω) on the noninverting input. This total input-referred spot noise voltage is only slightly higher than the 5.5nV/√Hz specification for the op amp voltage noise alone. This will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300Ω. Keeping both (RF RG) and the noninverting input source impedance less than 300Ω will satisfy both noise and frequency response flatness considerations. As the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 12 is not required. "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide variety of applications. The power-supply current trim for the OPA2690 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically 5µA out of each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, and using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: ±(NG × VOS(MAX)) ± (RF × IOS(MAX)) = ±(2 × 4.5mV) ± (402Ω × 1µA) = ±9.4mV − (NG = noninverting signal gain) A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the DC offset voltage on the summing junction will set up a DC current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 16 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This ensures that the adjustment circuit has minimal effect on the loop gain and hence, the frequency response. +5V Power−supply decoupling not shown. 0.1µF 328Ω 1/2 OPA2690 VO −5V RG 500Ω +5V 5kΩ RF 1kΩ VI 20kΩ ±200mV Output Adjustment 10kΩ 0.1µF VO 5kΩ VI =− RF RG = −2 −5V Figure 16. DC-Coupled, Inverting Gain of −2, with Offset Adjustment DISABLE OPERATION (SO-14 Package Only) The OPA2690I-14D provides an optional disable feature that can be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2690I-14D will operate normally. To disable, the control pin must be asserted LOW. Figure 17 shows a simplified internal circuit for the disable control feature. +VS 15kΩ Q1 25kΩ VDIS 110kΩ IS Control −VS Figure 17. Simplified Disable Control Circuit 23 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 In normal operation, base current to Q1 is provided through the 110kΩ resistor, while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled LOW, additional current is pulled through the 15kΩ resistor, eventually turning on those two diodes (≈100µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 17. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high-impedance state. If the OPA2690 is operating at a gain of +1, this will show a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 18 shows these glitches for the circuit of Figure 1 with the input signal at 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. 6 4 VDIS 2 Output Voltage (10mV/div) 0 30 20 10 Output Voltage VO = 0 0 −10 −20 −30 Time (20ns/div) Figure 18. Disable/Enable Glitch 24 VDIS (2V/div) The transition edge rate (dv/dt) of the DIS control line will influence this glitch. For the plot of Figure 18, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin provides adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing. THERMAL ANALYSIS Due to the high output power capability of the OPA2690, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2690ID (SO-8 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and with both outputs driving a grounded 20Ω load to +2.5V. PD = 10V × 12.6mA + 2 [52/(4 × (20Ω || 804Ω))] = 766mW Maximum TJ = +85°C + (0.766W × 125°C/W) = 180°C. This absolute worst-case condition exceeds the specified maximum junction temperature. Actual PDL is normally less than that considered here. Carefully consider maximum TJ in your application. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA2690 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA2690. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402Ω feedback used in the Electrical Characteristics is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for the unity-gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause an additional peaking in the gain of +1 frequency response. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 3pF) may not need an RS because the OPA2690 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin, see Figure 14). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2690 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2690 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2690 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2690 onto the board. 25 "#$% www.ti.com SBOS238D − JUNE 2002 − REVISED DECEMBER 2004 INPUT AND ESD PROTECTION The OPA2690 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 19. +VCC External Pin Internal Circuitry −VCC Figure 19. Internal ESD Protection 26 These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA2690), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA2690I-14D ACTIVE SOIC D 14 58 None CU NIPDAU Level-3-235C-168 HR OPA2690I-14DR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-3-235C-168 HR OPA2690ID ACTIVE SOIC D 8 100 None CU NIPDAU Level-3-235C-168 HR OPA2690IDR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-3-235C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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