HANBIT HMD4M32M8GL-6

HANBit
HMD4M32M8GL
16Mbyte(4Mx32) Fast Page Mode, 4K Refresh 72Pin SIMM
Part No. HMD4M32M8GL
GENERAL DESCRIPTION
The HMD4M32M8GL is a 4M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board.
A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
PIN ASSIGNMENT
w Part Identification
HMD4M32M8GL- 4,096 Cycles/64ms Ref . Gold
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
w High-density 16MByte design
1
Vss
25
DQ22
49
DQ8
w Single + 5V ±0.5V power supply
2
DQ0
26
DQ7
50
DQ24
w JEDEC standard pinout
3
DQ16
27
DQ23
51
DQ9
4
DQ1
28
A8
52
DQ25
5
DQ17
29
A10
53
DQ10
6
DQ2
30
Vcc
54
DQ26
7
DQ18
31
/WE2
55
DQ11
8
DQ3
32
NC
56
DQ27
9
DQ19
33
Vss
57
DQ12
10
Vcc
34
/RAS
58
DQ28
11
/WE0
35
Vcc
59
/WE3
12
A0
36
NC
60
DQ29
13
A1
37
NC
61
DQ13
14
A2
38
/OE0
62
DQ30
15
A3
39
Vss
63
DQ14
16
A4
40
/CAS
64
DQ31
17
A5
41
Vcc
65
DQ15
18
A6
42
NC
66
Vss
19
A7
43
NC
67
NC
20
DQ4
44
NC
68
NC
21
DQ20
45
A9
69
BDIN
w Access times : 50, 60ns
w FP(Fast Page) mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
-5
60ns access
-6
w Packages
72-pin SIMM
M
PIN CONFIGURATION DESCRIPTION
Pin Name
FUNCTION
A0 – A11
Address Input(4K Ref.)
A0 – A10
Address Input(2K Ref.)
DQ0-31
Data In/Out
/WE0-/WE3
Read/Write Input
/OE
Data Output Enable
/CAS
Column Address Strobe
/RAS
Row Address Strobe
BDIN
Board Insertion Signal
SIZE
Size Indentification
22
DQ5
46
A11
70
NC
Vcc/ Vss
Power and Ground
23
DQ21
47
/WE1
71
SIZE
NC
No Connection
24
DQ6
48
Vcc
72
Vss
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REV.1.0. (August. 2002)
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HANBit
HMD4M32M8GL
FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ3
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ4-DQ7
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ8-DQ11
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
DQ12-DQ15
U2
CAS
RAS
W
OE
U3
CAS
RAS
W
OE
/WE1
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U1
CAS
RAS
W
OE
/CAS
/RAS
/WE0
U4
CAS
RAS
W
OE
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U5
CAS
RAS
W
OE
DQ16-DQ19
/WE2
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U6
CAS
RAS
OE
W
CAS
RAS
W
OE
DQ20-DQ23
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U7
DQ24-DQ27
/WE3
DQ0
DQ1
DQ2
A0-A10(A11) DQ3
U8
CAS
RAS
W
OE
DQ28-DQ31
/OE
A0-A10(A11)
Vcc
Vss
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REV.1.0. (August. 2002)
0.1uF
or
Capacitor
for each DRAM
2
0.22uF
To all DRAMs
HANBit Electronics Co.,Ltd.
HANBit
HMD4M32M8GL
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 7.0V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 7.0V
Power Dissipation
PD
8W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
ICC1
-5
-
720
mA
-6
-
640
mA
-
16
mA
-5
-
720
mA
-6
-
640
mA
-5
-
640
mA
-6
-
560
mA
-
8
mA
-5
-
720
mA
-6
-
640
mA
Il(L)
-40
40
µA
IO(L)
-40
40
µA
VOH
2.4
-
V
VOL
-
0.4
V
ICC2
ICC3
ICC4
ICC5
ICC6
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)
ICC2 : Standby Current ( /RAS=/CAS=VIH )
ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
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HMD4M32M8GL
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V
VOH : Output High Voltage Level (IOH= -5mA )
VOL : Output Low Voltage Level (IOL = 4.2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
o
( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A11)
CIN1
-
40
pF
Input Capacitance (/WE0-/WE3)
C IN2
-
49
pF
Input Capacitance (/RAS)
CIN3
-
49
pF
Input Capacitance (/CAS)
CIN4
-
49
pF
Input/Output Capacitance (DQ0-31)
CDQ1
-
49
pF
AC CHARACTERISTICS
o
( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.)
-5
STANDARD OPERATION
-6
SYMBOL
UNIT
MIN
MAX
MAX
Random read or write cycle time
tRC
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
13
15
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
0
Output buffer turn-off delay
tOFF
0
13
0
15
ns
Transition time (rise and fall)
tT
3
50
3
50
ns
/RAS precharge time
tRP
30
/RAS pulse width
tRAS
50
/RAS hold time
tRSH
13
15
ns
/CAS hold time
tCSH
50
60
ns
/CAS pulse width
tCAS
13
10K
15
10K
ns
/RAS to /CAS delay time
tRCD
20
37
20
45
ns
/RAS to column address delay time
tRAD
15
25
15
30
ns
/CAS to /RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
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REV.1.0. (August. 2002)
4
90
MIN
110
ns
0
ns
40
10K
60
ns
10K
ns
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HANBit
HMD4M32M8GL
Column address hold time
tCAH
10
10
ns
Column address hold referenced to /RAS
tAR
40
45
ns
Column Address to /RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
40
45
ns
Write command pulse width
tWP
10
10
ns
Write command to /RAS lead time
tRWL
15
15
ns
Write command to /CAS lead time
tCWL
13
15
ns
Data-in set-up time
tDS
0
0
ns
Data-in hold time
tDH
10
15
ns
Data-in hold referenced to /RAS
tDHR
40
45
ns
Refresh period 2K Ref.
tREF
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
Fast page mode cycle time
tPC
35
40
ns
/CAS precharge time (Fast page)
tCP
10
10
ns
/RAS pulse width (Fast page )
tRASP
50
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
/CAS precharge(C-B-R counter test)
tCPT
20
20
ns
32
32
30
200K
35
60
200K
ns
ns
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write
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REV.1.0. (August. 2002)
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HMD4M32M8GL
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
TIMING DIAGRAM
Please refer to attached timing diagram chart (I)
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REV.1.0. (August. 2002)
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URL: www.hbe.co.kr
REV.1.0. (August. 2002)
HMD4M32M8GL
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REV.1.0. (August. 2002)
HMD4M32M8GL
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HMD4M32M8GL
PACKAGING INFORMATION
SIMM Design
3.38± 0.2mm
25.4 ± 0.2mm
6.35± 0.2mm
6.35± 0.2mm
6.35± 0.2mm
95.25± 0.2mm
2.54 mm MIN
0.25 mm MAX
1.27
1.27±0.08m
Gold : 1.04±0.10 mm
Solder:0.914±0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMD4M32M8GL-5
16MByte
4MX 32bit
72 Pin-SIMM
HMD4M32M8GL-6
16MByte
4MX 32bit
72 Pin-SIMM
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REV.1.0. (August. 2002)
9
Refresh
Cycle
4K Cycles
64ms Ref.
4K Cycles
64ms Ref.
Vcc
SPEED
5.0V
50ns
5.0V
60ns
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