HANBit HSD32M72D18P Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V Part No. HSD32M72D18P (Unbuffered) GENERAL DESCRIPTION The HSD32M72D18P is a 32M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M72D18P is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES • Part Identification HSD32M72D18P-F/10L : 100MHz (CL=3) HSD32M72D18P-F/10 : 100MHz (CL=2) HSD32M72D18P-F/12 : 125MHz (CL=3) HSD32M72D18P-F/13 : 133MHz (CL=3) F means Auto & Self refresh with Low-Power (3.3V) • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • The used device is 8M x 8bit , 4Banks SDRAM URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -1- HANBit HSD32M72D18P PIN ASSIGNMENT PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 Vss 29 DQM1 57 DQ18 85 Vss 113 DQM5 141 DQ50 2 DQ0 30 /CE0 58 DQ19 86 DQ32 114 /CE1 142 DQ51 3 DQ1 31 NC 59 Vcc 87 DQ33 115 /RAS 143 Vcc 4 DQ2 32 Vss 60 DQ20 88 DQ34 116 Vss 144 DQ52 5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC 6 Vcc 34 A2 62 NC 90 Vcc 118 A3 146 NC 7 DQ4 35 A4 63 CKE1 91 DQ36 119 A5 147 NC 8 DQ5 36 A6 64 Vss 92 DQ37 120 A7 148 Vss 9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53 10 DQ7 38 A10 66 DQ22 94 DQ39 122 BA0 150 DQ54 11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55 12 Vss 40 Vcc 68 Vss 96 Vss 124 Vcc 152 Vss 13 DQ9 41 Vcc 69 DQ24 97 DQ41 125 CLK1 153 DQ56 14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 NC 154 DQ57 15 DQ11 43 Vss 71 DQ26 99 DQ43 127 Vss 155 DQ58 16 DQ12 44 NC 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 /CE2 73 Vcc 101 DQ45 129 /CE3 157 Vcc 18 Vcc 46 DQM2 74 DQ28 102 Vcc 130 DQM6 158 DQ60 19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61 20 DQ15 48 NC 76 DQ30 104 DQ47 132 NC 160 DQ62 21 CB0 49 Vcc 77 DQ31 105 CB4 133 Vcc 161 DQ63 22 CB1 50 NC 78 Vss 106 CB5 134 NC 162 Vss 23 Vss 51 NC 79 CLK2 107 Vss 135 NC 163 CLK3 24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC 25 NC 53 CB3 81 WP 109 NC 137 CB7 165 SA0 26 Vcc 54 Vss 82 SDA 110 Vcc 138 Vss 166 SA1 27 /WE 55 DQ16 83 SCL 111 /CAS 139 DQ48 167 SA2 28 DQM0 56 DQ17 84 Vcc 112 DQM4 140 DQ49 168 Vcc * These pins are not used in this module ** These pins should be NC in the system which does not support SPD *Pin Names VREF : Power supply for reference CB0~7 : Check bit (Data in/data-out) CLK0 ~ CLK3 : Clock input CKE0 ~ CKE1 : Colck enable input /CE0 ~ /CE3 : Chip enable input Vcc : Power supply Vss : Ground SDA : Serial data I/O SCL : Serial clock SA0 ~ 2 : Address in EEPROM URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -2- HANBit HSD32M72D18P FUNCTIONAL BLOCK DIAGRAM URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -3- HANBit HSD32M72D18P PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS /WE Column address Latches column addresses on the positive going edge of the CLK with CAS low. strobe Enables column access. Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output Makes data output Hi-Z, tSHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. Vcc/Vss Power Power and ground for the input buffers and the core logic. supply/ground ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 18W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -4- HANBit HSD32M72D18P DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS CCLK 18 25 pF CIN 50 95 pF Address CADD 50 95 pF DQ (DQ0 ~ DQ7) COUT 13 18 pF Clock /RAS, /CAS,/WE,/CE, CKE, DQM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) TEST PARAMETER VERSION NOT SYMBOL UNIT CONDITION -13 -12 -10 2160 2160 1980 E 10L Burst length = 1 Operating current (One bank active) ICC1 198 tRC ≥ tRC(min) mA 0 IO = 0mA Precharge standby current ICC2P in power-down mode ICC2PS 18 mA 18 mA 360 mA tCC=10ns CKE & CLK ≤ VIL(max) tCC=∞ CKE ≥ VIH(min) Precharge standby current in CKE ≤ VIL(max) ICC2N CS* ≥ VIH(min), tCC=10ns Input signals are changed non power-down mode one time during 20ns URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -5- 1 HANBit HSD32M72D18P CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tCC=∞ 126 Input signals are stable Active standby current in power-down mode CKE ≤ VIL(max), tCC=10ns ICC3P 90 CKE&CLK ≤ VIL(max) ICC3PS mA 90 tCC=∞ CKE≥VIH(min), Active standby current in CS*≥VIH(min), ICC3N tCC=10ns 540 Input signals are changed non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) ICC3NS CLK ≤VIL(max), mA tCC=∞ 360 Input signals are stable IO = 0 mA Operating current ICC4 (Burst mode) Page burst 270 4Banks Activated 0 2610 2250 2250 mA 1 3960 3780 3780 mA 2 tCCD = 2CLKs Refresh current tRC ≥ tRC(min) ICC5 Self refresh current 396 0 CKE ≤ 0.2V ICC6 27 mA 14.4 mA Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 Vtt=1.4V +3.3V 1200Ω DOUT 870Ω URL: www.hbe.co.kr REV.1.0 (Augsut.2002) 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA -6- 50Ω DOUT Z0=50Ω 50pF HANBit Electronics Co.,Ltd. HANBit HSD32M72D18P (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) Row cycle time 100 tRC(min) 65 ns 68 70 70 ns 1 2 Last data in to row precharge tRDL(min) 2 CLK Last data in to Active delay tDAL(min) 2 CLK + 20 ns - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) SYMBO -13 -12 -10 -10L PARAMETER L CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 URL: www.hbe.co.kr REV.1.0 (Augsut.2002) MIN MAX 7.5 tCC MIN MAX 8 1000 - MIN MAX 10 1000 - MIN UNIT NOTE ns 1 ns 1,2 ns 2 MAX 10 1000 10 1000 12 5.4 6 6 6 - - 6 7 tSAC 2.7 3 3 3 - - 3 3 tOH HANBit Electronics Co.,Ltd. -7- HANBit HSD32M72D18P CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z CAS CLK to output latency=3 CAS in Hi-Z latency=2 tSLZ 1 1 1 1 ns 3 2 5.4 6 6 6 ns - - 6 7 ns tSHZ Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND Register Mode register set Auto refresh Refresh Entry Self refresh Exit Bank active & row addr. Auto precharge Read & disable column Auto precharge address disable Write & column address Auto precharge disable /C E /R A S /C A S /W E D Q M H X L L L L X OP code L L L H X X X X H H L L H L H H H H X X X BA 0,1 H X L L H H X V H X L H L H X V Bank selection All banks Entry A11 A9~A0 H 1,2 3 3 3 3 Row address Column 4 Address H (A0 ~ A9) L Address X L H L L X V 4,5 H H X X L L H Entry H L L DQM H No operation command H H L L H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X H X X X L H H H X X X 4,5 X V L X H 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : HANBit Electronics Co.,Ltd. -8- 4 (A0 ~ A9) H power URL: www.hbe.co.kr REV.1.0 (Augsut.2002) NOTE Column Exit Exit A10/ AP L H Clock suspend or active power down Precharge down mode CKE n Auto precharge disable Burst Stop Precharg e CKE n-1 7 HANBit HSD32M72D18P 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) PACKAGING INFORMATION Unit : inch [mm] 1.125 [28.58] PCB : 1.27 ±0.008 [ ±0.20 ] URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. -9- HANBit HSD32M72D18P ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc HSD32M72D18P-13 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-12 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-10L 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-10 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-F13 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-F12 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V HSD32M72D18P-F10L HSD32M72D18P-F10 256MByte 256MByte 32M x 72 32M x 72 168 Pin-DIMM 168 Pin-DIMM 4K 4K 3.3V 3.3V MODE MAX.frq ECC/ CL3 Unbuffered 133MHz ECC/ CL3 Unbuffered 125MHz ECC/ CL3 Unbuffered 100MHz ECC/ CL2 Unbuffered 100MHz ECC/ CL3 Unbuffered 133MHz ECC/ CL3 Unbuffered 125MHz ECC/ CL3 Unbuffered 100MHz ECC/ CL2 Unbuffered 100MHz F means Auto & Self refresh with Low-Power (3.3V) URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HANBit Electronics Co.,Ltd. - 10 - HANBit URL: www.hbe.co.kr REV.1.0 (Augsut.2002) HSD32M72D18P HANBit Electronics Co.,Ltd. - 11 -