HANBIT HSD64M64F8KA-10L

HANBit
HSD64M64F8KA
Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on
32Mx8 ,4Banks, 4K Ref., 3.3V
Part No. HSD64M64F8KA
GENERAL DESCRIPTION
The HSD64M64F8KA is a 64M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists
of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 120-pin glass-epoxy.
One 0.22uF and two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.
The HSD64M64F8KA is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory
system applications All module components may be powered from a single 3.3V DC power supply and all inputs and
outputs are LVTTL-compatible.
FEATURES
PIN ASSIGNMENT
• Part Identification
60-PIN P1 Connector
HSD64M64F8KA – 10L : 100MHz (CL=3)
60-PIN P2 Connector
HSD64M64F8KA – 10 : 100MHz (CL=2)
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
HSD64M64F8KA – 13 : 133MHz (CL=3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
DQM4
DQM5
NC
CKE0
CKE1
Vcc
NC
NC
/CS1
/CS2
Vcc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQM0
DQM1
/WE
CLK0
CLK1
Vss
/CAS
/RAS
/CS1
/CS2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQM2
DQM3
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vss
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vcc
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vcc
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vcc
DQM6
DQM7
A12
A11
A9
A8
A7
A6
A5
A4
Vcc
• Burst mode operation
• Auto & self refresh capability (8192Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going
edge of the system clock
• The used device is stacked 8M x 8bit x 4Banks
SDRAM
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
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HANBit Electronics Co.,Ltd.
HANBit
HSD64M64F8KA
FUNCTIONAL BLOCK DIAGRAM
Stacking 의
상 위
부분 위 치
* /CS0 + /CS2(b'd) = /CS1(Module), /CS1 + /CS3(b'd) = /CS2(Module)
** Address (0:12), /RAS, /CAS, /WE, BA(0:1), CLK, CKE0
U0~U15
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REV. 1.0 (August, 2002)
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HSD64M64F8KA
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
/CS
Chip enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
/WE
Column address
Latches column addresses on the positive going edge of the CLK with /CAS low.
strobe
Enables column access.
Write enable
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
Data input/output
Makes data output Hi-Z, tsHZ after the clock and masks the output.
mask
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Vcc/Vss
Power supply/ground
Power and ground for the input buffers and the core logic.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 4.6V
Power Dissipation
PD
16W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
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HSD64M64F8KA
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Supply Voltage
Vcc
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
Vcc+0.3
V
1
Input Low Voltage
VIL
-0.3
0
0.8
V
2
Output High Voltage
VOH
2.4
-
-
V
IOH = -2mA
Output Low Voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
I LI
-10
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
3
CAPACITANCE
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A11)
CIN1
40
80
pF
Input capacitance(/RAS, /CAS,/WE)
CIN2
40
80
pF
Input capacitance(CKE0)
CIN3
40
80
pF
Input capacitance(CLK0)
CIN4
40
64
pF
Input capacitance(/CS0~/CS3)
CIN5
40
80
pF
Input capacitance(DQM0~DQM7)
CIN3
40
64
pF
Input capacitance(BA0~BA1)
CIN3
40
64
pF
Data input/output capacitance (DQ0 ~ DQ63)
COUT
64
104
pF
(Vcc = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
PARAMETER
VERSION
UNIT
CONDITION
ICC1
Burst length = 1
tRC ≥ tRC(min) IO = 0mA
ICC2P
CKE ≤ VIL(max) tCC=10ns
Operating current
(One bank active)
Precharge standby
current in
power-down mode
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
NOT
SYMBOL
ICC2PS
CKE & CLK ≤ VIL(max)
-10
-10L
-13
720
720
800
E
mA
1
16
mA
3
16
mA
3
tCC=∞
4
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HSD64M64F8KA
CKE ≥ VIH(min)
ICC2N
Precharge standby
/CS ≥ VIH(min),
tcc=10ns
320
Input signals are changed
current in
one time during 20ns
non power-down mode
CKE ≥ VIH(min)
ICC2NS
CLK ≤ VIL(max),
tcc=∞
mA
3
mA
3
mA
3
112
Input signals are stable
Active standby current in
ICC3P
CKE ≤ VIL(max), tcc=10ns
80
power-down mode
ICC3PS
CKE&CLK ≤ VIL(max) tcc=∞
80
CKE≥VIH(min),
Active standby current in
ICC3N
/CS≥VIH(min),
tcc=10ns
480
Input signals are changed
non power-down mode
one time during 20ns
(One bank active)
CKE≥VIH(min)
ICC3NS
CLK ≤VIL(max),
tcc=∞
320
Input signals are stable
IO = 0 mA Page burst
Operating current
ICC4
(Burst mode)
4Banks Activated
800
800
880
mA
1
1520
1520
1600
mA
2
mA
3
tCCD = 2CLKs
Refresh current
ICC5
Self refresh current
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
24
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1PLL & 3 Drive Ics.
4. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
Value
UNIT
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
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HANBit
HSD64M64F8KA
+3.3V
Vtt=1.4V
1200Ω
DOUT
870Ω
50Ω
50pF*
DOUT
Z0=50Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
vss VOL (DC) = 0.4V, IOL = 2mA
(Fig. 2) AC output load circuit
(Fig. 1) DC output load
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-10
-10L
-13
UNIT
NOTE
Row active to row active delay
tRRD(min)
20
20
15
ns
1
/RAS to /CAS delay
tRCD(min)
20
20
20
ns
1
Row precharge time
tRP(min)
20
20
20
ns
1
tRAS(min)
50
50
45
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
70
ns
70
ns
1
2
CLK
2,5
tDAL(min)
2 CLK + 20 ns
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
CAS latency=3
2
CAS latency=2
1
Number of valid output data
65
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
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HSD64M64F8KA
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-10
PARAMETER
MIN
CLK cycle
CAS latency=3
CAS latency=2
CLK to valid
CAS latency=3
-13
MIN
MAX
10
1000
CAS latency=2
Output data
CAS latency=3
NOTE
1000
ns
1
ns
1,2
ns
1,2
10
6
6
5.4
6
7
6
3
3
3
3
3
3
tOH
CAS latency=2
UNIT
MAX
7.5
1000
12
10
MIN
tSAC
output delay
hold time
MAX
10
tCC
time
-10L
SYMBOL
CLK high pulse width
tCH
3
3
ns
2.5
ns
ns
CLK low pulse width
tCL
3
3
ns
2.5
ns
ns
Input setup time
tSS
2
2
ns
1.5
ns
ns
Input hold time
tSH
1
1
ns
0.8
ns
ns
CLK to output in Low-Z
tSLZ
1
1
ns
1
ns
ns
CLK to output
in Hi-Z
CAS latency=3
6
6
5.4
ns
1
6
7
6
ns
1
tSHZ
CAS latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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REV. 1.0 (August, 2002)
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HSD64M64F8KA
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refres
Exit
h
Bank active & row addr.
Read &
column
address
Write &
column
address
Auto
precharge
Auto
/R
A
S
/C
A
S
/W
E
D
Q
M
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
L
L
H
H
H
H
L
L
H
H
X
H
X
L
H
L
precharge
disable
Auto
X
BA
0,1
V
H
X
precharge
X
L
H
L
e
All banks
Clock suspend or
active power down
power
X
H
X
Entry
H
L
Exit
L
H
Entry
Exit
DQM
No operation command
H
L
L
H
L
L
L
H
H
L
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
H
H
X
X
H
X
X
X
L
H
H
H
1,2
3
3
3
3
Column
H
(A0 ~ A9)
4,5
Column
4
V
Address
(A0 ~ A9)
X
V
L
X
H
8
4,5
6
X
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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REV. 1.0 (August, 2002)
4
Address
X
X
NOTE
L
H
X
A11
A9~A0
Row address
L
X
L
H
Bank selection
A10/
AP
V
H
H
enable
Precharg
down mode
/C
S
eable
Burst Stop
Precharge
CKE
n
precharge
disable
Auto
CKE
n-1
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HANBit
HSD64M64F8KA
PACKAGING INFORMATION
Unit : mm
Front – Side
TOLERANCE
:
±0.20
Rear– Side (Top view)
1.3
PM
T = 8.7
5.0
2.6
4.6
PB
MAIN BOARD
3.75
Connector Configuration
- Module PCB Bottom (PM) : AMP 177984-2 (177986-2), 0.8mm Free Height Plugs, 60pins
- Main Board top (PB) : AMP 177983-2(177985-2),0.8mm Free Height Receptacles , 60pins
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REV. 1.0 (August, 2002)
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HSD64M64F8KA
ORDERING INFORMATION
Part Number
Density
Org.
HSD64M64F8KA-10L
512MByte
64M x 64
HSD64M64F8KA-10
512MByte
64M x 64
HSD64M64F8KA-13
512MByte
64M x 64
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
Package
120PIN
STACKABLE
120PIN
STACKABLE
120PIN
STACKABLE
10
Ref.
Vcc
MODE
MAX.frq
4K
3.3V
Synch
100MHz / CL=3
4K
3.3V
Synch
100MHz / CL=2
4K
3.3V
Synch
133MHz / CL=3
HANBit Electronics Co.,Ltd.