PDM41024 1 Megabit Static RAM 128K x 8-Bit Description Features n High-speed access times Com’l: 10, 12 and 15 ns Ind’l: 12 and 15 ns n Low power operation (typical) - PDM41024SA Active: 450 mW Standby: 50 mW - PDM41024LA Active: 400 mW Standby: 25mW n n n The PDM41024 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is accomplished when the write enable (WE) and the chip enable (CE1) inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE and CE2 remain HIGH and CE1 and OE are both LOW. The PDM41024 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41024 comes in two versions: the standard power version (SA) and the low power version (LA). The two versions are functionally the same and differ only in their power consumption. Single +5V (±10%) power supply TTL-compatible inputs and outputs Packages Plastic SOJ (300 mil) - TSO Plastic SOJ (400 mil) - SO Plastic TSOP (I)- T The PDM41024 is available in a 32-pin plastic TSOP (I), and a 300-mil and 400-mil plastic SOJ. Addresses I/O 0 • A0 • • • • • A16 Decoder • • • • • • 4 5 8 Memory Matrix 9 • • • • • Input Data Control Column I/O 10 • 11 • CE1 CE2 WE OE 3 7 • I/O 7 2 6 Functional Block Diagram Rev. 3.3 - 4/09/98 1 • Control 12 1 PDM41024 Pin Configuration SOJ TSOP (I) A11 A9 A8 A13 WE CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A3 Pin Description NC 1 32 Vcc A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 20 19 I/O6 I/O1 13 14 I/O2 15 18 I/O4 Vss 16 17 I/O3 I/O5 Name Description A16-A0 Address Inputs I/O7-I/O0 Data Inputs/Outputs OE WE CE1 CE2 I/O MODE OE Output Enable Input X X H X Hi-Z Standby WE Write Enable Input X X X L Hi-Z Standby Truth Table(1) CE1, CE2 Chip Enable Inputs L H L H DOUT Read NC No Connect X L L H DIN Write VCC Power (+5V) H H L H Hi-Z Output Disable VSS Ground NOTE: 1. H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol Rating Com’l. Ind. Unit VTERM Terminal Voltage with Respect to VSS –0.5 to +7.0 –0.5 to +7.0 V TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 125 145 °C Tj Maximum Junction Temperature (2) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja values: SOJ: 72o C/W TSOP: 95o C/W 2 4/09/98 - Rev. 3.3 PDM41024 Recommended DC Operating Condition Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V VSS Supply Voltage 0 0 0 V Industrial Ambient Temperature –40 25 85 °C Commercial Ambient Temperature 0 25 70 °C 1 2 DC Electrical Characteristics (VCC = 5.0V ± 10%) 3 PDM41024SA PDM41024LA Min. Max. Min. Max. Unit Symbol Parameter Test Conditions ILI Input Leakage Current VCC = MAX., VIN = VSS to VCC Com’l/ Ind. –5 5 –1 1 µA ILO Output Leakage Current VCC = MAX., CE1 = VIH and CE2 = VIL, VOUT = VSS to VCC Com’l/ Ind. –5 5 –1 1 µA VIL Input Low Voltage –0.5(1) 0.8 –0.5(1) 0.8 V VIH Input High Voltage 2.2 6.0 2.2 6.0 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. IOL = 10 mA, VCC = Min. — — 0.4 0.5 — — 0.4 0.5 V V VOH Output High Voltage IOH = –4 mA, VCC = Min. 2.4 — 2.4 — V 4 5 6 NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns 7 Power Supply Characteristics -10 Symbol ICC ISB ISB1 Parameter Operating Current CE1 = VIL and CE2 = VIH -12 -15 Power SA Com’l. 250 Com’l. 230 Ind. 240 Com’l. 185 Ind. 195 f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA LA 230 210 220 165 175 Standby Current CE1 = VIH and CE2 = VIL SA 80 70 70 55 55 f = fMAX = 1/tRC VCC = Max. LA 75 65 65 50 50 Full Standby Current CE1 ≥ VHC and CE2 ≤ VLC SA 20 20 25 10 15 f=0 VCC = Max. VIN ≥ VCC – 0.2V or ≤ 0.2V LA 10 10 10 5 10 8 9 10 11 SHADED AREAS = PRELIMINARY DATA NOTES: All values are maximum guaranteed values. VLC ≤ 0.2V, VHC ≥ VCC – 0.2V Rev. 3.3 - 4/09/98 12 3 PDM41024 Capacitance(1) (TA = +25°C, f = 1.0 MHz) Symbol Parameter Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance 8 pF NOTE:1. This parameter is determined by device characterization but is not production tested. AC Test Conditions VSS to 3.0V Input pulse levels Input rise and fall times 3 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 +5V +5V 480Ω 480Ω DOUT DOUT 255Ω 255Ω 30 pF Delta tAA - ns Figure 1. Output Load Equivalent 5 pF Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Typical Delta tAA vs Capacitive Loading 5 4 3 2 1 0 0 30 60 90 120 Additional Lumped Capacitive Loading (pF) Figure 3. 4 4/09/98 - Rev. 3.3 PDM41024 Read Cycle No. 1(4, 5) 1 tRC ADDR 2 tAA tOH DOUT DATA VALID PREVIOUS DATA VALID 3 Read Cycle No. 2(2, 4, 6) tRC 4 ADDR tAA tACE 5 CE1 CE2 tHZCE tLZCE 6 OE tLZOE tHZOE DOUT DATA VALID 7 tAOE 8 AC Electrical Characteristics -10(7) Description READ Cycle Sym -12(7) -15 Min. Max. Min. Max. Min. Max. Units READ cycle time tRC Address access time tAA Chip enable access time tACE Output hold from address change tOH 3 3 3 ns Chip enable to output in low Z(1,3) tLZCE 5 5 5 ns Chip disable to output in high Z(1,2,3) tHZCE Chip enable to power up time(3) Chip disable to power down time tPU (3) Output enable access time Output enable to output in low Z (1,3) Output disable to output in high Z(1,3) 10 12 10 12 10 15 6 0 7 0 ns ns 12 15 ns tAOE 6 6 6 ns 6 ns 0 0 6 0 6 11 ns 10 tLZOE 10 ns tPD tHZOE 9 ns 15 12 6 0 15 12 ns SHADED AREA = PRELIMINARY DATA Notes referenced are after Data Retention Table. Rev. 3.3 - 4/09/98 5 PDM41024 Write Cycle No. 1 (Write Enable Controlled) tWC ADDR tAW tAH tCW CE2 CE1 tAS tWP2 WE tDS DIN tDH DATA VALID tHZWE tLZWE HIGH-Z DOUT Write Cycle No. 2 (Write Enable Controlled) tWC ADDR tAW tAH tCW CE2 CE1 tAS tWP1 WE tDS DIN DOUT tDH DATA VALID HIGH-Z NOTE: Output Enable (OE) is inactive (high) 6 4/09/98 - Rev. 3.3 PDM41024 Write Cycle No. 3 (Chip Enable Controlled) 1 tWC ADDR tAW tAH tAS 2 tCW CE2 CE1 3 tWP1 WE tDS DIN tDH 4 DATA VALID HIGH-Z DOUT 5 NOTE: Output Enable (OE) is inactive (high) 6 AC Electrical Characteristics -10(7) Description -12(7) -15 WRITE Cycle Sym WRITE cycle time tWC 10 12 15 ns Chip enable active time tCW 10 10 11 ns Address valid to end of write tAW 10 10 11 ns Address setup time tAS 0 0 0 ns Address hold from end of write tAH 0 0 0 ns Write pulse width tWP1 8 8 11 ns Write pulse width tWP2 8 8 12 ns tDS 7 7 7 ns Data setup time Data hold time tDH 0 0 0 ns (1,3) tLZWE 0 0 0 ns Z(1,3) tHZWE Write disable to output in low Z Write enable to output in high 7 Min. Max. Min. Max. Min. Max. Units 7 7 7 8 9 10 ns SHADED AREA = PRELIMINARY DATA Notes referenced are after Data Retention Table 11 12 Rev. 3.3 - 4/09/98 7 PDM41024 Low VCC Data Retention Waveform Data Retention Mode V CC 4.5V 4.5V VDR t CDR tR VDR VIH CE1 V CE2 IL DON'T CARE VIH V IL ≤ 0.2V Data Retention Electrical Characteristics (LA Version Only) for JEDEC Version Symbol Parameter Test Conditions VDR VCC for Retention Data ICCDR Data Retention Current tCDR tR (3) CE1 ≥ VCC – 0.2V or CE2 ≤ VSS + 0.2V VIN ≥ VCC – 0.2V or ≤ 0.2V Min. Typ. Max. Unit 2 — — V VCC = 2V — — 500 µA VCC = 3V — — 750 µA 0 — — ns tRC — — ns Chip Deselect to Data Retention Time Operation Recovery Time NOTES: (For three previous Electrical Characteristics tables) 1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE. 3. This parameter is sampled. 4. WE is high for a READ cycle. 5. The device is continuously selected. All the Chip Enables are held in their active state. 6. The address is valid prior to or coincident with the latest occurring Chip Enable. 7. Vcc = 5V ± 5%. Ordering Information XXXXX X Device Type Power XX Speed X X X Package Type Process Temp. Range Preferred Shipping Container Blank Tubes TR Tape & Reel TY Tray Blank Commercial (0° to +70°C) I Industrial (-40° to +85°C) A Automotive (-40° to +105°C) TSO 32-pin 300-mil Plastic SOJ SO 32-pin 400-mil Plastic SOJ T 32-pin Plastic TSOP (I) 10 Commercial Only 12 15 (use 15 ns for slower designs) SA LA Standard Power Low Power PDM41024 - 1 Meg (128Kx8) Static RAM 8 4/09/98 - Rev. 3.3