ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8312I is a low skew, 1-to-12 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8312I single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. • 12 LVCMOS / LVTTL outputs ICS • LVCMOS / LVTTL clock input • Maximum output frequency: 250MHz • Output skew: 160ps (maximum) • Operating supply modes: Core/Output 3.3V/3.3V 2.5V/2.5V 1.8V/1.8V 3.3V/2.5V 3.3V/1.8V 2.5V/1.8V The ICS8312I is characterized at full 3.3V, 2.5V, and 1.8V, or mixed 3.3V core/2.5V, 3.3V core/1.8V and 2.5V core/1.8V output operating supply modes. Guaranteed output and part-topart skew characteristics along with the 1.8V output capabilities makes the ICS8312I ideal for high performance, single ended applications that also require a limited output voltage. • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT GND Q3 VDDO Q2 GND Q1 Q0 32 31 30 29 28 27 26 25 nD Q LE 12 CLK VDDO CLK_EN Q0:Q11 GND 1 24 VDD 2 23 VDDO CLK_EN 3 22 Q5 21 GND 20 Q6 Q4 CLK 4 GND 5 OE 6 19 VDDO VDD 7 18 Q7 GND 8 17 GND ICS8312I 9 10 11 12 13 14 15 16 OE GND Q8 VDDO Q9 GND Q10 VDDO Q11 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Pacakge Top View 8312AYI http://www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 5, 8, 12, 16, 17, 21, 25, 29 2, 7 Name Type GND Power VDD Power 3 CLK_EN Input 4 CLK Input 6 OE Input Description Power supply ground. Core supply pins. Synchronous control for enabling and disabling clock outputs. Pullup LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q11. LVCMOS / LVTTL interface levels. 9, 11, 13, 15, Q11, Q10, Q9, Q8, 18, 20, 22, Q7, Q6, Q5, Output Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels. 24, 26, 28, Q4, Q3, Q2, 30, 32 Q1, Q0 10, 14, 19, Power Output supply pins. VDDO 23, 27, 31 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance (per output) VDDO = 3.465V 19 pF VDDO = 2.625V 18 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ VDDO = 3.3V ± 5% 7 Ω ROUT Output Impedance VDDO = 2.5V ± 5% 7 Ω VDDO = 1.8V ± 0.2V 10 Ω VDDO = 2V TABLE 3A. OUTPUT ENABLE AND 16 pF CLOCK ENABLE FUNCTION TABLE Control Inputs Output OE CLK_EN Q0:Q11 0 X Hi-Z 1 0 LOW 1 1 Follows CLK input TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs OE CLK_EN CLK Q0:Q11 1 1 0 LOW 1 1 1 HIGH 8312AYI http://www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 1.6 1.8 2.0 V 1.6 1.8 VDDO Output Supply Voltage 2.0 V IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V VDD Core Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA Units TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum 2.375 2.5 2.625 V 1.6 1.8 2.0 V VDD Core Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current 10 µA IDDO Output Supply Current 10 µA 8312AYI http://www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter CLK VIH Input High Voltage CLK_EN, OE CLK VIL Input Low Voltage CLK_EN, OE CLK IIH Input High Current CLK_EN, OE Test Conditions Minimum VDD = 3.3V ± 5% 2 IIL Input Low Current CLK_EN, OE VOH Output High Voltage Output Low Voltage Units VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V 0.65*VDD VDD + 0.3 V VDD = 3.3V ± 5% 2 VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 1.8V ± 0.2V 0.65*VDD VDD + 0.3 V VDD = 3.3V ± 5% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 1.8V ± 0.2V -0.3 0.35*VDD V VDD = 3.3V ± 5% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 1.8V ± 0.2V -0.3 0.35*VDD V VDD = 3.3V ± 5% 150 µA VDD = 2.5V ± 5% 150 µA VDD = 1.8V ± 0.2V 150 µA VDD = 3.3V ± 5% 5 µA VDD = 2.5V ± 5% 5 µA 5 µA VDD = 3.3V ± 5% -5 µA VDD = 2.5V ± 5% -5 µA VDD = 1.8V ± 0.2V -5 µA VDD = 3.3V ± 5% -150 µA VDD = 2.5V ± 5% -150 µA VDD = 1.8V ± 0.2V -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; IOH = -1mA 2 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 0.2V; IOH = -100uA VDD - 0.2 V VDDO = 1.8V ± 0.2V; NOTE 1 VDD - 0.3 VDDO = 3.3V ± 5%; NOTE 1 VOL Maximum VDD = 1.8V ± 0.2V VDD = 1.8V ± 0.2V CLK Typical V 0.5 V VDDO = 2.5V ± 5%; IOL = 1mA 0.4 V VDDO = 2.5V ± 5%; NOTE 1 0.45 V VDDO = 1.8V ± 0.2V; IOL = 100uA 0.2 V VDDO = 1.8V ± 0.2V; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. 8312AYI http://www.icst.com/products/hiperclocks.html 4 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Minimum Typical Maximum Units 250 MHz 2.7 ns Output Skew; NOTE 2, 5 150 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 850 ps tR/tF Output Rise Time; NOTE 4 20% to 80% 175 800 ps odc Output Duty Cycle f ≤ 150MHz 45 55 % f ≤ 250MHz 1.2 2.0 All parameters measured at fMAX unless noted otherwise. See Table 5C listed below for Notes 1 through 5. TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Minimum Typical Maximum Units 250 MHz 3.5 ns Output Skew; NOTE 2, 5 155 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 1.1 ns tR/tF Output Rise Time; NOTE 4 20% to 80% 200 800 ps odc Output Duty Cycle f ≤ 150MHz 45 55 % f ≤ 250MHz 1.25 2.4 All parameters measured at fMAX unless noted otherwise. See Table 5C listed below for Notes 1 through TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Minimum Typical Maximum Units 200 MHz 4.9 ns Output Skew; NOTE 2, 5 160 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 2.4 ns tR/tF Output Rise Time; NOTE 4 20% to 80% 175 875 ps odc Output Duty Cycle f ≤ 100MHz 45 55 % f ≤ 200MHz 1.6 3.3 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8312AYI http://www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 tR/tF Output Rise Time; NOTE 4 20% to 80% odc Output Duty Cycle f ≤ 150MHz Minimum f ≤ 250MHz Typical Maximum Units 250 MHz 2.8 ns 150 ps 1 ns 200 800 ps 45 55 % 1.5 2.1 All parameters measured at fMAX unless noted otherwise. See Table 5F listed below for Notes 1 through 5. TABLE 5E. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Minimum Typical Maximum Units 200 MHz 3.5 ns Output Skew; NOTE 2, 5 150 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 1.4 ns tR/tF Output Rise Time; NOTE 4 20% to 80% 200 800 ps odc Output Duty Cycle f ≤ 100MHz 45 55 % f ≤ 200MHz 1.5 2.5 All parameters measured at fMAX unless noted otherwise. See Table 5F listed below for Notes 1 through TABLE 5F. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 tsk(o) Minimum Typical Maximum Units 200 MHz 3.9 ns Output Skew; NOTE 2, 5 160 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 1.6 ns tR/tF Output Rise Time; NOTE 4 20% to 80% 200 800 ps odc Output Duty Cycle f ≤ 100MHz 45 55 % f ≤ 200MHz 1.4 2.7 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8312AYI http://www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO LVCMOS SCOPE VDD, VDDO Qx LVCMOS GND Qx GND -1.165V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 0.9V ± 0.1V SCOPE VDD, VDDO 1.25V±5% SCOPE VDD VDDO LVCMOS Qx LVCMOS Qx GND GND -0.9V ± 0.1V -1.25V±5% 1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 0.9V±0.1V 2.4±0.9V 0.9V±0.1V SCOPE V DD VDDO LVCMOS VDDO Qx LVCMOS Qx GND GND -0.9V±0.1V -0.9V±0.1V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 8312AYI SCOPE V DD 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT http://www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER Part 1 V DDO Qx 2 DDO 2 Part 2 V DDO Qy V Qx V DDO Qy 2 t sk(o) OUTPUT SKEW 2 t sk(pp) PART-TO-PART SKEW VDD 2 80% 80% CLK Clock Outputs 20% 20% tR VDDO 2 tF Q0:Q11 t PD OUTPUT RISE/FALL TIME PROPAGATION DELAY V DDO 2 Q0:Q11 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8312AYI http://www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8312I is: 339 8312AYI http://www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8312AYI http://www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 23, 2003 ICS8312I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8312AYI ICS8312AYI 32 Lead LQFP 250 per tray -40°C to 85°C ICS8312AYIT ICS8312AYI 32 Lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8312AYI http://www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 23, 2003