ICSSSTUA32S869B Advance Information Integrated Circuit Systems, Inc. 14-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 7 8 9 10 11 A B C D Product Features: • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50% more dynamic driver strength than standard SSTU32864 • Supports LVCMOS switching levels on C1 and RESET# inputs • Low voltage operation VDD = 1.7V to 1.9V • Available in 150 BGA package • Green packages available E F G H J K L M N P R T U V W 150 Ball BGA (Top View) Functionality Truth Table Inputs Outputs RESET# DCS# CSR# CK CK# H L L ↑ ↓ Dn, DODT, DCKE QODT, QCKE Qn QCS# L L L L H H L L ↑ ↓ H L H H L L L or H L or H X Q0 Q0 Q0 H ↑ ↓ L L L L H L H L H ↑ ↓ H H L H H L H L or H L or H X Q0 Q0 Q0 H H L ↑ ↓ L L H L H H H L ↑ ↓ H H H H H L L or H L or H X Q0 Q0 Q0 H H H ↑ ↓ L Q0 H L H H H ↑ ↓ H Q0 H H H H H L or H L or H X Q0 Q0 Q0 L X or floating X or floating X or floating X or floating X or floating L L L 1173—10/28/05 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICSSSTUA32S869B Advance Information Ball Assignments 1 2 3 4 5 6 7 8 9 10 A NB VDD MCL(1) NC GND VREF GND NC MCL(1) VDD NC B VDD NB VDD GND GND GND GND GND VDD NB VDD C QCKEA VDD NB GND NB GND NB GND NB VDD QCKEB D Q2A VDD GND NB DCKE NB D2 NB GND VDD Q2B E Q3A VDD NB D3 NB NC NB DODT NB NC Q3B F QODTA VDD GND NB NC NB NC NB GND VDD QODTB G Q5A VDD GND D5 NB CLK NB D6 GND VDD Q5B H Q6A NB GND NB NC NB NC NB GND NB Q6B J QCSA# VDD NB NC NB RESET# NB CSR# NB VDD QCSB# K VDD VDD GND GND NB NB NB GND VDD VDD VDD L Q8A VDD NB DCS# NB CLK# NB D8 NB VDD Q8B M Q9A NB GND NB NC NB NC NB GND NB Q9B N Q10A VDD GND D9 NB NC NB D10 GND VDD Q10B P Q11A VDD GND NB NC NB NC NB GND VDD Q11B R Q12A C1 NB D11 NB NC NB D12 NB VDD Q12B T Q13A VDD GND NB D13 NB D14 NB GND VDD Q13B U Q14A VDD NB GND NB GND NB GND NB VDD Q14B V VDD NB VDD GND GND GND GND GND VDD NB VDD VDD MCL(1) PARIN1 GND VREF GND PPO1 MCL(1) VDD NB W P TYERR1# 11 Note: NC denotes a no-connect (ball present but not connected to the die). NB indicates no ball is populated at that gridpoint. 1173—10/28/05 2 ICSSSTUA32S869B Advance Information Parity and Standby Function Table Inputs Output RESET# DCS# CSR# CK CK# £ of inputs = H D1..… D14(1) PARIN1(2) PPO1(2) PTYERR1#(3) H H H H H H H H H H L L L L L L L L H X X or floating X X X X L L L L H X X or floating ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ L or H X or floating ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ L or H X or floating Even Odd Even Odd Even Odd Even Odd X X X or floating L L H H L L H H X X X or floating L H H L L H H L PPOn0 PPOn0 H L L H H L L H PTYERRn0# PTYERRn0# L H L NOTE 1 Inputs D1, D4 and D4 are not included in this range. NOTE 2 PARIN1 arrives one (C1 = 0) or two (C = 1) clock cycles after data to which it applies. NOTE 3 This transition assumes PTYERR1# is high at the crossing of CK going high and CK# going low. If PTYERR1# is low, it stays latched low for two clock cycles or until RESET# is driven low. PARIN1 is used to generate PPO1 and PTYERR1#. 1173—10/28/05 3 ICSSSTUA32S869B Advance Information General Description The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs. The ICSSSTUA32S869B operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR1# are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. ICSSSTUA32S869B must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that there are no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn, PPO1 (Paritial-Parity-Out) and PTYERR1# (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS or CSR input is low, the Qn, PPO1 and PTYERR1# outputs will function normally. The RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR1# high. The ICSSSTUA32S869B includes a parity checking function. The ICSSSTUA32S869B accepts a parity bit from the memory controller at its input pin PARIN1 one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR1 pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1, see Figure 6 and 7. When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO1 and PTYERR1# signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR1# signals of the first register are left floating. The PPO1 outputs of the first register are cascaded to the PARIN1 signals on the second register (back). The PPO1 and PTYERR1# signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in Figure 1. If an error occurs, and the PTYERR1# is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations. All registers used on an individual DIMM must be of the same configuration, i.e single or dual die. Parin1, W4 Parin . PPO1, W8 . Register 1 (Front) NC, A4 NC, A8 NC, A8 PTYERR1# W1 Parin1, W4 Register 2 (Back) NC, A11 Set C1 = 0 for Register 1; Set C1 = 1 for Register 2. NC denotes No Connect. Figure 1 — Parity implementation and device wiring for SSTU32S869 and SSTU32D869 1173—10/28/05 4 ICSSSTUA32S869B Advance Information Terminal Functions Signal Group Signal Name Type Description Ungated inputs DCKE, DODT SSTL_18 DRAM function pins not associated with Chip Select. Chip Select gated inputs D1 ... D14(1) SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. Chip Select inputs DCS#, CSR# SSTL_18 DRAM Chip Select signals. This pins initiate DRAM address/ command decodes, and as such at least one will be low when a valid address/command is present. Re-driven outputs Q1A...Q14A, SSTL_18 Q1B ... Q14B, QCSA#, QCSB# QCKEA,QCKEB QODTA,QODTB Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. Parity input PARIN1 SSTL_18 Inout parity is received on pin PARIN1 and should maintain (1) parity across the D1...D14 inputs, at the rising edge of the clock, one cycle after Chip Select is LOW. Parity output PPO1 SSTL_18 Partial Parity Output. Indicates parity out of D1-D14(1) Parity error output PTYERR1# Open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR1# will be active for two clock cycles, and delayed by in total 2 clock cycles for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). Configuration Inputs C1 1.8V LVCMOS When Low, register is configured as Register 1. When High, register is confugured as Register 2. Clock inputs CK, CK# SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Miscellaneous inputs RESET# 1.8 V LVCMOS Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET# also resets the PTYERR# signal. VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. VDD Power Input GND Ground Input Ground Power supply voltage NOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range. 1173—10/28/05 5 ICSSSTUA32S869B Advance Information Block Diagram VREF LSP0 internal node (CS Active) 2 PARIN1 PARITY GENERATOR AND CHECKER 2 PPO1 PTYERR1# D 2 R D D1 R D D14 R DCS# 11 Q1A Q1B Q14A Q14B D QCSA# R QCSB# D QCKEA R QCKEB D QODTA R QODTB CSR# DCKE DODT RESET# CK CK# 1173—10/28/05 6 ICSSSTUA32S869B Advance Information Block Diagram RESET# LPSO (Internal Node) CLK CLK# D CLK D2 - D3, D5 - D6, D8 - D14 VREF 11 D R CE D2 - D3, D5 - D6, D8 - D14 11 CE CLK 11 11 R D2 - D3, 11 D5 - D6, D8 - D14 Q2A - Q3A, Q5A - Q6A, Q8A - Q14A Q2B - Q3B, Q5B - Q6B, Q8B - Q14B Parity Check 0 D PPO 2 CLK CLK R R PAR_IN 1, PAR_IN 2 2 PPO 1, D 1 CE 2 PTYERR 1, 2 PTYERR 2 C1, C2 CLK 2-Bit Counter 0 D 1 R CLK R NOTE 2 PARIN 1 is used to generate PPO1 and PTYERR1#. 1173—10/28/05 7 ICSSSTUA32S869B Advance Information Register Timing RESET# DCS# CSR# n n+2 n+1 n+3 CLK CLK# tsu D1 - D14 tH (1) tPD CLK to Q Q1 - Q14 (1) tSU tH PAR_IN1,(2) PAR_IN2, tPD CLK to PPO PPO1, PPO2 (2) PTYERR1#,(2) PTYERR2#, tPD CLK to PTYERR# tPD CLK to PTYERR# Note 1 This range doesn't include D1, D4 and D7 and their corresponding outputs 1173—10/28/05 8 n+4 ICSSSTUA32S869B Advance Information Register Timing RESET# DCS# CSR# n n+3 n+2 n+1 n+4 CLK CLK# tsu D1 - D4 tH (1) tPD CLK to Q Q1 - Q14 (1) PAR_IN1, PAR_IN2 tSU (2) tH tPD CLK to PPO PPO1, (2) PPO2 (not used) tPD CLK to PTYERR# PTYERR1#, (2) PTYERR2# Note 1: This range doesn't include D1, D4 and D7 and their corresponding outputs 1173—10/28/05 9 tPD CLK to PTYERR# ICSSSTUA32S869B Advance Information Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDDQ or GND Current/Pin . . . . . . . . . . . . . . . –65°C to +150°C -0.5 to 2.5V -0.5 to VDD + 2.5V -0.5 to VDDQ + 0.5 ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance3 36°C ............... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER V DD VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID IOH IOL TA DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET#, C0 Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 1 MIN TYP 1.7 1.8 0.49 x VDD 0.5 x VDD V REF - 0.04 VREF 0 VREF + 0.125 VREF + 0.250 MAX 1.9 0.51 x V DD VREF + 0.04 VDDQ VREF - 0.125 VREF - 0.250 UNITS V 0.65 x VDDQ 0.675 0.600 0 0.35 x VDDQ 1.125 -8 8 70 mA °C Guaranteed by design, not 100% tested in production. Note: Reset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Reset# is low. Mode Select C1 Device Mode 0 First Device in Pair, Front 1 Second Device in Pair, Back 1173—10/28/05 10 ICSSSTUA32S869B Advance Information Electrical Characteristics - DC TA = 0 - 70°C; V DD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL VIK V OH V OL II IDD I DDD Ci PARAMETERS CONDITIONS VDDQ I I = -18mA I OH = -100µA I OH = 6mA I OL = 100µA I OL = 6mA All Inputs V I = V DD or GND Standby (Static) RESET# = GND V I = V IH(AC) or VIL(AC), Operating (Static) RESET# = V DD RESET# = V DD, Dynamic operating V I = V IH(AC) or VIL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 RESET# = V DD, V I = V IH(AC) or VIL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle Input capacitance, V I = V REF ± 250 mV Dn, PAR_IN inputs Input capacitance, V I = V REF ± 250 mV DCS#n Input capacitance, V ICR = 0.9V; VI(PP) = 600 mV CK and CK# inputs 2 Input capacitance, V I = V DD or GND RESET# input Data Inputs V I = V REF ±350mV CLK and CLK# V ICR = 1.25V, VI(PP) = 360mV V I = V DDQ or GND RESET# MIN TYP 1.7V 1.7V 1.7V 1.7V 1.9V VDDQ - 0.2 1.2 V 0.2 0.5 ±5 0.2 1.9V µA µA TBD mA TBD µ/clock MHz TBD µA/ clock MHz/data 1.8V 2.5 3.5 pF 2 3 pF 2 3 pF Note 2 Note 2 pF 2.5 2 3.5 3 pF 1.8V 2.5 Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V ± 0.1V UNIT PARAMETER MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_∆ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate) 11 UNITS -1.2 Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - The vendor must supply this value for full device description. 1173—10/28/05 MAX ICSSSTUA32S869B Advance Information Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 1.8V ±0.1V PARAMETERS SYMBOL MIN MAX Clock frequency 340 f clock tACT Differential inputs active time 10 t INACT Differential inputs inactive time 15 tS Setup time Data before CLK↑, CLK#↓ 0.5 DCS0 before CLK↑, CLK#↓, 0.7 CSR# high DCS#, DODT, DCKE and Q Hold time 0.30 after CK↑, CK#↓ tH PARIN1 after CK↑, CK#↓ 0.30 Hold time 1 - Guaranteed by design, not 100% tested in production. Notes: 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax Max input clock frequency 340 Propagation delay, single CK↑ to CK#↓ QN bit switching Low to High propagation CK↑ to CK#↓ to tLH delay PTYERR# High to low propagation CK↑ to CK#↓ to tHL delay PTYERR# Propagation delay tPDMSS CK↑ to CK#↓ QN simultaneous switching High to low propagation tPHL RESET# ↓ to QN↓ delay Low to High propagation RESET# ↓ to tPLH delay PTYERR1#↑ 1. Guaranteed by design, not 100% tested in production. tPDM 1173—10/28/05 12 Units MHz 1.2 1.9 ns 1.2 3 ns 1 3 ns 2 ns 3 ns 3 ns UNITS MHz ns ns ns ns ns ICSSSTUA32S869B Advance Information VDD DUT td = 350ps TL =50Ω CK Inputs CK# CK RL = 1000Ω TL=350ps, 50Ω Out Test Point CL = 30 pF (see Note 1) Test Point RL = 1000Ω RL = 100Ω LOAD CIRCUIT Test Point LVCMOS RESET# Inp ut VDD VDD/2 VDD/2 t in act IDD (see Note 2) VID 0V CK CK t PLH 90% t PHL 10% VOH Output VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR V TT VTT VICR VOLTAGE WAVEFORMS – PULSE DURATION LVCMOS RST# Input VID CK VIH VDD /2 VIL VICR t RPHL CK t su Inpu t VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VID tw Inpu t VICR VICR t act VREF VOH th Output VREF VIH VTT VOL VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES VIL VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES Figure 6 — Parameter M easurement I nfor mation (V DD = 1.8 V ± 0.1 V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM. 1173—10/28/05 13 ICSSSTUA32S869B Advance Information Output slew rate measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. VDD DUT RL = 50Ω OUT TEST POINT CL = 10 pF SEE NOTE (1) 002aaa377 (1) CL includes probe and jig capacitance. Figure 12 — Load circuit, HIGH-to-LOW slew measurement OUTPUT VOH 80% dv_f 20% VOL dt_f 002aaa378 Figure 13 — Voltage waveforms, HIGH-to-LOW slew rate measurement DUT OUT TEST POINT CL = 10 pF SEE NOTE (1) RL = 50Ω 002aaa379 (1) CL includes probe and jig capacitance. Figure 14 — Load circuit, LOW-to-HIGH slew measurement dt_r VOH 80% dv_r 20% OUTPUT VOL 002aaa380 Figure 15 — Voltage waveforms, LOW-to-HIGH slew rate measurement 1173—10/28/05 14 ICSSSTUA32S869B Advance Information Error output load circuit and voltage measurement information (VDD = 1.8 V ± 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR10 MHz; Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. VDD DUT RL = 1 k OUT TEST POINT CL = 10 pF SEE NOTE (1) 002aaa500 (1) CL includes probe and jig capacitance. Figure 16 — Load circuit, error output measurements LVCMOS RESET Input VCC VCC/2 0V tPLH VOH 0.15 V Output Waveform 2 0V 002aaa501 Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET# input Timing Inputs VICR VI(PP) VICR tHL VCC Output Waveform 1 VCC/2 VOL 002aaa502 Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs Timing Inputs VICR VI(PP) VICR tLH VOH Output Waveform 2 0.15 V 0V 002aaa503 Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs 1173—10/28/05 15 ICSSSTUA32S869B Advance Information DUT OUT Testpoint RL=1K CL=5pF See Note (1) (1) CL includes probe and jig capacitance. Figure 22 — Partial parity out load circuit CK VICR VICR tPLH tPHL Vi(P-P) CK VTT VTT Output VTT = VDD/2 VICR Cross Point Voltage Vi(P-P) = 600mV tPLH and tPHL are the same as tPD. Figure 23 — Partial parity out voltage waveform, propagation delay time with respect to CLK input 1173—10/28/05 16 ICSSSTUA32S869B Advance Information d= b D1 D h= E E1 T c ALL DIMENSIO NS IN MILLIMETERS ----- BALL G RID ----D E T e HORIZ VERT TO TAL Min/Max 13.00 Bs c 8.00 Bsc 0.90/1.20 0.65 Bsc 11 19 150 REF. DIMS d h Min/Max Min/Max 0.38/0.48 0.27/0.37 D1 E1 b c 11.70 Bs c 6.50 Bs c 0.65 0.75 Note: B all grid total indic ates max imum ball count for pack age. Les ser quantity may be used. Ordering Information ICSSSTUA32S869BH(LF)-T Example: ICS XXXX y H (LF)- T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 1173—10/28/05 17 *** ICSSSTUA32S869B Advance Information Revision History Rev. 0.1 Issue Date Description 10/27/2005 Initial Release. Page # - 1173—10/28/05 18