DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1. The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs. When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO and PTYERR signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR signals of the first register are left floating. The PPO outputs of the first register are cascaded to the PARIN signas on the second register (back). The PPO and PTYERR signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in the diagram below. The IDT74SSTUBF32869A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. If an error occurs, and the PTYERR is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. IDT74SSTUBF32869A must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that there are no glitches on the output. All registers used on an individual DIMM must be of the same configuration, i.e single or dual die. Features • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50% more dynamic driver strength than standard SSTU32864 • Supports LVCMOS switching levels on C1 and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 150 BGA package The device monitors both DCS and CSR inputs and will gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS and CSR input is low, the Qn, PPO and PTYERR outputs will function normally. The RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR high. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL Applications • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A • Ideal for DDR2 667 and 800 1 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity Implementation and Device Wiring PPO, W8 PARIN, W4 Register 1 (Front) PARIN NC, A8 PTYERR, W1 PPO, W4 Register 2 (Back) NC, A4 NC, A11 NC, A8 Set C=0 for Register 1, and C=1 for Register 2 Block Diagram (CS Active) VREF 2 2 2 PARIN D PPO 2 Q PARITY GENERATOR AND CHECKER 2 PTYERR R Q1A D D1 Q Q1B R 11 Q14A(1) D14 (1) D Q Q14B (1) R QCSA DCS0 D Q QCSB CSR R QCKEA DCKE D Q QCKEB R QODTA DODT D Q QODTB R RESET CLK CLK NOTE: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Block Diagram RESET LPS0 (Internal Node) CLK CLK CE D CLK D2 - D3, D5 - D6, D8 - D14 VREF 11 R CE CE D CE 11 CLK D2 - D3, D5 - D6, D8 - D14 Q2 A- Q3A, Q5A - Q6A, Q8A - Q14A 11 Q2B - Q3B, Q5B - Q6B, Q8B - Q14B 11 R 11 D2 - D3, D5 - D6, D8 - D25 Parity Check 0 PPO CLK CLK R R PARIN 2 D 1 D CE 2 2 PTYERR C1, C2 CLK 0 2-Bit Counter D 1 R CLK R NOTE: 1.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 3 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configuration 1 2 4 5 6 7 8 9 10 11 A NB VDD MCL NC GND VREF GND NC MCL VDD NC B VDD NB VDD GND GND GND GND GND VDD NB VDD C QCKEA VDD NB GND NB GND NB GND NB VDD QCKEB D Q2A VDD GND NB DCKE NB D2 NB GND VDD Q2B E Q3A VDD NB D3 NB NC NB DODT NB C1 Q3B F QODTA VDD GND NB NC NB NC NB GND VDD QODTB G Q5A VDD GND D5 NB CLK NB D6 GND VDD Q5B H Q6A NB GND NB NC NB NC NB GND NB Q6B J QCSA VDD NB NC NB RESET NB CSR NB VDD QCSB K VDD VDD GND GND NB NB NB GND VDD VDD VDD L Q8A VDD NB DCS NB CLK NB D8 NB VDD Q8B M Q9A NB GND NB NC NB NC NB GND NB Q9B N Q10A VDD GND D9 NB NC NB D10 GND VDD Q10B P Q11A VDD GND NB NC NB NC NB GND VDD Q11B R Q12A C1 NB D11 NB NC NB D12 NB VDD Q12B T Q13A VDD GND NB D13 NB D14 NB GND VDD Q13B U Q14A VDD NB GND NB GND NB GND NB VDD Q14B V VDD NB VDD GND GND GND GND GND VDD NB VDD VDD MCL PARIN GND VREF GND PPO VDD NB W PTYERR 3 (1) (1) (1) (1) MCL 150-Ball BGA TOP VIEW NOTE: 1.NC denotes a no-connect (ball present but not connected to the die). NB indicates no ball is populated at that gridpoint. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 4 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE 150 Ball CTBGA Package Attributes Top Marking 11 10 1 2 3 4 5 6 7 8 9 10 9 8 7 6 5 4 3 2 1 11 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W TOP VIEW BOTTOM VIEW SIDE VIEW 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 5 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 Outputs RESET DCS CSR CLK CLK Dn, DODT, DCKE Qn QCS QODT, QCKE H L L ↑ ↓ L L L L H L L ↑ ↓ H H H L L L or H L or H X Q0 H L H ↑ ↓ L L H L H ↑ ↓ H H H L H L or H L or H X Q0 H H L ↑ ↓ L L H H L ↑ ↓ H H L 2 Q0 H 2 L L L 2 Q0 H 2 H Q0 Q 02 L H 2 Q 02 H 2 Q 02 H H L L or H L or H X Q0 H H H ↑ ↓ L Q02 H L 2 H H H H H ↑ ↓ H Q0 H H H L or H L or H X Q02 Q02 Q 02 L X or Floating X or Floating L L L 1 2 X or X or X or Floating Floating Floating H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW Output Level before the indicated steady-state conditions were established. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 6 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Terminal Functions Signal Group Terminal Name Type Description Ungated Inputs DCKE, DODT SSTL_18 DRAM function pins not associated with Chip Select Chip Select Gated Inputs D1...D141 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW Chip Select Inputs DCS, CSR SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. Re-Driven Outputs Q1A...Q14A1, Q1B...Q14B1, QCSnA, B QCKEnA, B QODTnA, B SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock Parity Input PARIN SSTL_18 Input parity is received on pin PARIN, and should maintain odd parity across the D1:D14 inputs, at the rising edge of the clock, one cycle after Chip Select is LOW. Parity Output PPO SSTL_18 Partial Parity Output. Indicates parity out of D1-D14. When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by in total two clock cycles for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). Parity Error Output PTYERR Configuration Inputs C1 SSTL_18 When LOW, the register is configured as Register 1. When HIGH, the register is configured as Register 2. Clock Inputs CLK, CLK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). RESET SSTL_18 Input Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. VREF 0.9V nominal Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased Inputsreliability. VDD Power Input Power Supply Voltage GND Ground Input Ground Miscellaneous Inputs 1 Open Drain This range does not include D1, D4, and D7, and their corresponding outputs. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 7 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 Outputs RESET DCS CSR CLK CLK Σ of Inputs = H (D1 - D14)2 PARIN3 H L X ↑ ↓ Even L L H H L X ↑ ↓ Odd L H L H L X ↑ ↓ Even H H L H L X ↑ ↓ Odd H L H H L L ↑ ↓ Even L L H H L L ↑ ↓ Odd L H L H L L ↑ ↓ Even H H L H L L ↑ ↓ Odd H L H H H H ↑ ↓ X X PPOn0 PTYERRn0 H X X L or H L or H X X PPOn0 PTYERRn0 L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L H PPO PTYERR4 1 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2 This range does not include D1, D4, and D7. 3 PARIN arrives one clock cycle (C1 = 0), or two clock cycles (C1 = 1), after the data to which it applies. 4 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 8 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Rating Supply Voltage, VDD -0.5V to 2.5V 1 -0.5V to VDD + 2.5V VO1,2 -0.5V to VDDQ + 0.5V Input Voltage Range, VI Output Voltage Range, Input Clamp Current, IIK ±50mA Output Clamp Current, IOK ±50mA Continuous Output Clamp Current, IO ±50mA Continuous Current through each VDD or GND ±100mA Package Thermal Impedance (θja)3 0m/s Airflow 40°C/W 1m/s Airflow 29°C/W Storage Temperature -65 to +150°C 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. Mode Select C1 Device Mode 0 First device in pair, Front 1 Second device in pair, Back Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V ± 0.1V Min. Max. Units dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 V/ns Parameter dV/dt_Δ1 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Operating Characteristics, TA = 25°C The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol Parameter Min. Typ. Max. Units VDD I/O Supply Voltage 1.7 1.8 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V VTT Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDD V VI Input Voltage VIH AC High-Level Input Voltage 0 VIL Dn, PARIN, AC Low-Level Input Voltage DCS, CSR, DCKEn, DC High-Level Input Voltage DODTn DC Low-Level Input Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage VIL VIH RESET, C1 VREF + 0.25 VREF - 0.25 VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ VICR Common Mode Input Range VID Differential Input Voltage IOH High-Level Output Current -12 IOL Low-Level Output Current 12 IERROL TA CLK, CLK 0.675 1.125 600 PTYERR Low-Level Output Current 25 Operating Free-Air Temperature 0 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 V 10 CONFIDENTIAL V V mV mA mA +70 IDT74SSTUBF32869A °C 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDDQ/VDD = 1.8V ± 0.1V. Symbol Parameter VIK IDD IDDD CIN Typ. VDDQ = 1.7V, IOH = -100μA VDDQ-0.2 VDDQ = 1.7V, IOH = -12mA 1.2 Max. Units -1.2 V V VDDQ = 1.7V, IOL = 100μA 0.2 VDDQ = 1.7V, IOL = 12mA 0.5 PTYERR Output Low Voltage IERROL = 25mA; VDD = 1.7V 0.5 V All Inputs VI = VDD or GND +5 μA Static Standby IO = 0, VDD = 1.9V, RESET = GND VOL IIL Min. II = -18mA VOH VERROL Test Conditions Static Operating -5 μA 200 IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) V 10 mA IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) 120 Dynamic Operating (clock only) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 247 μA/Clock MHz Dynamic Operating (per each data input) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. 52 μA/Clock MHz/ Data Dn, PARIN, DSCn inputs VI = VREF ± 250mV CLK and CLK inputs VICR = 0.9V, VIPP = 600mV RESET VI = VDD or GND 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 3 3.5 4.5 pF 4.5 11 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V ± 0.1V Symbol fCLOCK tW Min. Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW tACT 1 tINACT2 tSU Units 410 MHz 1 ns Differential Inputs Active Time 10 ns Differential Inputs Inactive Time 15 ns Setup Time Hold Time tH Max. DCS before CLK↑, CLK↓, CSR HIGH; CSR before CLK↑, CLK↓, DCS HIGH 0.6 DCS before CLK↑, CLK↓, CSR LOW 0.5 DODT, DOCKE, and data before CLK↑, CLK↓ 0.5 PAR_IN before CLK↑, CLK↓ 0.5 DCS, DODT, DCKE, and data after CLK↑, CLK↓ 0.4 PAR_IN after CLK↑, CLK↓ 0.4 ns ns 1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V ± 0.1V Symbol fMAX tPDM tPD 1 2 tPDMSS 1 Parameter Min. Max Input Clock Frequency 340 Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn 1.1 1.5 ns Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn 0.4 0.8 ns 1.6 ns 3 ns 3 ns 1.6 ns Propagation Delay, simultaneous switching, CLK↑ / CLK↓ to Qn Units MHz tLH LOW to HIGH Propagation Delay, CLK↑ / CLK↓ to PTYERR tHL HIGH to LOW Propagation Delay, CLK↑ / CLK↓ to PTYERR tPD Propagation Delay from CLK↑ / CLK↓ to PPO tPHL HIGH to LOW Propagation Delay, RESET↓ to Qn↓ 3 ns tPLH LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑ 3 ns 1 2 1.2 Max. 0.5 Design target as per JEDEC specifications. Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.) 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 12 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V ± 0.1V Parameter dV/dt_r dV/dt_f dV/dt_Δ 1 Min. Max. Units 1 4 V/ns 1 4 V/ns 1 V/ns 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 13 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU D1 - D14 tH (1) t PD CLK to Q (1) Q1 - Q14 tH tSU PARIN (2) tPD CLK to PPO PPO (2) PTYERR (2) tPD CLK to PTYERR tPD CLK to PTYERR NOTES: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 2.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 14 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU D1 - D14 tH (1) tPD CLK to Q Q1 - Q14 (1) tSU PARIN tH (2) tPD CLK to PPO (2) PPO (not used) PTYERR (2) tPD CLK to PTYERR tPD CLK to PTYERR NOTES: 1.This range does not include D1, D4, and D7, and their corresponding outputs. 2.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 15 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD/2 VDD DUT R L = 1KΩ TL = 50Ω CLK CLK CLK Inputs ZO = 50Ω Test Point ZO = 50Ω Test Point CLK Inputs Test Point CL = 30 pF Test Point CLK TL = 350ps, 50Ω Out DUT RL = 50Ω ZO = 50Ω Out CLK R L = 1KΩ Test Point RL = 100Ω Test Point Production-Test Load Circuit Simulation Load Circuit CLK tPLH VDD LVCMOS RESET Input VDD/2 V ICR V ICR CLK V ID tPHL V OH Output VDD/2 V TT V TT V OL 0V tACT tINACT Voltage Waveforms - Propagation Delay Times 90% IDD 10% LVCMOS RESET Input Voltage and Current Waveforms Inputs Active and Inactive Times VIH VDD/2 VIL tRPHL VOH Output VTT VOL tW Input VICR VICR Voltage Waveforms - Propagation Delay Times VID NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VID VICR CLK tSU tH VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 16 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD DUT VDD DUT RL = 50Ω Out RL = 1KΩ Out Test Point Test Point CL = 10 pF CL = 10 pF Load Circuit: Error Output Measurements Load Circuit: High-to-Low Slew-Rate Adjustment Output LVCMOS RESET Input VOH 80% VCC VCC/2 0V tPLH VOH 20% dv_f 0.15V Output Waveform 2 VOL 0V dt_f Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) Voltage Waveforms: High-to-Low Slew-Rate Adjustment Timing Inputs DUT VICR VICR VI(PP) tHL Out Test Point CL = 10 pF VCC/2 VOL Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) Load Circuit: Low-to-High Slew-Rate Adjustment Timing Inputs dt_r VOH dv_r VCC Output Waveform 1 RL = 50Ω 80% VICR VICR VI(PP) tHL VOH Output Waveform 2 20% Output VOL 0.15V 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) Voltage Waveforms: Low-to-High Slew-Rate Adjustment NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 17 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) DUT Testpoint OUT CL = 5pF (1) RL = 1K Partial Parity Out Load Circuit CLK VICR VI(PP) VICR CLK tPHL tPLH VTT VTT Output Partial Parity Out Voltage Waveform, Propagation Delay Time with Respect to CLK Input VTT = VTT/2 VICR Cross Point Voltage VI(PP) = 600mV tPLH and tPHL are the same as tPD. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 18 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Application Information The typical values below are measured on standard JEDEC raw cards, using the JEDEC DDR2 register validation board running patterns 0x43, 0x4F, and 0x5A. Raw Card Values Raw Card1 tPDMSS Overshoot Undershoot W 1.48 446 444 1 All values are valid under nominal conditions and minimum/maximum of typical signals on one typical DIMM. Measurements include all jitter and ISI effects. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 19 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 TOP VIEW BOTTOM VIEW ∅0.08 M C ∅0.15 M C A B d = ∅0.35 ~ 0.48(150X) A1 CORNER A1 CORNER 1 2 3 4 5 6 7 8 11 10 9 9 10 11 8 7 6 5 4 3 2 b A 0.25 REF 1 A 0.03 REF B B // D 0.20 C C 0.65 C SEATING PLANE C G H D D E F G H J K L M J K D1 11.70 F 13.00 ± 0.05 E L M N N P P R R T T U h = 0.25 ~ 0.37 V 1.20 MAX U V 0.12 C W W 0.65 E T E1 6.50 A 8.00 ± 0.05 B 0.15(4X) c ALL DIMENSIONS IN MILLIMETERS D 13.00 Bsc E 8.00 Bsc T Min/Max 0.90/1.20 e 0.65 Bsc BALL GRID Horiz Vert Total 11 19 150 d Min/Max 0.35/0.48 h Min/Max 0.25/0.37 D1 11.70 Bsc E1 6.50 Bsc REF. DIMS b c 0.65 0.75 NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 20 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Ordering Information IDT74SSTUBF XX Family XX XXX Device Type Package X Shipping Carrier T 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Tape and Reel BKG Low Profile, Fine Pitch, Ball Grid Array 869A 14-Bit Configurable Registered Buffer for DDR2 32 Double Density 21 CONFIDENTIAL IDT74SSTUBF32869A 7093/8 IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA