KODENSHI KK74ACT158N

TECHNICAL DATA
KK74ACT158
Quad 2-Input Data Selector/Multiplexer
High-Speed Silicon-Gate CMOS
The KK74ACT158 is identical in pinout to the LS/ALS138,
HC/HCT138. The KK74ACT158 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device routes 2 nibbles (A or B) to a single port (Y) as
determined by the Select input. The data is presented at the outputs in
invertered form. A high level on the Output Enable input sets all four Y
outputs to a high level.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT158N Plastic
KK74ACT158D SOIC
TA = -40° to 85° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 16 =VCC
PIN 8 = GND
Outputs
Output
Enable
Select
Y0-Y3
H
X
H
L
L
A0-A3
L
H
B0-B3
X=don’t care
A0-A3,B0-B3=the levels of the respective
Data-Word Inputs
1
KK74ACT158
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
tr, tf
*
Parameter
Input Rise and Fall Time
(except Schmitt Inputs)
*
Min
Max
Unit
4.5
5.5
V
0
VCC
V
140
°C
+85
°C
-24
mA
24
mA
10
8.0
ns/V
-40
VCC =4.5 V
VCC =5.5 V
0
0
VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74ACT158
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum HighLevel Output Voltage
IOUT ≤ -50 µA
4.5
5.5
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.76
4.76
4.5
5.5
0.1
0.1
0.1
0.1
VIN= VIH or VIL
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
±0.1
±1.0
µA
*
VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
VOL
Maximum LowLevel Output Voltage
IOUT ≤ 50 µA
V
*
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
∆ICCT
Additional Max.
ICC/Input
VIN=VCC - 2.1 V
5.5
1.5
mA
IOLD
+Minimum Dynamic
Output Current
VOLD=1.65 V Max
5.5
75
mA
IOHD
+Minimum Dynamic
Output Current
VOHD=3.85 V Min
5.5
-75
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
5.5
80
µA
8.0
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
KK74ACT158
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to 85°C
Min
Max
Min
Max
Unit
tPLH
Propagation Delay, Select to Output Y (Figure 2)
2.5
9.5
2.0
11.0
ns
tPHL
Propagation Delay, Select to Output Y (Figure 2)
1.5
9.0
1.5
10.0
ns
tPLH
Propagation Delay, Output Enable to Output Y
(Figure 3)
1.5
9.5
1.5
10.5
ns
tPHL
Propagation Delay, Output Enable to Output Y
(Figure 3)
1.5
9.5
1.5
10.5
ns
tPLH
Propagation Delay, Input A or B to Output Y
(Figure 1)
1.5
8.0
1.0
8.5
ns
tPHL
Propagation Delay, Input A or B to Output Y
(Figure 1)
1.5
6.5
1.0
7.5
ns
CIN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
Figure 1. Switching Waveforms
45
pF
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
4
KK74ACT158
EXPANDED LOGIC DIAGRAM
A0
B0
Y0
A1
B1
Y1
A2
B2
Y2
A3
B3
OE
SELECT
Y3
5
KK74ACT158
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
16
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
B
1
8
5.33
C
F
L
C
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
-T- SEATING
PLANE
N
G
K
M
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
9
H
B
1
G
P
8
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
9.8
10
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.72
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
6