MCNIX MX23L6412

MX23L6412
SEQUENTIAL 64M-BIT MASK ROM
FEATURES
• Bit organization
- 4M x 16 (word mode only)
- 256 words/page
- Total 16K pages
• Sequential access at 200ns cycle time in a page
• Asynchronous chip enable input (ALEH, ALEL)
• Access time
- Read latency time: 950ns
- Read cycle time: 200ns
- RD access time: 150ns
• Current
- Operating:25mA(max.)
- Address input:2mA(max.)
- Standby:20uA(max.)
• Supply voltage
- 3.0V~3.6V
• Package
- 32 pin TSOP
ORDER INFORMATION
Part No.
MX23L6412TC-20
Read Cycle Time
200ns
Package
32 pin TSOP
GENERAL DESCRIPTION
are not used internally. As for low 16 bit address, A1~A8
are through 8 bit address counter, A9~A15 are through 7
bit address register, and A0 are not used internally. High
address input must be done before low address input,
and both address inputs are needed for page change or
address change in a same page. After address inputs,
CE goes high at ALEH falling edge and RD doesn't toggle,
the ROM is in stand-by mode.
The product is a 64M bits (4M x 16) mask ROM
composed of 16K pages, and each consists of 256 words
memory cell array. This mask ROM has a 16 bit address
input / data output bus (AD0~AD15), two address latch
enable pins (high : ALEH, low : ALEL), a read strobe
(RD).
There are 3 modes, Stand-by mode, Active mode, and
Address input mode. Stand-by mode is a non-operating
state, and has the smallest current dissipation. Active
mode is an operating state, and data output is possible.
Address input mode is a state of address input.
After ROM turned into Active mode from Address input
mode, it takes tL time to read. In a page, sequential
read access is possible at tCYC cycle time. Sequential
read operation (increment of internal address counter) is
done at every falling edge of RD. At the end of a page,
internal address counter raps around to the beginning of
the page.
Address input is through AD bus when ALEL is high.
The high and low 16 bit addresses are latched at
ALEH’sand ALEL falling edges. As for high 16 bit address, A0~A6 are through 7 bit address register, A7~A15
P/N:PM0652
REV. 1.5, MAR. 11, 2003
1
MX23L6412
PIN CONFIGURATION
PIN DESCRIPTION
32 TSOP
NC
CE
VSS
AD12
AD13
AD14
AD15
NC
NC
AD0
AD1
AD2
AD3
VCC
ALEL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX23L6412
Symbol
AD0~AD15
ALEH
ALEL
CE
RD
VCC
VSS
NC
NC
RD
VCC
AD11
AD10
AD9
AD8
NC
NC
AD7
AD6
AD5
AD4
VSS
ALEH
NC
Pin Function
Address Input / Data Output
Address Latch Enable High
Address Latch Enable Low
Chip Enable Input
Read Strobe Input
Power Supply Pin
Ground Pin
No Connection
TRUTH TABLE
Mode
Operation
CE
ALEH
ALEL
RD
AD Bus
Address Input
High address input
L
H
H
X
Address input
Address Input
Low address input
X
L
H
X
Address input
Active
Internally active
X
L
L
H
Floating
Active
Data read
X
L
L
L
Data output
Stand-by
Stand-by *
X
H-->L
L
X
Floating
Note: Please see "standby mode" timing diagram.
BLOCK DIAGRAM
RD
ALEH
ALEL
Enable
CE
Reg.
Address
Register
Row Decoder
Address
Register
Output Buffer
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Input Buffer
CE
Memory Cell Array
256 words/ Page
Column Decoder
Address
Presettable
Counter
Enable
Latch x 16
Clock
P/N:PM0652
REV. 1.5, MAR. 11, 2003
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MX23L6412
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
Symbol
VIN
Topr
Tstg
Ratings
-0.5V to 4.6V
0° C to 70° C
-55° C to 125° C
DC CHARACTERISTICS (Ta = 0° C~70° C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Address Input Current
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ICC2
MIN.
2.0V
2.0V
-0.5V
-10uA
-10uA
-
MAX.
0.4V
VCC+0.5V
0.8V
10uA
10uA
25mA
2mA
Standby Current (CMOS)
ISTB
-
20uA
Input Capacitance
Output Capacitance
CIN
COUT
-
12pF
12pF
Conditions
IOH = -0.4mA
IOL = 2mA
VIN = 0V to 3.6V
VOUT = 0V to 3.6V
Cycle = 200ns, VIN = VIH or VIL, active mode
Cycle = 100ns, VIN = VIH or VIL, address
input mode
Cycle = 200ns, VIN = VCC±
±0.3V or
0V±
±0.3V,stand-by mode
Ta = 25° C, f = 5MHz, VIN = 0V
Ta = 25° C, f = 5MHz, VOUT = 0V
AC CHARACTERISTICS (Ta = 0° C~70° C, VCC = 3.3V±10%)
Item
ALEL Setup Time
ALE Delay Time
Address Setup Time
Address Hold Time
Read Latency Time
Read Cycle Time
CE Setup Time
CE Hold Time
RD Access Time
RD High Time
Output Hold Time
Output Float Time
Release Time
Symbol
tALES
tALED
tAS
tAH
tL
tCYC
tCES
tCEH
tRD
tRDH
tOH
tDF
tR
MIN.
70ns
70ns
30ns
0
950ns
200ns
50ns
0ns
MAX.
Conditions
150ns
50ns
0
40ns
0
P/N:PM0652
REV. 1.5, MAR. 11, 2003
3
MX23L6412
TIMING DIAGRAM
Address Input Mode and Active Mode
Address Input Mode
Active Mode
ALEH
tALES
tALED
tL
ALEL
tCYC
tCES
CE
tCEH
tR
tRDH
RD
tAS tAH
AD[0:15]
AH
tOH
tRD
AL
D0
D1
AH
DN
tDF
Standby Mode
Active Mode
CE Latch
Standby Mode
(1)
tALED
ALEL
tALES
ALEH
tCEH
CE
tCES
Active Mode
(2)
CE Latch
Standby Mode
ALEL
(Low)
tALES
ALEH
CE
P/N:PM0652
REV. 1.5, MAR. 11, 2003
4
MX23L6412
AC Test Conditions
2.4V
2.4V
TEST POINTS
INPUT
0.4V
0.4V
2.0V
2.0V
TEST POINTS
OUTPUT
0.8V
0.8V
* Input Rise and Fall Times : <10ns
* Output Load : 1TTL+100pF (without active current loading)
P/N:PM0652
REV. 1.5, MAR. 11, 2003
5
MX23L6412
PACKAGE INFORMATION
P/N:PM0652
REV. 1.5, MAR. 11, 2003
6
MX23L6412
REVISION HISTORY
REVISION
1.1
1.2
1.3
1.4
1.5
DESCRIPTION
To revise the CE setup time tCES as 50ns(min.) instead of 30ns
Modify Access time--Read latency time:1000ns--->950
Add Package Information
Change Standby Current:500uA(max.)--->20uA(max.)
Add Standby Mode Timing Diagram
To modify Package Information
P/N:PM0652
PAGE
P3
P1,3
P5
P1,3
P2,4
P6
DATE
JUL/26/1999
OCT/13/2000
AUG/17/2001
FEB/20/2002
MAR/11/2003
REV. 1.5, MAR. 11, 2003
7
MX23L6412
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-6688
FAX:+886-3-563-2888
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TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.