NEC UPD4218165LG5-A50-7JF

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD42S18165L, 4218165L
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE
Description
The µPD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S18165L can execute CAS before RAS self refresh.
The µPD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 1,048,576 words by 16 bits organization
• Single +3.3 V ±0.3 V power supply
• Fast access and cycle time
Part number
Power consumption
Active (MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
EDO (Hyper page mode)
cycle time (MIN.)
µPD42S18165L-A50, 4218165L-A50
612 mW
50 ns
84 ns
20 ns
µPD42S18165L-A60, 4218165L-A60
540 mW
60 ns
104 ns
25 ns
µPD42S18165L-A70, 4218165L-A70
504 mW
70 ns
124 ns
30 ns
• The µPD42S18165L can execute CAS before RAS self refresh
Part number
Refresh cycle
Refresh
Power consumption at standby
(MAX.)
µPD42S18165L
1,024 cycles/128 ms
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
0.54 mW
(CMOS level input)
µPD4218165L
1,024 cycles/16 ms
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10562EJ8V0DS00 (8th edition)
Date Published January 1997 N
Printed in Japan
The mark
shows major revised points.
©
1995
µPD42S18165L, 4218165L
Ordering Information
2
Part number
Access time
(MAX.)
µPD42S18165LG5-A50-7JF
50 ns
µPD42S18165LG5-A60-7JF
60 ns
µPD42S18165LG5-A70-7JF
70 ns
µPD42S18165LLE-A50
50 ns
µPD42S18165LLE-A60
60 ns
µPD42S18165LLE-A70
70 ns
µPD4218165LG5-A50-7JF
50 ns
µPD4218165LG5-A60-7JF
60 ns
µPD4218165LG5-A70-7JF
70 ns
µPD4218165LLE-A50
50 ns
µPD4218165LLE-A60
60 ns
µPD4218165LLE-A70
70 ns
Package
50-pin plastic TSOP (II)
(400 mil)
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
42-pin plastic SOJ
(400 mil)
50-pin plastic TSOP (II)
(400 mil)
42-pin plastic SOJ
(400 mil)
CAS before RAS refresh
RAS only refresh
Hidden refresh
µPD42S18165L, 4218165L
Pin Configurations (Marking Side)
50-pin Plastic TSOP (II) (400 mil)
42-pin Plastic SOJ (400 mil)
50
GND
VCC
1
42
GND
I/O1
2
49
I/O16
I/O1
2
41
I/O16
I/O2
3
48
I/O15
I/O2
3
40
I/O15
I/O3
4
47
I/O14
I/O3
4
39
I/O14
I/O4
5
46
I/O13
I/O4
5
38
I/O13
VCC
6
45
GND
VCC
6
37
GND
I/O5
7
44
I/O12
I/O5
7
36
I/O12
I/O6
8
43
I/O11
I/O6
8
35
I/O11
I/O7
9
42
I/O10
I/O7
9
34
I/O10
I/O8
10
41
I/O9
I/O8
10
33
I/O9
NC
11
40
NC
NC
11
32
NC
31
LCAS
30
UCAS
NC
12
WE
13
µ PD42S18165LLE
µ PD4218165LLE
1
µ PD42S18165LG5-7JF
µ PD4218165LG5-7JF
VCC
RAS
14
29
OE
36
NC
NC
15
28
A9
35
LCAS
NC
16
27
A8
34
UCAS
A0
17
26
A7
18
33
OE
A1
18
25
A6
NC
19
32
A9
A2
19
24
A5
NC
20
31
A8
A3
20
23
A4
A0
21
30
A7
VCC
21
22
GND
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VCC
25
26
GND
NC
15
NC
16
WE
17
RAS
A0 to A9
: Address Inputs
I/O1 to I/O16
: Data Inputs/Outputs
RAS
: Row Address Strobe
UCAS
: Column Address Strobe (upper)
LCAS
: Column Address Strobe (lower)
WE
: Write Enable
OE
: Output Enable
V CC
: Power Supply
GND
: Ground
NC
: No Connection
3
µPD42S18165L, 4218165L
Block Diagram
RAS
LCAS
UCAS
WE
Lower
Byte
Control
Clock Generator
OE
Data
Output
Buffer
Upper
Byte
Control
VCC
A0
to
A9
CAS before
RAS Counter
Row
Address
Buffer
Column
Address
Buffer
X0 to X9
1,024
Data
Input
Buffer
Row Decoder
GND
Memory
Cell
Array
1,024 × 1,024 × 16
Data
Output
Buffer
1,024 × 16
Y0 to Y9
Sense Amplifier
1,024
Column Decoder
4
I/O1
to
I/O8
(Lower Byte)
I/O9
to
I/O16
(Upper Byte)
× 16
Data
Input
Buffer
µPD42S18165L, 4218165L
Input/Output Pin Functions
The µPD42S18165L, 4218165L have input pins RAS, CASNote, WE, OE, A0 to A9 and input/output pins I/O1 to
I/O16.
Pin name
RAS
(Row address strobe)
Input/Output
Input
Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
CAS
(Column address strobe)
CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
A0 to A9
(Address inputs)
Address bus.
Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence
(address multiplex method).
Therefore, one word is selected from 1,048,576-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)
Write control signal.
OE
(Output enable)
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
I/O1 to I/O16
(Data inputs/outputs)
Note
Write operation is executed by activating RAS, CAS and WE.
Input/Output
16-bit data bus.
I/O1 to I/O16 are used to input/output data.
CAS means UCAS and LCAS.
5
µPD42S18165L, 4218165L
Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle’s falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
RAS
VIH –
VIL –
tOFR
tHPC
CAS
VIH –
VIL –
tOFC
Address
VIH –
VIL –
Row
Col.A
Col.B
tRAC
tAA
tCAC
WE
tRCH
tAA
tCAC
tAA
tCAC
tWPZ
tRRH
VIH –
VIL –
tOCH
tCHO
tOCH
tOEP
tOEP
tOEA
OE
Col.C
tOEA
tWEZ
tCHO
VIH –
VIL –
tOLZ
tDHC
tCLZ
I/O
6
VOH –
VOL –
Hi - Z
Data out A
tOEZ
Data out B
tCLZ
tOEZ
Data out C
tOEZ
Data out C
Hi - Z
µPD42S18165L, 4218165L
Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate t HPC at the MIN. value.
2. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
t OFC is effective when RAS is inactivated before CAS is inactivated.
t OFR is effective when CAS is inactivated before RAS is inactivated.
The slower of t OFC and tOFR becomes effective.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ····· t OEZ is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either t RRH or t RCH must be met ····· t WEZ and t WPZ are effective.
The faster of t OEZ and t WEZ becomes effective.
The faster of (1) and (2) becomes effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ····· t CHO is effective.
(2) CAS, OE: active ····· t OCH is effective.
7
µPD42S18165L, 4218165L
Electrical Specifications
• CAS means UCAS and LCAS.
• All voltages are referenced to GND.
• After power up (V CC ≥ V CC(MIN.)), wait more than 100 µ s (RAS, CAS inactive) and then, execute eight CAS
before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
–0.5 to +4.6
V
Supply voltage
VCC
–0.5 to +4.6
V
Output current
IO
20
mA
Power dissipation
PD
1
W
Operating ambient temperature
TA
0 to +70
˚C
Storage temperature
Tstg
–55 to +125
˚C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.3
3.6
V
Supply voltage
VCC
3.0
High level input voltage
VIH
2.0
VCC + 0.3
V
Low level input voltage
VIL
–0.3
+0.8
V
Operating ambient temperature
TA
0
70
˚C
MAX.
Unit
pF
Capacitance (TA = 25 ˚C, f = 1 MHZ)
Parameter
Input capacitance
Data input/output capacitance
8
Symbol
Test condition
MIN.
TYP.
CI1
Address
5
CI2
RAS, CAS, WE, OE
7
CI/O
I/O
7
pF
µPD42S18165L, 4218165L
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Symbol
Operating current
Standby
µPD42S18165L
ICC1
ICC2
current
µPD4218165L
RAS only refresh current
Operating current
ICC3
ICC4
(Hyper page mode (EDO))
CAS before RAS
ICC5
refresh current
CAS before RAS
ICC6
long refresh current
(1,024 cycles / 128 ms,
only for the µPD42S18165L)
Test condition
MIN.
MAX.
Unit
Notes
mA
1, 2, 3
RAS, CAS cycling
tRAC = 50 ns
170
tRC = tRC (MIN.), IO = 0 mA
tRAC = 60 ns
150
tRAC = 70 ns
140
RAS, CAS ≥ VIH (MIN.), IO = 0 mA
0.5
RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA
0.15
RAS, CAS ≥ VIH (MIN.), IO = 0 mA
2.0
RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA
0.5
RAS cycling, CAS ≥ VIH (MIN.)
tRAC = 50 ns
170
tRC = tRC (MIN.), IO = 0 mA
tRAC = 60 ns
150
tRAC = 70 ns
140
RAS ≤ VIL (MAX.), CAS cycling
tRAC = 50 ns
120
tHPC = tHPC (MIN.), IO = 0 mA
tRAC = 60 ns
110
tRAC = 70 ns
100
RAS cycling
tRAC = 50 ns
170
tRC = tRC (MIN.) , IO = 0 mA
tRAC = 60 ns
150
tRAC = 70 ns
140
CAS before RAS refresh :
tRC = 125.0 µs
RAS, CAS:
VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
tRAS ≤ 300 ns
Standby:
RAS, CAS ≥ VCC – 0.2 V
Address: VIH or VIL
WE, OE: VIH
IO = 0 mA
tRAS ≤ 1 µs
mA
mA
1, 2, 3 ,4
mA
1, 2, 5
mA
1, 2
300
µA
1, 2
400
µA
1, 2
200
µA
2
CAS before RAS
self refresh current
(only for the µPD42S18165L)
ICC7
RAS, CAS :
tRASS = 5 ms
VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
IO = 0 mA
Input leakage current
II (L)
VI = 0 to 3.6 V
All other pins not under test = 0 V
–5
+5
µA
Output leakage current
IO (L)
VO = 0 to 3.6 V
Output is disabled (Hi-Z)
–5
+5
µA
High level output voltage
VOH
IO = –2.0 mA
2.4
Low level output voltage
VOL
IO = +2.0 mA
V
0.4
V
Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS ≤ VIL (MAX.)
and CAS ≥ VIH (MIN.).
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.
9
µPD42S18165L, 4218165L
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
(2) Output timing specification
VIH (MIN.) = 2.0 V
VOH (MIN.) = 2.0 V
VIL (MAX.) = 0.8 V
VOL (MAX.) = 0.8 V
tT = 2 ns
tT = 2 ns
(3) Output load condition
VCC
1,180 Ω
I/O
100 pF
CL
870 Ω
Common to Read, Write, Read Modify Write Cycle
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
Read / Write cycle time
tRC
84
–
104
–
124
–
ns
RAS precharge time
tRP
30
–
40
–
50
–
ns
CAS precharge time
tCPN
8
–
10
–
10
–
ns
RAS pulse width
tRAS
50
10,000
60
10,000
70
10,000
ns
CAS pulse width
tCAS
8
10,000
10
10,000
12
10,000
ns
RAS hold time
tRSH
10
–
10
–
12
–
ns
CAS hold time
tCSH
38
–
40
–
50
–
ns
RAS to CAS delay time
tRCD
11
37
14
45
14
52
ns
2
RAS to column address delay time
tRAD
9
25
12
30
12
35
ns
2
CAS to RAS precharge time
tCRP
5
–
5
–
5
–
ns
3
Row address setup time
tASR
0
–
0
–
0
–
ns
Row address hold time
tRAH
7
–
10
–
10
–
ns
Column address setup time
tASC
0
–
0
–
0
–
ns
Column address hold time
tCAH
7
–
10
–
12
–
ns
OE lead time referenced to RAS
tOES
0
–
0
–
0
–
ns
CAS to data setup time
tCLZ
0
–
0
–
0
–
ns
OE to data setup time
tOLZ
0
–
0
–
0
–
ns
OE to data delay time
tOED
10
–
13
–
15
–
ns
Masked byte write hold time referenced to RAS
tMRH
0
–
0
–
0
–
ns
tT
1
50
1
50
1
50
ns
tREF
–
128
–
128
–
128
ms
–
16
–
16
–
16
ms
Transition time (rise and fall)
Refresh time
µPD42S18165L
µPD4218165L
10
1
4
µPD42S18165L, 4218165L
Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 µs.
If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tAA (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the µPD42S18165L.
Read Cycle
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
Access time from RAS
tRAC
–
50
–
60
–
70
ns
1
Access time from CAS
tCAC
–
15
–
17
–
18
ns
1
Access time from column address
tAA
–
25
–
30
–
35
ns
1
Access time from OE
tOEA
–
13
–
15
–
18
ns
Column address lead time referenced to RAS
tRAL
25
–
30
–
35
–
ns
Read command setup time
tRCS
0
–
0
–
0
–
ns
Read command hold time referenced to RAS
tRRH
0
–
0
–
0
–
ns
Read command hold time referenced to CAS
tRCH
0
–
0
–
0
–
ns
2
Output buffer turn-off delay time from OE
tOEZ
0
10
0
13
0
15
ns
3
CAS hold time to OE
t CHO
5
–
5
–
5
–
ns
4
2
Notes 1. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tAA (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.
4. WE: inactive (in read cycle)
CAS: inactive, OE: active ····· tCHO is effective.
CAS, OE: active ····· tOCH is effective.
11
µPD42S18165L, 4218165L
Write Cycle
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
WE hold time referenced to CAS
tWCH
7
–
10
–
10
–
ns
1
WE pulse width
tWP
8
–
10
–
10
–
ns
1
WE lead time referenced to RAS
tRWL
10
–
10
–
12
–
ns
WE lead time referenced to CAS
tCWL
8
–
10
–
12
–
ns
WE setup time
tWCS
0
–
0
–
0
–
ns
OE hold time
tOEH
0
–
0
–
0
–
ns
Data-in setup time
tDS
0
–
0
–
0
–
ns
3
Data-in hold time
tDH
7
–
10
–
10
–
ns
3
2
Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
Read modify write cycle time
tRWC
107
–
133
–
157
–
ns
RAS to WE delay time
tRWD
64
–
77
–
89
–
ns
1
CAS to WE delay time
tCWD
27
–
32
–
37
–
ns
1
Column address to WE delay time
tAWD
39
–
47
–
54
–
ns
1
Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
12
µPD42S18165L, 4218165L
Hyper Page Mode (EDO)
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
Read / Write cycle time
tHPC
20
–
25
–
30
–
ns
RAS pulse width
tRASP
50
125,000
60
125,000
70
125,000
ns
CAS pulse width
tHCAS
8
10,000
10
10,000
12
10,000
ns
CAS precharge time
tCP
8
–
10
–
10
–
ns
Access time from CAS precharge
tACP
–
30
–
35
–
40
ns
CAS precharge to WE delay time
tCPWD
41
–
52
–
59
–
ns
RAS hold time from CAS precharge
tRHCP
30
–
35
–
40
–
ns
tHPRWC
52
–
66
–
75
–
ns
Data output hold time
tDHC
5
–
5
–
5
–
ns
OE to CAS hold time
tOCH
5
–
5
–
5
–
ns
OE precharge time
tOEP
5
–
5
–
5
–
ns
Output buffer turn-off delay from WE
tWEZ
0
10
0
13
0
15
ns
4,5
WE pulse width
tWPZ
7
–
10
–
10
–
ns
5
Output buffer turn-off delay from RAS
tOFR
0
10
0
13
0
15
ns
4,5
Output buffer turn-off delay from CAS
tOFC
0
10
0
13
0
15
ns
4,5
Read modify write cycle time
1
2
3
Notes 1. tHPC (MIN.) is applied to CAS access.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. WE: inactive (in read cycle)
CAS: inactive, OE: active ······ tCHO is effective.
CAS, OE: active ······ tOCH is effective.
4. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
5. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)
Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
The slower of tOFC and tOFR becomes effective.
(2)
Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ······ tOEZ is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ······ tWEZ and tWPZ are effective.
The faster of tOEZ and tWEZ becomes effective.
The faster of (1) and (2) becomes effective.
13
µPD42S18165L, 4218165L
Refresh Cycle
Parameter
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit Notes
CAS setup time
tCSR
5
–
5
–
5
–
ns
CAS hold time (CAS before RAS refresh)
tCHR
10
–
10
–
10
–
ns
RAS precharge CAS hold time
tRPC
5
–
5
–
5
–
ns
RAS pulse width (CAS before RAS self refresh)
tRASS
100
–
100
–
100
–
µs
1
RAS precharge time (CAS before RAS self refresh)
tRPS
90
–
110
–
130
–
ns
1
CAS hold time (CAS before RAS self refresh)
tCHS
–50
–
–50
–
–50
–
ns
1
WE hold time
tWHR
15
–
15
–
15
–
ns
Note 1. This specification is applied only to the µPD42S18165L.
14
µPD42S18165L, 4218165L
Read Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
tCRP
UCAS
LCAS
tRCD
tRSH
tCAS
VIH –
VIL –
tRAD
tASR
Address
tCPN
VIH –
VIL –
tRAH
tRAL
tCAH
tASC
Row
Col.
tRCH
tRCS
WE
tRRH
VIH –
VIL –
tWPZ
tOCH
tOES
tCHO
tWEZ
tOEA
OE
VIH –
VIL –
tRAC
tAA
tCAC
tOLZ
tCLZ
U I/O
L I/O
VOH –
VOL –
Hi - Z
tOFC
tOEZ
tOFR
Data out
Hi - Z
15
µPD42S18165L, 4218165L
Upper Byte Read Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
tCRP
UCAS
tRCD
tRSH
tCAS
tCPN
VIH –
VIL –
tCRP
LCAS
tMRH
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRAH
tRAL
tCAH
tASC
Row
Col.
tRCH
tRCS
WE
tRRH
VIH –
VIL –
tWPZ
tOCH
tOES
tOEA
OE
tCHO
tWEZ
VIH –
VIL –
tRAC
tAA
tCAC
tOLZ
tOFC
tOEZ
tOFR
tCLZ
U I/O
VOH –
VOL –
Remark L I/O: Hi-Z
16
Hi - Z
Data out
Hi - Z
µPD42S18165L, 4218165L
Lower Byte Read Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCRP
UCAS
tMRH
VIH –
VIL –
tCSH
tCRP
LCAS
tRCD
tRSH
tCAS
VIH –
VIL –
tRAD
tASR
Address
tCPN
VIH –
VIL –
tRAH
tRAL
tCAH
tASC
Row
Col.
tRCH
tRCS
WE
tRRH
VIH –
VIL –
tWPZ
tOCH
tOES
tOEA
OE
tCHO
tWEZ
VIH –
VIL –
tRAC
tAA
tCAC
tOLZ
tOFC
tOEZ
tOFR
tCLZ
L I/O
VOH –
VOL –
Hi - Z
Data out
Hi - Z
Remark U I/O: Hi-Z
17
µPD42S18165L, 4218165L
Early Write Cycle
tRC
tRP
tRAS
RAS
VIH–
VIL–
tCSH
tCRP
UCAS
LCAS
tRSH
tRCD
tCAS
VIH–
VIL–
tRAD
tASR
Address
WE
U I/O
L I/O
VIH–
VIL–
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
tDH
VIH–
VIL–
VIH–
VIL–
Remark OE: Don’t care
18
tRAH
Data in
tCPN
µPD42S18165L, 4218165L
Upper Byte Early Write Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
tRCD
tCRP
UCAS
VIH –
VIL –
tCRP
LCAS
tMRH
VIH –
VIL –
tASR
Address
VIH –
VIL –
WE
VIH –
VIL –
tRAD
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
U I/O
tCPN
tRSH
tCAS
VIH –
VIL –
tDH
Data in
Remark OE, L I/O: Don’t care
19
µPD42S18165L, 4218165L
Lower Byte Early Write Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCRP
UCAS
tMRH
VIH –
VIL –
tCSH
tCRP
LCAS
tRCD
tRSH
tCAS
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
WE
VIH –
VIL –
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
L I/O
VIH –
VIL –
Remark OE, U I/O: Don’t care
20
tDH
Data in
tCPN
µPD42S18165L, 4218165L
Late Write Cycle
t RC
t RAS
RAS
t RP
VIH–
VIL–
t CSH
t CRP
UCAS
LCAS
t RCD
t RSH
t CPN
t CAS
VIH–
VIL–
t RAD
t ASR
Address
VIH–
VIL–
t RAH
t ASC
Row
t CAH
Col.
t CWL
t RWL
t RCS
WE
t WP
VIH–
VIL–
t OEH
OE
VIH–
VIL–
t OED
U I/O
L I/O
VIH–
VIL–
Hi-Z
t DS
t DH
Data in
21
µPD42S18165L, 4218165L
Upper Byte Late Write Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
tCRP
tRCD
tRSH
tCPN
tCAS
UCAS
VIH –
VIL –
tCRP
LCAS
tMRH
VIH –
VIL –
tRAD
tRAH
tASR
Address
VIH –
VIL –
tASC
Row
tCAH
Col.
tCWL
tRWL
tRCS
WE
tWP
VIH –
VIL –
tOEH
OE
VIH –
VIL –
tOED
U I/O
VIH –
VIL –
Remark L I/O: Don’t care
22
tDS
tDH
Hi - Z
Data in
µPD42S18165L, 4218165L
Lower Byte Late Write Cycle
tRC
tRAS
RAS
tRP
VIH –
VIL –
tCRP
UCAS
tMRH
VIH –
VIL –
tCSH
tCRP
LCAS
tRCD
VIH –
VIL –
tCPN
tCAS
VIH –
VIL –
tRAD
tRAH
tASR
Address
tRSH
tASC
Row
tCAH
Col.
tCWL
tRWL
tRCS
WE
tWP
VIH –
VIL –
tOEH
OE
VIH –
VIL –
tOED
L I/O
VIH –
VIL –
Hi - Z
tDS
tDH
Data in
Remark U I/O: Don’t care
23
µPD42S18165L, 4218165L
Read Modify Write Cycle
t RWC
t RAS
RAS
t RP
VIH–
VIL–
t CSH
t CRP
UCAS
LCAS
t RCD
t RSH
t CPN
t CAS
VIH–
VIL–
t RAD
t ASR
Address
VIH–
VIL–
t RAH
t ASC
Row
t CAH
Col.
t RWD
t AWD
t CWD
t RCS
WE
t CWL
t RWL
t WP
VIH–
VIL–
t OEA
OE
VIH–
VIL–
t RAC
t AA
t CAC
U I/O
L I/O
t OEH
t OED
VIH–
VIL–
t DS
t DH
Data in
t OLZ
t CLZ
U I/O VOH–
L I/O VOL–
24
Hi-Z
t OEZ
Data out
Hi-Z
µPD42S18165L, 4218165L
Upper Byte Read Modify Write Cycle
tRWC
tRAS
RAS
tRP
VIH –
VIL –
tCSH
tCRP
UCAS
tRCD
tCPN
tRSH
tCAS
VIH –
VIL –
tCRP
LCAS
tMRH
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRAH
tASC
Row
tCAH
Col.
tRWD
tAWD
tCWD
tRCS
WE
tCWL
tRWL
tWP
VIH –
VIL –
tOEA
OE
VIH –
VIL –
tRAC
tAA
tCAC
U I/O
tOEH
tOED tDS
VIH –
VIL –
tDH
Data in
tOLZ
tCLZ
U I/O
VOH –
VOL –
Hi - Z
tOEZ
Data out
Hi - Z
Remark In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z.
25
µPD42S18165L, 4218165L
Lower Byte Read Modify Write Cycle
tRWC
tRAS
RAS
tRP
VIH –
VIL –
tCRP
UCAS
tMRH
VIH –
VIL –
tCSH
tCRP
tRCD
tCPN
tRSH
tCAS
LCAS
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRAH
tASC
Row
tCAH
Col.
tRWD
tAWD
tCWD
tRCS
WE
tCWL
tRWL
tWP
VIH –
VIL –
tOEA
OE
VIH –
VIL –
tRAC
tAA
tCAC
L I/O
tOEH
tOED tDS
VIH –
VIL –
tDH
Data in
tOLZ
tCLZ
L I/O
VOH –
VOL –
Hi - Z
tOEZ
Data out
Hi - Z
Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.
26
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Read Cycle
tRASP
RAS
VIH –
VIL –
tCSH
tCRP
UCAS
LCAS
tRCD
tRSH
tHCAS
tHPC
tHCAS
tCP
tHCAS
tCP
VIH –
VIL –
tRAD
tRAH tASC
Row
tCAH
tASC
Col.
tCAH
Col.
tRAL
tCAH
tASC
tOFR
tOFC
Col.
tRCH
tRRH
tRCS
WE
tCPN
VIH –
VIL –
tASR
Address
tRP
tRHCP
tWPZ
VIH –
VIL –
tWEZ
tACP
tAA
tCAC
tOCH
OE
tOEA
tOLZ
VIH –
VIL –
tRAC
tAA
tCAC
tCLZ
U I/O
L I/O
VOH –
VOL –
Hi - Z
tDHC
Data out
tACP
tAA
tCAC
tDHC
Data out
tCHO
tOEZ
Data out
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
27
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Byte Read Cycle
tRASP
tRP
tRHCP
VIH –
RAS VIL –
tHPC
tCSH
tCRP
UCAS
tRCD
tCP
tHCAS
tCP
tMRH
VIH –
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRAL
tRAH
tASC
Row
tASC
tCAH
Col.
tCAH
Col.
tASC
tCAH
tOFR
tOFC
Col.
tRCH
tRRH tWPZ
tRCS
WE
tCPN
VIH –
VIL –
tCRP
LCAS
tRSH
tHCAS
tHCAS
VIH –
VIL –
tWEZ
tACP
tAA
tCAC
tOCH
OE
tOEA
tOLZ
VIH –
VIL –
tRAC
tAA
tCAC
tCLZ
U I/O
VOH –
VOL –
tACP
tAA
tCAC
tCHO
tCLZ
tDHC
tOEZ
Hi - Z
Data out
Data out
tDHC
L I/O
VOH –
VOL –
Hi - Z
Data out
Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
28
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Read Cycle (WE Control)
t RASP
RAS
t RP
t RHCP
VIH –
VIL –
t RSH
t HCAS
t CSH
t CRP
UCAS
LCAS
t HCAS
t HCAS
t CPN
VIH –
VIL –
t ASR
Address
t RCD
VIH –
VIL –
t RAD
t RAH t ASC
Row
Col.
t RAL
t ASC
tCAH
t ASC
t CAH
Col.
tCAH
Col.
t RCH
t WPZ
t RCS
WE
t RCS
t RCH
t RCH
t WPZ
t RRH
t RCS
t WPZ
VIH –
VIL –
t OCH
tCHO
t OEA
tWEZ
t OLZ
OE
VIH –
VIL –
t RAC
t AA
t CAC
t CLZ
U I/O
L I/O
VOH –
VOL –
Hi - Z
t OFR
t AA
t CAC
t CLZ
t WEZ
Data out
t OFC
t AA
Hi - Z
t WEZ
t CAC
t OEZ
t CLZ
Data out
Hi - Z
Data out
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
29
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Read Cycle (OE Control)
tRASP
RAS
tRP
tRHCP
VIH –
VIL –
tCSH
tCRP
tRSH
tHPC
tRCD
tHCAS
tCP
tHCAS
tCP
tHCAS
tCPN
UCAS VIH –
LCAS VIL –
tRAD
tASR
Address
VIH –
VIL –
tRAH
Row
WE
tASC
tCAH
tASC
Col.A
tRCS
tASC
tCAH
Col.B
tRAC
tAA
tCAC
VIH –
VIL –
Col.C
tRCH
tOES
tCHO
tOEA
tOFR
tCAH
tAA
tCAC
tRRH
tCAC
tAA
tOCH
tOCH
OE
tOFC
tRAL
tCHO
tACP
tACP
tOEP
tOEP
tOEP
tOCH
tCHO
VIH –
VIL –
tCLZ
U I/O VOH –
L I/O VOL –
Hi - Z
tOEA
tOLZ
tOEA
tOLZ
tOLZ
tOEZ
Data out A
tCLZ
tOEZ
Data out B
tOEZ
Data out B
tOEZ
Data out C
Hi - Z
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
30
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Early Write Cycle
tRASP
RAS
tRP
VIH–
VIL–
tRHCP
tCSH
tCRP
UCAS
LCAS
tHPC
tRCD
tHCAS
tCP
tHCAS
tRSH
tCP
tHCAS
VIH–
VIL–
tRAL
tRAD
tASR
Address
VIH–
VIL–
WE
VIH–
VIL–
U I/O
L I/O
tCPN
tRAH
tASC
Row
tCAH
tASC
Col.
tASC
Col.
tWCS
tWCH
tDS
tDH
VIH–
VIL–
tCAH
Data in
tWCS
tDS
tCAH
Col.
tWCH
tWCS
tWCH
tDH
tDS
tDH
Data in
Data in
Remarks 1. OE: Don’t care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
31
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Byte Early Write Cycle
tRP
tRASP
RAS
tRHCP
VIH–
VIL–
tCSH
tCRP
UCAS
tHPC
tRCD
tCP
WE
U I/O
VIH–
VIL–
tRAD
tRAH
tASC
Row
tCAH
tASC
Col.
tCP
tMRH
tCAH
tWCS
tWCH
tDS
tDH
tWCS
tRAL
tCAH
tASC
Col.
Col.
tWCH
tWCS
tWCH
VIH–
VIL–
VIH–
VIL–
tDS
Data in
tDH
Data in
tDS
L I/O
tHCAS
VIH–
VIL–
tASR
Address
tCPN
VIH–
VIL–
tCRP
LCAS
tRSH
tHCAS
tHCAS
VIH–
VIL–
tDH
Data in
Remarks 1. OE: Don’t care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
32
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Late Write Cycle
t RASP
RAS
VIH–
VIL–
t CSH
t CRP
UCAS
LCAS
t RP
t RHCP
t RCD
t HCAS
t HPC
t HCAS
t CP
t RSH
t HCAS
t CP
VIH–
VIL–
t RAD
t ASR t RAH
Address
VIH–
VIL–
t RAL
t ASC
Row
t CAH
t ASC
Col.
t RCS
Col.
t WP
Col.
t RCS
t WP
t CWL
t RWL
t RCS
t WP
VIH–
VIL–
t OEH
t OEH
VIH–
VIL–
t OED
U I/O
L I/O
t CAH
t CWL
t OEH
OE
t ASC
t CAH
t CWL
WE
t CPN
VIH–
VIL–
Hi-Z
t DS
t DH
Data in
t OED
Hi-Z
t DS
t DH
Data in
t OED
Hi-Z
t DS
t DH
Data in
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
33
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Byte Late Write Cycle
tRP
tRASP
tRHCP
RAS
VIH–
VIL–
UCAS
tHPC
tCSH
tCRP
tRCD
tCP
tHCAS
tCP
tMRH
VIH–
VIL–
tRAD
tASR
Address
VIH–
VIL–
tRAH
tASC
Row
tASC
tCAH
Col.
tCAH
tRCS
tWP
tCWL
tRWL
tRCS
tWP
tRCS
tWP
VIH–
VIL–
tOEH
tOEH
VIH–
VIL–
tOED
U I/O
Col.
tCWL
tOEH
OE
tRAL
tCAH
tASC
Col.
tCWL
WE
tCPN
VIH–
VIL–
tCRP
LCAS
tRSH
tHCAS
tHCAS
VIH–
VIL–
Hi - Z
Hi - Z
tDH
Data in
tOED
VIH–
L I/O
VIL–
tDS
tOED
tOED
Hi - Z
tOED
Hi - Z
Hi - Z
tDS
tDH
Data in
tDS
tDH
Data in
tOED
Hi - Z
Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
34
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Read Modify Write Cycle
t RASP
RAS
VIH–
VIL–
t CRP
UCAS
LCAS
t RP
t HPRWC
t HCAS
t RCD
t CP
t HCAS
t CP
t HCAS
t RAD
t ASR t RAH
Address
VIH–
VIL–
t RAL
t ASC
Row
t CAH
t ASC
t ACP
t RWD
t AWD
t CWD
t CWL
t WP t RCS
t CAH
Col.
t ACP
t CPWD
t AWD
t CWD
t CWL
t WP
t RCS
t CWL
t RWL
t WP
t CPWD
t AWD
t CWD
VIH–
VIL–
t AA
t CAC
t OEH
t OEA
t AA
t CAC
t OEH
t OEH
t CAC
t OEA
t OEA
VIH–
VIL–
t CLZ
t OLZ
U I/O VOH–
L I/O VOL–
Hi-Z
t CLZ
t OED
t OEZ
VIH–
VIL–
t OED
out
t CLZ
t OEZ
t OLZ
Hi-Z
t DS
U I/O
L I/O
t ASC
Col.
t RAC
t AA
OE
t CAH
Col.
t RCS
WE
t CPN
VIH–
VIL–
t OLZ
Hi-Z
out
t DH
in
t DS
t DH
in
t OED
t OEZ
Hi-Z
out
t DS
t DH
in
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
35
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Byte Read Modify Write Cycle
tRP
tRASP
RAS
VIH–
VIL–
tCRP
UCAS
tHPRWC
tHCAS
tRCD
VIH–
VIL–
tCRP
LCAS
tHCAS
tCP
tCP
tMRH
VIH–
VIL–
tRAD
tRAL
tCAH
tASR tRAH tASC
Address
VIH–
VIL–
Row
tASC
Col.
tCAH
tASC
Col.
tCAH
Col.
tACP
tRWD
tAWD
tCWD
tRCS
WE
tWP
tRCS
tCWL
tWP
tCWL
tRWL
tWP
VIH–
VIL–
tOEH
tOEA
tCLZ
VOH–
U I/O
VOL–
Hi - Z
VOH–
VOL–
Hi - Z
tOEH
tCAC
tCAC
tOED
tCLZ
tOEZ
tOLZ
tCLZ
tOED
tOLZ
tOEZ
Hi - Z
out
tOEH
tOEA
tOEA
tOED
tOEZ
Hi - Z
out
Hi - Z
out
tDS
VIH–
U I/O VIL–
tAA
tAA
tOLZ
tDS tDH
tDH
in
in
tDS
L I/O
tRCS
tCPWD
tAWD
tCWD
VIH–
VIL–
tCAC
L I/O
tACP
tCPWD
tAWD
tCWD
tCWL
tRAC
tAA
OE
tCPN
tHCAS
VIH–
VIL–
tDH
in
Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
36
µPD42S18165L, 4218165L
Hyper Page Mode (EDO) Read and Write Cycle
tRASP
RAS
tRP
tRHCP
VIH –
VIL –
tCSH
tCRP
UCAS
LCAS
tHCAS
tHCAS
tCP
VIH –
VIL –
tRAD
tRAH tASC
Row
tCAH
Col.
tASC
OE
Col.
Col.
tRCH
tWCS
VIH –
VIL –
VIH –
VIL –
VOH –
VOL –
Hi - Z
tOEZ
tDHC
Data out
tWEZ
Hi - Z
Data out
tDS
U I/O
L I/O
tWCH
tCHO
tACP
tAA
tCAC
tOCH
tOEA
tOLZ
tRAC
tAA
tCAC
tCLZ
U I/O
L I/O
tCPN
tRAL
tCAH
tASC
tCAH
tRCS
WE
tCP
VIH –
VIL –
tASR
Address
tRSH
tHCAS
tHPC
tRCD
VIH –
VIL –
tDH
Data in
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
37
µPD42S18165L, 4218165L
CAS Before RAS Self Refresh Cycle (Only for the µPD42S18165L)
tRASS
RAS
tRPS
VIH –
VIL –
tCRP
tRPC
tCHS
UCAS
LCAS
VIH –
VIL –
tCPN
t CSR
Remark Address, WE, OE: Don’t care
L I/O, U I/O: Hi-Z
Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 1,024 times within a 16 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 µs), CAS before
RAS refresh cycles will be executed one time.
If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (1,024/128 ms) should be met.
For details, please refer to How to use DRAM User’s Manual.
38
µPD42S18165L, 4218165L
CAS Before RAS Refresh Cycle
tRC
tRC
tRAS
RAS
tRAS
tRP
VIH–
VIL–
tCRP
tCSR
UCAS
LCAS
tRP
tCHR
tRPC
tCSR
tCHR
tRPC
tCPN
VIH–
VIL–
Remark Address, WE, OE: Don’t care
L I/O, U I/O: Hi-Z
RAS Only Refresh Cycle
tRC
tRAS
RAS
tRC
tRP
tRAS
tRP
VIH–
VIL–
tCRP
tRPC
tCRP
tCPN
UCAS VIH–
LCAS VIL–
tASR
Address
VIH–
VIL–
tRAH
Row
Remark WE, OE: Don’t care
tASR
tRAH
Row
L I/O, U I/O: Hi-Z
39
µPD42S18165L, 4218165L
Hidden Refresh Cycle (Read)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH –
RAS VIL –
tCRP
tRCD
tCHR
tRSH
tCPN
UCAS VIH –
LCAS VIL –
tASR
Address
VIH –
VIL –
tRAD
tRAH
tRAL
tCAH
tASC
Row
Col.
tRCH
tRCS
WE
tWPZ
tWHR
VIH –
VIL –
tWEZ
tOES
tOEA
OE
tCHO
VIH –
VIL –
tRAC
tAA
tCAC
tOLZ
tCLZ
U I/O VOH –
L I/O VOL –
40
Hi - Z
tOFR
tOFC
tOEZ
Data out
Hi - Z
PD42S18165L, 4218165L
Hidden Refresh Cycle (Write)
tRC
tRC
tRAS
RAS
tRP
tRAS
tRP
VIH–
VIL–
tCRP
tRCD
tRSH
tCHR
tCPN
UCAS VIH–
LCAS VIL–
tRAD
tASR
Address
VIH–
VIL–
WE
VIH–
VIL–
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
U I/O
L I/O
VIH–
VIL–
tDH
Data in
Remark OE: Don’t care
41
PD42S18165L, 4218165L
Package Drawings
50PIN PLASTIC TSOP(II) (400 mil)
50
26
1
P
E
F
detail of lead end
25
A
H
J
K
G
I
N
C
D
M
B
L
M
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
21.17 MAX.
0.834 MAX.
B
1.0 MAX.
0.040 MAX.
C
0.8 (T.P.)
0.031 (T.P.)
D
0.32 +0.08
–0.07
0.013±0.003
E
0.1±0.05
0.004±0.002
F
1.2 MAX.
0.048 MAX.
G
0.97
0.038
H
11.76±0.2
0.463±0.008
I
10.16±0.1
0.400±0.004
J
0.8±0.2
0.031 +0.009
–0.008
K
0.145 +0.025
–0.015
0.006±0.001
L
0.5±0.1
0.020 +0.004
–0.005
M
0.13
0.005
N
0.10
0.004
P
3 +7
–3
3 +7
–3
S50G5-80-7JF4
42
PD42S18165L, 4218165L
42 PIN PLASTIC SOJ (400 mil)
22
1
21
F
E
G
U
J
C
42
D
B
H
I
T
P
Q
K
M
N
M
P42LE-400A
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
B
27.56 +0.2
–0.35
1.085+0.008
–0.014
C
10.16
0.400
D
11.18 ± 0.2
0.440 ± 0.008
E
1.08 ± 0.15
0.043+0.006
–0.007
F
0.74
0.029
G
3.5 ± 0.2
0.138 ± 0.008
H
2.545 ± 0.2
0.100 ± 0.008
I
0.8 MIN.
0.031 MIN.
J
2.6
0.102
K
1.27 (T.P.)
0.050 (T.P.)
M
0.40 ± 0.10
0.016 +0.004
–0.005
N
0.12
0.005
P
9.4 ± 0.20
0.370 ± 0.008
Q
0.10
0.004
T
R 0.85
U
0.20
+0.10
–0.05
R 0.033
0.008
+0.004
–0.002
43
PD42S18165L, 4218165L
Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
µ PD42S18165L, 4218165L.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
Types of Surface Mount Device
µ PD42S18165LG5-7JF, 4218165LG5-7JF: 50-pin plastic TSOP (II) (400 mil)
Soldering process
Infrared ray reflow
Soldering conditions
Peak temperature of package surface: 235 °C or lower,
Reflow time: 30 seconds or less (210 °C or higher),
Symbol
IR35-107-3
Number of reflow processes: MAX. 3
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 °C afterwards)
Peak temperature of package: 215 °C or lower,
VPS
VP15-107-3
Reflow time: 40 seconds or less (200 °C or higher),
Number of reflow processes: MAX. 3
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 °C afterwards)
Partial heating method
Terminal temperature: 300 °C or lower,
–
Time: 3 seconds or lower (Per side of the package).
Note
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution
Do not apply more than one soldering method at any one time, except for “Partial heating
method”.
44
PD42S18165L, 4218165L
µ PD42S18165LLE, 4218165LLE: 42-pin plastic SOJ (400 mil)
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak temperature of package surface: 235 °C or lower,
Reflow time: 30 seconds or less (210 °C or higher),
Number of reflow processes: MAX. 3
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 °C afterwards)
IR35-207-3
VPS
Peak temperature of package: 215 °C or lower,
Reflow time: 40 seconds or less (200 °C or higher),
Number of reflow processes: MAX. 3
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 °C afterwards)
VP15-207-3
Partial heating method
Terminal temperature: 300 °C or lower,
Time: 3 seconds or less (Per side of the package).
Note
–
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution
Do not apply more than one soldering method at any one time, except for “Partial heating
method”.
45
PD42S18165L, 4218165L
[MEMO]
46
PD42S18165L, 4218165L
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
47
µPD42S18165L, 4218165L
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
48