COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller Y General Description Y The COP8780C, COP8781C and COP8782C are members of the COPSTM 8-bit microcontroller family. They are fully static microcontrollers, fabricated using double-metal, double poly silicon gate microCMOS EPROM technology. These devices are available as UV erasable or One Time Programmable (OTP). These low cost microcontrollers are complete microcomputers containing all system timing, interrupt logic, EPROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with associated 16-bit autoreload/capture register, and a multisourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific application. These devices operate over a voltage range of 4.5V to 6.0V. An efficient, regular instruction set operating at a 1 ms instruction cycle rate provides optimal throughput. The COP8780C, COP8781C and COP8782C can be configured to EMULATE the COP880C, COP840C and COP820C microcontrollers. Key Features Y Y Y Y 16-bit multi-function timer supporting Ð PWM mode Ð External event counter mode Ð Input capture mode Crystal, RC or External Oscillator, user configurable 4 kbytes on-chip OTP EPROM with security feature 128 or 64 bytes of on-chip RAM, user configurable Y CPU/Instruction Set Features Y Y Y Y Y Y Y Y Y Memory-mapped I/O Software selectable I/O options (TRI-STATEÉ, PushPull, Weak Pull-Up Input, High Impedance input) Low current drain (typically k 1 mA) Extra-low current static HALT mode Single supply operation: 4.5V to 6.0V Temperature range: b40§ C to a 85§ C Development Support Y Y 1 ms instruction cycle time Three multi-source interrupts servicing Ð External interrupt with selectable edge Ð Timer interrupt Ð Software interrupt Versatile and easy to use instruction set 8-bit Stack Pointer (SP)Ðstack in RAM Two 8-bit Register Indirect Data Memory Pointers (B and X) Fully Static CMOS I/O Features Y Schmitt trigger inputs on Port G MICROWIRE/PLUS serial I/O Packages: Ð 44 PLCC, OTP, Emulates COP880C, 36 I/O pins Ð 40 DIP, OTP, Emulates COP880C, 36 I/O pins Ð 28 DIP, OTP, Emulates COP820C/840C/881C, 24 I/O pins Ð 20 DIP, OTP, Emulates COP822C/842C, 16 I/O pins Ð 28 SO, 20 SO, OTP Ð 44 LDCC, UV Erasable Ð 40 CERDIP, 28 CERDIP, 20 CERDIP, UV Erasable Y Emulation device for the COP880C, COP840C, and COP820C Real-time emulation and full program debug offered by MetaLink development system Block Diagram TL/DD/11299 – 1 FIGURE 1. Block Diagram TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. COPSTM microcontrollers, MICROWIRETM , MICROWIRE/PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation. iceMASTERTM is a trademark of MetaLink Corporation. C1996 National Semiconductor Corporation TL/DD11299 RRD-B30M96/Printed in U. S. A. http://www.national.com COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller August 1996 Connection Diagrams TL/DD/11299 – 4 Top View Order Number COP8780C-XXX/V or COP8780C-XXX/EL See NS Package Number EL40C or V44A TL/DD/11299–3 Top View Order Number COP8780C-XXX/N or COP8780C-XXX/J See NS Package Number J40AQ or N40A TL/DD/11299–5 Top View Order Number COP78782C/XXX/J, COP8782C-XXX/N or COP8782C-XXX/WM See NS Package Number J20AQ, M20B or N20B TL/DD/11299 – 6 Top View Order Number COP8781C-XXX/J, COP8781C-XXX/N or COP8781C-XXX/WM See NS Package Number J28AQ, M28B or N28B FIGURE 3. Connection Diagrams http://www.national.com 2 COP8780C/COP8781C/COP8782C Absolute Maximum Ratings Total Current into VCC Pin (Source) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) 7V 50 mA Total Current out of GND Pin (Sink) 60 mA b 65§ C to a 150§ C Storage Temperature Range Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Programming Voltage VPP (RESET pin) and ME (pin G6) 13.4V b 0.3V to VCC a 0.3V Voltage at any Pin DC Electrical Characteristics COP87XXC; b40§ C s TA s a 85§ C unless otherwise specified Parameter Condition Min Operating Voltage Power Supply Ripple (Note 1) Peak to Peak Supply Current CKI e 10 MHz (Note 2) HALT Current (Note 3) VCC e 6V, tc e 1 ms VCC e 6V, CKI e 0 MHz Input Levels RESET, CKI Logic High Logic Low All Other Inputs Logic High Logic Low Max Units 6.0 0.1 VCC V V 21 10 mA mA 0.1 VCC V V 0.2 VCC V V a2 b 250 mA mA 0.9 VCC 0.7 VCC Hi-Z Input Leakage Input Pullup Current VCC e 6.0V VCC e 6.0V, VIN e 0V G Port Input Hysteresis (Note 6) Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Typ 4.5 b2 b 40 0.05 VCC VCC e 4.5V, VOH e 3.8V VCC e 4.5V, VOL e 1.0V b 0.4 VCC e 4.5V, VOH e 3.2V VCC e 4.5V, VOH e 3.8V VCC e 4.5V, VOL e 0.4V b 10 b 0.4 V mA mA 10 b 110 a 2.0 mA mA mA mA 15 3 mA mA g 200 mA 1.6 b 2.0 Allowable Sink/Source Current per Pin D Outputs (Sink) All Others Maximum Input Current (Notes 4, 6) without Latchup (Room Temp) Room Temp RAM Retention Voltage, Vr (Note 5) 2.0 V Input Capacitance (Note 6) 7 pF Load Capacitance on D2 (Note 6) 1000 pF Note 1: Rate of voltage change must be less than 0.5V/ms. Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: The HALT mode will stop CKI from oscillating in the RC and the crystal configurations. Halt test conditions: All Inputs tied to VCC. L, C, and G port I/O’s configured as outputs and programmed low; D outputs programmed low; the window for UV erasable packages is completely covered with an opaque cover to prevent light from falling onto the die during HALT mode test. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously. Note 6: Parameter characterized but not tested. 3 http://www.national.com COP8780C/COP8781C/COP8782C AC Electrical Characteristics b40§ C k TA k a 85§ C unless otherwise specified Parameter Condition Max Units 1 3 DC DC ms ms fr e Max fr e 10 MHz Ext Clock fr e 10 MHz Ext Clock 45 55 12 8 % ns ns VCC t 4.5V VCC t 4.5V 200 60 Instruction Cycle Time (tc) Crystal/Resonator or External Clock R/C Oscillator Mode VCC t 4.5V VCC t 4.5V CKI Clock Duty Cycle (Note 7) Rise Time (Note 7) Fall Time (Note 7) Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 SO, SK All Others Min Typ CL e 100 pF, RL e 2.2 kX VCC t 4.5V VCC t 4.5V 0.7 1 MICROWIRETM Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) 20 56 Reset Pulse Width tc tc tc tc 1.0 ms tc e Instruction Cycle Time. Timing Diagram TL/DD/10802 – 2 4 ns 1 1 1 1 Note 7: Parameter guaranteed by design, but not tested. FIGURE 2. MICROWIRE/PLUS Timing ms ms ns ns 220 Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time http://www.national.com ns ns Pin Descriptions Pins G1 and G2 currently do not have any alternate functions. VCC and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description. RESET is the master reset input. See Reset description. PORT D is an 8-bit output port that is preset high when RESET goes low. Care must be exercised with the D2 pin operation. At reset, the external load on this pin must ensure that the output voltage stay above 0.7 VCC to prevent the chip from entering special modes. Also, keep the external loading on D2 to less than 1000 pF. PORT I is an 8-bit Hi-Z input port. The 28-pin device does not have a full complement of PORT I pins. The unavailable pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated PORT I pins will draw power only when addressed. PORT L is an 8-bit I/O port. PORT C is a 4-bit I/O port. Three memory locations are allocated for the L, G and C ports, one each for data register, configuration register and the input pins. Reading bits 4–7 of the C-Configuration register, data register, and input pins returns undefined data. There are two registers associated with the L and C ports: a data register and a configuration register. Therefore, each L and C I/O bit can be individually configured under software control as shown below: Config. Data Ports L and C Setup 0 0 1 1 0 1 0 1 Hi-Z Input (TRI-STATE Output) Input with Pull-Up (Weak One Output) Push-Pull Zero Output Push-Pull One Output Functional Description Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. ALU AND CPU REGISTERS The ALU can do an 8-bit addition, subtraction, logical or shift operation in one cycle time. There are five CPU registers: A is the 8-bit Accumulator register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register, can be auto incremented or decremented. X is the 8-bit alternate address register, can be incremented or decremented. SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack in RAM. The SP must be initialized with software (usually to RAM address 06F Hex with 128 bytes of on-chip RAM selected, or to RAM address 02F Hex with 64 bytes of on-chip RAM selected). The SP is used with the subroutine call and return instructions, and with the interrupts. B, X and SP registers are mapped into the on-chip RAM. The B and X registers are used to address the on-chip RAM. The SP register is used to address the stack in RAM during subroutine calls and returns. On the 20- and 28-pin parts, it is recommended that all bits of Port C be configured as outputs to minimize current. PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. There are two registers associated with the G port: a data register and a configuration register. Therefore, each G port bit can be individually configured under software control as shown below: Config. Data Port G Setup 0 0 1 1 0 1 0 1 Hi-Z Input (TRI-STATE Output) Input with Pull-Up (Weak One Output) Push-Pull Zero Output Push-Pull One Output PROGRAM MEMORY The device contains 4096 bytes of UV erasable or OTP EPROM memory. This memory is mapped in the program memory address space from 0000 to 0FFF Hex. The program memory may contain either instructions or data constants, and is addressed by the 15-bit program counter (PC). The program memory can be indirectly read by the LAID (Load Accumulator Indirect) instruction for table lookup of constant data. All locations in the EPROM program memory will contain 0FF Hex (all 1’s) after the device is erased. OTP parts are shipped with all locations already erased to 0FF Hex. Unused EPROM locations should always be programmed to 00 Hex so that the software trap can be used to halt runaway program operation. The device can be configured to inhibit external reads of the program memory. This is done by programming the security bit in the ECON (EPROM configuration) register to zero. See the ECON REGISTER section for more details. Since G6 and G7 are input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. The device will be placed in the HALT mode by writing a one to the G7 bit in the G-port data register. Six pins of Port G have alternate features: G0 INTR (an external interrupt) G3 TIO (timer/counter input/output) G4 SO (MICROWIRE/PLUS serial data output) G5 SK (MICROWIRE/PLUS clock I/O) G6 SI (MICROWIRE/PLUS serial data input) G7 CKO crystal oscillator output (selected by programming the ECON register) or HALT Restart/general purpose input DATA MEMORY The data memory address space includes on-chip RAM, I/O, and registers. Data memory is addressed directly by instructions, or indirectly by means of the B, X, or SP point- 5 http://www.national.com Functional Description (Continued) ers. The device can be configured to have either 64 or 128 bytes of RAM, depending on the value of the ‘‘RAM SIZE’’ bit in the ECON (EPROM CONFIGURATION) register. The sixteen bytes of RAM located at data memory address 0F0– 0FF are designated as ‘‘registers’’. These sixteen registers can be decremented and tested with the DRSZ (Decrement Register and Skip if Zero) instruction. The three pointers X, B, and SP are memory mapped into this register address space at addresses 0FC, 0FE, and 0FD respectively. The remaining registers are available for general usage. Any bit of data memory can be directly set, reset or tested. All of the I/O registers and control registers (except A and PC) are memory mapped. Consequently, any of the I/O bits or control register bits can be directly and individually set, reset, or tested. RESET The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the Ports L, G and C are placed in the TRI-STATE mode and the Port D is set high. The PC, PSW and CNTRL registers are cleared. The data and configuration registers for Ports L, G and C are cleared. The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes. Note: RAM contents are undefined upon power-up. ECON (EPROM CONFIGURATION) REGISTER The ECON register is used to configure the user selectable clock, security, and RAM size options. The register can be programmed and read only in EPROM programming mode. Therefore, the register should be programmed at the same time as the program memory locations 0000 through 0FFF Hex. UV erasable parts are shipped with 0FF Hex in this register while the OTP parts are shipped with 07F Hex in this register. Erasing the EPROM program memory also erases the ECON register. The device has a security feature which, when enabled, prevents reading of the EPROM program memory. The security bit in the ECON register determines whether security is enabled or disabled. If the security option is enabled, then any attempt to externally read the contents of the EPROM will result in the value E0 Hex being read from all program memory locations. If the security option is disabled, the contents of the internal EPROM may be read. The ECON register is readable regardless of the state of the security bit. The format of the ECON register is as follows: TL/DD/11299 – 7 RC t 5X Power Supply Rise Time FIGURE 4. Recommended Reset Circuit OSCILLATOR CIRCUITS Figure 5 shows the three clock oscillator configurations available for the device. The CKI 1 and CKI 2 bits in the ECON register are used to select the clock option. See the ECON REGISTER section for more details. TABLE I Bit 7 Bit 6 X X Bit 5 Bit 4 Bit 3 Bit 2 SECURITY CKI 2 CKI 1 X Bit 1 Bit 0 RAM SIZE X Bit 7 e X Bit 6 e X Bit 5 e 1 Don’t care. Don’t care. Security disabled. EPROM read and write are allowed. e0 Security enabled. EPROM read and write are not allowed. TL/DD/11299 – 8 FIGURE 5. Crystal, External and R-C Connection Diagrams Bits 4,3 A. Crystal Oscillator The device can be driven by a crystal clock. The crystal network is connected between the pins CKI and CKO. Table II shows the component values required for various standard crystal frequencies. e 1,1 e 0,1 External CKI option selected. Not allowed. e 1,0 RC oscillator option selected. e 0,0 Crystal oscillator option selected. Bit 2 e X Don’t care. Bit 1 e 1 Selects 128 byte RAM option. This emulates COP840 and COP880. e0 Bit 0 e X B. External Oscillator CKI can be driven by an external clock signal provided it meets the specified duty cycle, rise and fall times, and input levels. In External oscillator mode, G7 is available as a general purpose input and/or HALT restart control. Selects 64 byte RAM option. This emulates COP820. Don’t care. http://www.national.com 6 Functional Description (Continued) TABLE II. Crystal Oscillator Configuration, TA e 25§ C R1 (kX) R2 (MX) C1 (pF) C2 (pF) CKI Freq (MHz) Conditions 0 0 1 1 30 30 30 – 36 30 – 36 10 4 VCC e 5V VCC e 5V TABLE III. RC Oscillator Configuration, TA e 25§ C R (kX) C (pF) CKI Freq. (MHz) Instr. Cycle (ms) Conditions 3.3 5.6 6.8 82 100 100 2.2 to 2.7 1.1 to 1.3 0.9 to 1.1 3.7 to 4.6 7.4 to 9.0 8.8 to 10.8 VCC e 5V VCC e 5V VCC e 5V Note: (R/C Oscillator Configuration): 3k s R s 200k, 50 pF s C s 200 pF. INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupts respectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled. IEDG selects the external interrupt edge (0 e rising edge, 1 e falling edge). The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt. IPND and TPND bits signal which interrupt is pending. After an interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the interrupts to be prioritized under software. The pending flags have to be cleared by the user. Setting the GIE bit high inside the interrupt subroutine allows nested interrupts. The software interrupt does not reset the GIE bit. This means that the controller can be interrupted by other interrupt sources while servicing the software interrupt. C. R/C Oscillator CKI can be configured as a single pin RC controlled oscillator. In RC oscillator mode, G7 is available as a general purpose input and/or HALT restart control. Table III shows the variation in the oscillator frequencies as functions of the component (R and C) values. HALT MODE The device supports a power saving mode of operation: HALT. The controller is placed in the HALT mode by setting the G7 data bit, alternatively the user can stop the clock input. (Stopping the clock input will draw more current than setting the G7 data bit.) In the HALT mode all internal processor activities including the clock oscillator are stopped. The fully static architecture freezes the state of the controller and retains all information until continuing. In the HALT mode, power requirements are minimal as it draws only leakage currents and output current. The applied voltage (VCC) may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine. There are two ways to exit the HALT mode: via the RESET or by the G7 pin. A low on the RESET line reinitializes the microcontroller and starts execution from address 0000H. In external and RC oscillator modes, a low to high transition on the G7 pin also causes the microcontroller to come out of the HALT mode. Execution resumes at the address following the HALT instruction. Except for the G7 data bit, which gets reset, all RAM locations retain the values they had prior to execution of the ‘‘HALT’’ instruction. It is required that the first instruction following the ‘‘HALT’’ instruction be a ‘‘NOP’’ in order to synchronize the clock. INTERRUPT PROCESSING The interrupt, once acknowledged, pushes the program counter (PC) onto the stack and the stack pointer (SP) is decremented twice. The Global Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then vectors to the address 00FFH and resumes execution from that address. This process takes 7 cycles to complete. At the end of the interrupt subroutine, any of the following three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts. Any of the three instructions can be used to return from a hardware interrupt subroutine. The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop. INTERRUPTS The device has a sophisticated interrupt structure to allow easy interface to the real world. There are three possible interrupt sources, as shown below. A maskable interrupt on external G0 input (positive or negative edge sensitive under software control) A maskable interrupt on timer underflow or timer capture A non-maskable software/error interrupt on opcode zero Note: There is always the possiblity of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. 7 http://www.national.com Functional Description (Continued) TL/DD/11299 – 9 FIGURE 6. Interrupt Block Diagram The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/ PLUS interface with the internal clock source is called the Master mode of operation. Operating the MICROWIRE/ PLUS interface with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS , the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table IV details the different clock rates that may be selected. DETECTION OF ILLEGAL CONDITIONS The device incorporates a hardware mechanism that allows it to detect illegal conditions which may occur from coding errors, noise and ‘‘brown out’’ voltage drop situations. Specifically, it detects cases of executing out of undefined EPROM area and unbalanced stack situations. Reading an undefined EPROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is also ‘‘00’’. Thus a program accessing undefined EPROM will cause a software interrupt. Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for each subroutine call. By initializing the stack pointer to the top of RAM, the first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program will attempt to execute from FFFF (hexadecimal), which is an undefined EPROM location and will trigger a software interrupt. TABLE IV MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous bidirectional communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 7 shows the block diagram of the MICROWIRE/PLUS interface. SL1 SL0 SK Cycle Time 0 0 1 0 1 x 2tc 4tc 8tc where, tc is the instruction cycle time. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 8 shows how two device microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement. Master MICROWIRE/PLUS Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally by the device. The MICROWIRE/PLUS Master always initiates all data exchanges (Figure 8) . The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table V summarizes the bit settings required for Master mode of operation. SLAVE MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL TL/DD/11299–10 FIGURE 7. MICROWIRE/PLUS Block Diagram http://www.national.com 8 Functional Description (Continued) TL/DD/11299 – 11 FIGURE 8. MICROWIRE/PLUS Application bit in the CNTRL register enables the SO and SK functions on the G Port. The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register. Table V summarizes the settings required to enter the Slave mode of operation. The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated (Figure 8). MODE 1. TIMER WITH AUTO-LOAD REGISTER In this mode of operation, the timer T1 counts down at the instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allows the generation of square-wave outputs or pulse width modulated outputs under software control (Figure 9) . TABLE V MODE 2. EXTERNAL COUNTER In this mode, the timer T1 becomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automatically copied into the counter. The underflow can also be programmed to generate an interrupt (Figure 9) . G4 G5 Config. Config. Bit Bit 1 1 0 1 1 0 0 0 G4 Fun. G5 Fun. G6 Fun. Operation SO Int. SK SI MICROWIRE Master TRI-STATE Int. SK SI MICROWIRE Master Ext. SK SI MICROWIRE Slave TRI-STATE Ext. SK SI MICROWIRE Slave SO MODE 3. TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. In this mode the user can elect to be interrupted on the specified trigger edge (Figure 10) . TIMER/COUNTER The device has a powerful 16-bit timer with an associated 16-bit register enabling it to perform extensive timer functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the register CNTRL allow the timer to be started and stopped under software control. The timer-register pair can be operated in one of three possible modes. Table VI details various timer operating modes and their requisite control settings. TABLE VI. Timer Operating Modes CNTRL Bits 765 Operation Mode T Interrupt Timer Counts On 000 001 010 011 100 101 110 111 External Counter w/Auto-Load Reg. External Counter w/Auto-Load Reg. Not Allowed Not Allowed Timer w/Auto-Load Reg. Timer w/Auto-Load Reg./Toggle TIO Out Timer w/Capture Register Timer w/Capture Register Timer Underflow Timer Underflow Not Allowed Not Allowed Timer Underflow Timer Underflow TIO Pos. Edge TIO Neg. Edge TIO Pos. Edge TIO Neg. Edge Not Allowed Not Allowed tc tc tc tc 9 http://www.national.com Functional Description (Continued) Control Registers CNTRL REGISTER (ADDRESS X’00EE) The Timer and MICROWIRE/PLUS control register contains the following bits: SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by IEDG External interrupt edge polarity select (0 e rising edge, 1 e falling edge) MSEL Enable MICROWIRE/PLUS functions SO and SK Start/Stop the Timer/Counter (1 e run, 0 e stop) Timer input edge polarity select (0 e rising edge, 1 e falling edge) Selects the capture mode Selects the timer mode TRUN TL/DD/11299–12 TC3 FIGURE 9. Timer/Counter Auto Reload Mode Block Diagram TC2 TC1 TC1 TC2 TC3 TRUN MSEL IEDG S1 Bit 7 S0 Bit 0 PSW REGISTER (ADDRESS X’00EF) The PSW register contains the following select bits: GIE Global interrupt enable ENI External interrupt enable BUSY MICROWIRE/PLUS busy shifting IPND External interrupt pending ENTI Timer interrupt enable TPND Timer interrupt pending C Carry Flag HC Half carry Flag TL/DD/11299–13 FIGURE 10. Timer Capture Mode Block Diagram TIMER PWM APPLICATION Figure 11 shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the ‘‘Timer with auto reload’’ mode and the TIO pin is selected as the timer output. At the outset the TIO pin is set high, the timer T1 holds the on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and copies the off time into the timer, which continues to run. By alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily generated. HC C TPND ENTI IPND Bit 7 BUSY ENI GIE Bit 0 Addressing Modes REGISTER INDIRECT This is the ‘‘normal’’ mode of addressing for the device. The operand is the memory location addressed by the B register or X register. DIRECT The instruction contains an 8-bit address field that directly points to the data memory location for the operand. IMMEDIATE The instruction contains an 8-bit immediate field as the operand. REGISTER INDIRECT (AUTO INCREMENT AND DECREMENT) This is a register indirect mode that automatically increments or decrements the B or X register after executing the instruction. TL/DD/11299–14 FIGURE 11. Timer Application RELATIVE This mode is used for the JP instruction, the instruction field is added to the program counter to get the new program location. JP has a range of b31 to a 32 to allow a one byte relative jump (JP a 1 is implemented by a NOP instruction). There are no ‘‘pages’’ when using JP, all 15 bits of PC are used. http://www.national.com 10 Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. RAM Select Address Contents 64 On-Chip RAM Bytes Selected by ECON reg. 00 – 2F 30 – 7F 48 On-Chip RAM Bytes Unused RAM Address Space (Reads as all 1’s) 128 On-Chip RAM Bytes Selected by ECON reg. 00 – 6F 70 – 7F 112 On-chip RAM Bytes Unused RAM Address Space (Reads as all 1’s) 80 to BF Expansion Space for On-Chip EERAM C0 to CF Expansion Space for I/O and Registers D0 to DF D0 D1 D2 D3 D4 D5 D6 D7 On-Chip I/O and Registers Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port I Input Pins (Read Only) D8 D9 DA DB DC DD – DF Port C Data Register Port C Configuration Register Port C Input Pins (Read Only) Reserved for Port C Port D Data Register Reserved for Port D E0 to EF E0 – E7 E8 E9 EA EB EC ED EE EF On-Chip Functions and Registers Reserved for Future Parts Reserved MICROWIRE/PLUS Shift Register Timer Lower Byte Timer Upper Byte Timer Autoload Register Lower Byte Timer Autoload Register Upper Byte CNTRL Control Register PSW Register F0 to FF FC FD FE On-Chip RAM Mapped as Registers X Register SP Register B Register Reading unused memory locations below 7FH will return all ones. Reading other unused memory locations will return undefined data. 11 http://www.national.com Instruction Set Symbols [B] Memory indirectly addressed by B register [X] Memory indirectly addressed by X register Mem Direct address memory or [B] MemI Direct address memory or [B] or Immediate data Imm 8-bit Immediate data Reg Register memory: addresses F0 to FF (Includes B, X and SP) Bit Bit number (0 to 7) w Loaded with Ý Exchanged with REGISTER AND SYMBOL DEFINITIONS Registers A 8-bit Accumulator register B 8-bit Address register X 8-bit Address register SP 8-bit Stack pointer register PC 15-bit Program counter register PU upper 7 bits of PC PL lower 8 bits of PC C 1-bit of PSW register for carry HC Half Carry GIE 1-bit of PSW register for global interrupt enable Instruction Set A w A a MemI A w A a MemI a C, C w Carry HC w Half Carry A w A a MemI a C, C w Carry HC w Half Carry A w A and MemI A w A or MemI A w A xor MemI Compare A and MemI, Do next if A e MemI Compare A and MemI, Do next if A l MemI Do next if lower 4 bits of B i Imm Reg w Reg b 1, skip if Reg goes to 0 1 to bit, Mem (bit e 0 to 7 immediate) 0 to bit, Mem If bit, Mem is true, do next instr. ADD ADC add add with carry SUBC subtract with carry AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT Logical AND Logical OR Logical Exclusive-OR IF equal IF greater than IF B not equal Decrement Reg. ,skip if zero Set bit RBIT Reset bit IFBIT If bit X LD A LD mem LD Reg Exchange A with memory Load A with memory Load Direct memory Immed. Load Register memory Immed. A Ý Mem A w MemI Mem w Imm Reg w Imm X X LD A LD A LD M Exchange A with memory [B] Exchange A with memory [X] Load A with memory [B] Load A with memory [X] Load Memory Immediate (B w B g 1) A Ý [B] (X w X g 1) A Ý [X] (B w B g 1) A w [B] (X w X g 1) A w [X] [B] w Imm (B w B g 1) CLRA INCA DECA LAID DCORA RRCA SWAPA SC RC IFC IFNC Clear A Increment A Decrement A Load A indirect from ROM DECIMAL CORRECT A ROTATE A RIGHT THRU C Swap nibbles of A Set C Reset C If C If not C Aw0 AwAa1 AwAb1 A w ROM(PU,A) A w BCD correction (follows ADC, SUBC) C x A7 x . . . x A0 x C A7 . . . A4 Ý A3 . . . A0 C w 1, HC w 1 C w 0, HC w 0 If C is true, do next instruction If C is not true, do next instruction JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Jump absolute long Jump absolute Jump relative short Jump subroutine long Jump subroutine Jump indirect Return from subroutine Return and Skip Return from Interrupt Generate an interrupt No operation PC w ii (ii e 15 bits, 0 to 32k) PC11..0 w i (i e 12 bits) PC w PC a r (r is b31 to a 32, not 1) [SP] w PL,[SP-1] w PU,SP-2,PC w ii [SP] w PL,[SP-1] w PU,SP-2,PC11.. 0 w i PL w ROM(PU,A) SP a 2,PL w [SP],PU w [SP-1] SP a 2,PL w [SP],PU w [SP-1],Skip next instruction SP a 2,PL w [SP],PU w [SP-1],GIE w 1 [SP] w PL,[SPb1] w PU,SP-2,PC w 0FF PC w PC a 1 http://www.national.com 12 13 JP -17 JP -16 JP -1 JP -0 D LD 0FF,Ý1 LD 0FE,Ýi LD 0FD,Ýi LD 0FC,Ýi LD 0FB,Ýi LD 0FA,Ýi LD 0F9,Ýi LD 0F8,Ýi LD 0F7,Ýi LD 0F6,Ýi LD 0F5,Ýi LD 0F4,Ýi LD 0F3,Ýi LD 0F2,Ýi LD 0F1,Ýi LD 0F0,Ýi C B * LD A, [X] DIR LD Md, Ýi LD A, [X b] LD A, [X a ] * NOP * X A, [X] * * X A, [X b] X A, [X a ] * RRCA A * LD A, [B] JSRL JMPL LD A, [Bb] LD A, [B a ] * * * X A, [B] JID LAID X A, [Bb] X A, [B a ] SC RC 9 * LD [B], Ýi LD A, Md X A,Md LD [Bb],Ýi LD [B a ],Ýi * LD A, Ýi OR A, Ýi XOR A, Ýi AND A, Ýi ADD A, Ýi IFGT A, Ýi IFEQ A, Ýi SUBC A, Ýi ADC A, Ýi 8 RETI RET RETSK * DECA INCA IFNC IFC OR A,[B] XOR A,[B] AND A,[B] ADD A,[B] IFGT A,[B] IFEQ A,[B] SUBC A,[B] ADC A, [B] Md is a directly addressed memory location DRSZ 0FF DRSZ 0FE DRSZ 0FD DRSZ 0FC DRSZ 0FB DRSZ 0FA DRSZ 0F9 DRSZ 0F8 DRSZ 0F7 DRSZ 0F6 DRSZ 0F5 DRSZ 0F4 DRSZ 0F3 DRSZ 0F2 DRSZ 0F1 DRSZ 0F0 is the immediate data JP -18 JP -2 i JP -19 JP -3 where, JP -20 JP -24 JP -8 JP -4 JP -25 JP -9 JP -21 JP -26 JP -10 JP -5 JP -27 JP -11 JP -22 JP -28 JP -12 JP -6 JP -29 JP -13 JP -23 JP -30 JP -14 JP -7 E JP -31 F JP -15 RBIT 7,[B] RBIT 6, [B] RBIT 5,[B] RBIT 4,[B] RBIT 3,[B] RBIT 2,[B] RBIT 1,[B] RBIT 0,[B] * DCORA SWAPA CLRA * * * * 6 5 LD B, 0 LD B, 1 LD B, 2 LD B, 3 LD B, 4 LD B, 5 LD B, 6 LD B, 7 LD B, 8 LD B, 9 LD B, 0A LD B, 0B LD B, 0C LD B, 0D LD B, 0E LD B, 0F 4 IFBNE 0F IFBNE 0E IFBNE 0D IFBNE 0C IFBNE 0B IFBNE 0A IFBNE 9 IFBNE 8 IFBNE 7 IFBNE 6 IFBNE 5 IFBNE 4 IFBNE 3 IFBNE 2 IFBNE 1 IFBNE 0 * is an unused opcode (see following table) SBIT 7,[B] SBIT 6, [B] SBIT 5,[B] SBIT 4,[B] SBIT 3,[B] SBIT 2,[B] SBIT 1,[B] SBIT 0,[B] IFBIT 7,[B] IFBIT 6,[B] IFBIT 5,[B] IFBIT 4,[B] IFBIT 3,[B] IFBIT 2,[B] IFBIT 1,[B] IFBIT 0,[B] 7 Bits 7 – 4 3 JSR 0F00 –0FFF JSR 0E00 –0EFF JSR 0D00 –0DFF JSR 0C00 –0CFF JSR 0B00 –0BFF JSR 0A00 –0AFF JSR 0900 –09FF JSR 0800 –08FF JSR 0700 –07FF JSR 0600 –06FF JSR 0500 –05FF JSR 0400 –04FF JSR 0300 –03FF JSR 0200 –02FF JSR 0100 –01FF JSR 0000 –00FF 2 JMP 0F00 –0FFF JMP 0E00 –0EFF JMP 0D00 –0DFF JMP 0C00 –0CFF JMP 0B00 –0BFF JMP 0A00 –0AFF JMP 0900 –09FF JMP 0800 –08FF JMP 0700 –07FF JMP 0600 –06FF JMP 0500 –05FF JMP 0400 –04FF JMP 0300 –03FF JMP 0200 –02FF JMP 0100 –01FF JMP 0000 –00FF 1 JP a 32 JP a 31 JP a 30 JP a 29 JP a 28 JP a 27 JP a 26 JP a 25 JP a 24 JP a 23 JP a 22 JP a 21 JP a 20 JP a 19 JP a 18 JP a 17 0 JP a 16 JP a 15 JP a 14 JP a 13 JP a 12 JP a 11 JP a 10 JP a 9 JP a 8 JP a 7 JP a 6 JP a 5 JP a 4 JP a 3 JP a 2 INTR F E D C B A 9 8 7 6 5 4 3 2 1 0 OPCODE LIST Bits 3 – 0 http://www.national.com Instruction Execution Time Bytes and Cycles per Instruction Most instructions are single byte (with immediate addressing mode instruction taking two bytes). Most single instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. Arithmetic Instructions (Bytes/Cycles) [B] Direct Immed. ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 SBIT RBIT IFBIT 1/1 1/1 1/1 1/3 3/4 3/4 3/4 Memory Transfer Instructions (Bytes/Cycles) Register Register Indirect Indirect Direct Immed. Auto Incr & Decr [B] [X] [B a , Bb] [X a , Xb] X A,* 1/1 LD A,* 1/1 LD B,Imm LD B,Imm LD Mem,Imm LD Reg,Imm 1/3 1/3 2/3 2/3 2/2 1/1 2/3 3/3 1/2 1/2 1/3 1/3 (If B k 16) (If B l 15) 2/2 2/3 * e l Memory location addressed by B or X or directly. Instructions Using A & C Instructions CLRA INCA DECA LAID DCORA RRCA SWAPA SC RC IFC IFNC http://www.national.com Transfer of Control Instructions Bytes/Cycles Instructions 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP 14 Bytes/Cycles 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/7 1/1 Bytes and Cycles per Instruction (Continued) Development Support SUMMARY The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do not use these opcodes. # iceMASTERTM : IM-COP8/400ÐFull feature in-circuit emulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available. # COP8 Debug Module: Moderate cost in-circuit emulation Unused Opcode Instruction 60 61 62 63 67 8C 99 9F A7 A8 NOP NOP NOP NOP NOP RET NOP LD [B], Ýi X A, [B] NOP Unused Opcode Instruction A9 AF B1 B4 B5 B7 B9 BF NOP LD A, [B] C x HC NOP NOP X A, [X] NOP LD A, [X] and development programming unit. # COP8 Evaluation and Programming Unit: EPU-COP880CÐlow cost In-circuit simulation and development programming unit. # Assembler: COP8-DEV-IBMA. A DOS installable crossdevelopment Assembler, Linker, Librarian and Utility Software Development Tool Kit. # C Compiler: COP8C. A DOS installable cross development Software Tool Kit. # OTP/EPROM Programmer Support: Covering needs from engineering prototype, pilot production to full production environments. 15 http://www.national.com Development Support (Continued) # Watch windows, content updated automatically at each IceMASTER (IM) IN-CIRCUIT EMULATION execution break. The iceMASTER IM-COP8/400 is a full feature, PC-based in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 12 for configuration. # Instruction by instruction memory/register changes displayed on source window when in single step operation. # Single base unit and debugger software reconfigurable to support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file. The iceMASTER IM-COP8/400 with its device specific COP8 Probe provides a rich feature set for developing, testing and maintaining product: # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Real-time in-circuit emulation; full 2.4-5.5VDC operation # Halt/Idle mode notification. # On-line HELP customized to specific processor using range, full DC-10 MHz clock. Chip options are programmable or jumper selectable. # Direct connection to application board by package com- master model file. patible socket or surface mount assembly. # Includes a copy of COP8-DEV-IBMA assembler and link- # Full 32 kbyte of loadable programming space that over- er SDK. lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the probe as necessary. IM Order Information Base Unit: # Full 4k frame synchronous trace memory. Address, instruction, and 8 unspecified, circuit connectable trace lines. Display can be HLL source (e.g., C source), assembly or mixed. IM-COP8/400-1 iceMASTER base unit, 110V power supply IM-COP8/400-2 iceMASTER base unit, 220V power supply # A full 64k hardware configurable break, trace on, trace off control, and pass count increment events. iceMASTER Probe # Tool set integrated interactive symbolic debuggerÐsup- MHW-880C20DWPC MHW-880C28DWPC MHW-880C40DWPC MHW-880C44PWPC ports both assembler (COFF) and C Compiler (.COD) linked object formats. # Real time peformance profiling analysis; selectable bucket definition. 20 DIP 28 DIP 40 DIP 44 PLCC DIP to SO Adapters MHW-SOIC20 MHW-SOIC28 20 SO 28 SO TL/DD/11299 – 15 FIGURE 12. COP iceMASTER Environment http://www.national.com 16 Development Support (Continued) # Debugger software is processor customized, and recon- IceMASTER DEBUG MODULE (DM) figured from a master model file. The iceMASTER Debug Module is a PC based, combination in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 13 for configuration. # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Halt/Idle mode notification. # Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data is taken directly from the overlay RAM. The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. Summary of features is as follows: # Programming of 44 PLCC and 68 PLCC parts requires external programming adapters. # Includes wall mount power supply. # On-board VPP generator from 5V input or connection to # Real-time in-circuit emulation; full operating voltage external supply supported. Requires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display). range operation, full DC-10 MHz clock. # All processor I/O pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly. # On-line HELP customized to specific processor using master model file. # Full 32 kbyte of loadable programming space that over- # Includes a copy of COP8-DEV-IBMA assembler and link- lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary. er SDK. DM Order Information # 100 frames of synchronous trace memory. The display Debug Module Unit can be HLL source (C source), assembly or mixed. The most recent history prior to a break is available in the trace memory. COP8-DM/880C Cable Adapters # Configured break points; uses INTR instruction which is modestly intrusive. # SoftwareÐonly supported features are selectable. # Tool set integrated interactive symbolic debuggerÐsupports both assembler (COFF) and C Compiler (.COD) SDK linked object formats. # Instruction by instruction memory/register changes dis- DM-COP8/20D 20 DIP DM-COP8/28D 28 DIP DM-COP8/40D 40 DIP DM-COP8/44P 44 PLCC DIP to SO Adapters played when in single step operation. COP8-DM/20D-SO 20 SO COP8-DM/28D-SO 28 SO TL/DD/11299 – 16 FIGURE 13. COP8-DM Environment 17 http://www.national.com Development Support (Continued) # Tool set integrated interactive symbolic debuggerÐsup- IceMASTER EVALUATION PROGRAMMING UNIT (EPU) ports both assembler (COFF) and C Compiler (.COD) SDK linked object formats. The iceMASTER EPU-COP880C is a PC based, in-circuit simulation tool to support the feature family COP8 products. See Figure 14 for configuration. The simulation capability is a very low cost means of evaluating the general COP8 architecture. In addition, the EPU has programming capability, with added adapters, for programming the whole COP8 product family of OTP and EPROM products. The product includes the following features: # Instruction by instruction memory/register changes displayed when in single step operation. # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Halt/Idle mode notification. Restart requires special handling. # Programming menu supports full product line of program- # Non-real-time in-circuit simulation. Program overlay mable OTP and EPROM COP8 products. Only a 40 ZIF socket is available on the EPU unit. Adapters are available for other part package configurations. memory is PC resident; instructions are downloaded over RS-232 as executed. Approximate performance is 20 kHz. # Integral wall mount power supply provides 5V and devel- # Includes a 40 pin DIP cable adapter. Other target pack- ops the required VPP to program parts. ages are not supported. All processor I/O pins are cabled to the application development environment. # Includes a copy of COP8-DEV-IBMA assembler, linker SDK. # Full 32 kbytes of loadable programming space that over- EPU Order Information lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary. Evaluation Programming Unit EPU-COP880C # On-chip timer and WATCHDOGTM execution are not well synchronized to the instruction simulation. # 100 frames of synchronous trace memory. The display can be HLL source (e.g., C source), assembly or mixed. The most recent history prior to a break is available in the trace memory. Evaluation Programming Unit with debugger and programmer control software and 40 ZIF programming socket General Programming Adapters # Up to 8 software configured break points; uses INTR in- COP8-PGMA-DS 28 and 20 DIP and SOIC adapter COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44 PLCC adapter struction which is modestly intrusive. # Common look-feel debugger software across all MetaLink productsÐonly supported features are selectable. TL/DD/11299 – 17 FIGURE 14. EPU-COP8 TooI Environment http://www.national.com 18 Development Support (Continued) CROSS REFERENCE TABLE COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT The following cross reference table lists the COP800 devices which can be emulated with the COP87XXC single-chip, form fit and function emulators. National Semiconductor offers a relocateable COP8 macro cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows: Single-Chip Emulator Selection Table # Basic and Feature Family instruction set by ‘‘device’’ type. # # # # # # # Nested macro capability. Extensive set of assembler directives. Supported on PC/DOS platform. Generates National standard COFF output files. Integrated Linker and Librarian. Device Number Package Description Emulates COP8780CV 44 PLCC One Time Programmable (OTP) COP880C COP880C COP8780CEL 44 LDCC UV Erasable Integrated utilities to generate ROM code file outputs. DUMPCOFF utility. This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. It may be ordered separately or it is bundled with the MetaLink products at no additional cost. COP8780CN 40 DIP OTP COP880C COP8780CJ 40 DIP UV Erasable COP880C COP8781CN 28 DIP OTP COP881C, COP840C, COP820C Order Information COP8781CJ 28 DIP UV Erasable COP881C, COP840C, COP820C COP8781CWM 28 SO OTP COP881C, COP840C, COP820C COP8782CN 20 DIP OTP COP842C, COP822C COP8782CJ 20 DIP UV Erasable COP842C, COP822C COP8782CWM 20 SO OTP COP842C, COP822C Assembler SDK: COP8-DEV-IBMA Assembler SDK on installable 3.5× PC/DOS Floppy Disk Drive format. Periodic upgrades and most recent version is available on National’s BBS and Internet. COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products. Features are summarized as follows: INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production. # ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application. # BITS data type extension. Register declaration Ýpragma with direct bit level definitions. # C language support for interrupt routines. # Expert system, rule based code geration and optimization. # Performs consistency checks against the architectural definitions of the target COP8 device. # Generates program memory code. # Supports linking of compiled object or COP8 assembled object formats. # Global optimization of linked code. # Symbolic debug load format fully source level supported by the MetaLink debugger. 19 http://www.national.com Development Support (Continued) Approved List Manufacturer North America Europe BP Microsystems (800) 225-2102 (713) 688-4600 Fax: (713) 688-0920 a 49-8152-4183 a 49-8856-932616 a 852-234-16611 a 852-2710-8121 Data I/O (800) 426-1045 (206) 881-6444 Fax: (206) 882-1043 a 44-0734-440011 Call North America HI-LO (510) 623-8860 Call Asia a 886-2-764-0215 Fax: a 886-2-756-6403 ICE Technology (800) 624-8949 (919) 430-7915 a 44-1226-767404 Fax: 0-1226-370-434 MetaLink (800) 638-2423 (602) 926-0797 Fax: (602) 693-0681 a 49-80 9156 96-0 Fax: a 49-80 9123 86 a 852-737-1800 Systems General (408) 263-6667 a 41-1-9450300 a 886-2-917-3005 Fax: a 886-2-911-1283 Needhams (916) 924-8037 Fax: (916) 924-8065 DIAL-A-HELPER BBS via a Standard Modem Modem: CANADA/U.S.: (800) NSC-MICRO (800) 672-6427 EUROPE: ( a 49) 0-8141-351332 AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. Baud: Set-Up: DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic. The Dial-A-Helper system provides access to an automated information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail, when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found. http://www.national.com Asia Operation: 14.4k Length: 8-Bit Parity: None Stop Bit: 1 24 Hours, 7 Days DIAL-A-HELPER via FTP ftp nscmicro.nsc.com user: anonymous password: username @ yourhost.site.domain DIAL-A-HELPER via a WorldWide Web Browser ftp://nscmicro.nsc.com National Semiconductor on the WorldWide Web See us on the WorldWide Web at: http://www.national.com 20 ERASING THE COP8780C EPROM Development Support (Continued) The EPROM program memory is erased by exposing the transparent window on the UV erasable packages to an ultraviolet light source. Erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ð to 4000Ð range. After programming, ‘‘truly opaque’’ labels should be placed over the window of the device to prevent functional failure due to the generation of photo currents, erasure and excessive HALT current. The term ‘‘truly opaque’’ needs additional clarification when used in the context of covering quartz windows on these devices. The typical white colored stickers or labels are normally used for they are easy to write on. These stickers are not opaque but translucent, they do let a certain percentage of UV-light through. The black write-protect labels supplied with 5.25× floppy disks work extremely well. If problems are encountered during programming (fails blank check) or during normal operation (intermittent functional or logical failures), need to determine first if an appropriate opaque label is being used to cover the quartz window at all times. Note that the device will also draw more current than normal (especially in HALT mode) when the window of the device is not covered with an opaque label. The recommended erasure procedure for the device is exposure to short wave ultraviolet light which has a wavelength of 2537Ð. The integrated dose (UV intensity c exposure time) for erasure should be a minimum of 30W-sec/ cm2. The device should be placed within one inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. The following table shows the minimum erasure time for various light intensities. CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National’s customer response centers. CANADA/U.S.: Tel: email: (800) 272-9959 support @ tevm2.nsc.com EUROPE: email: europe.support @ nsc.com Deutsch Tel: a 49 (0) 180-530 85 85 English Tel: a 49 (0) 180-532 78 32 Fran3ais Tel: a 49 (0) 180-532 93 58 Italiano Tel: a 49 (0) 180-534 16 80 JAPAN: Tel: a 81-043-299-2309 S.E. ASIA: Beijing Tel: ( a 86) 10-6856-8601 Shanghai Tel: ( a 86) 21-6415-4092 Hong Kong Tel: ( a 852) 2737-1600 Korea Tel: ( a 82) 2-3771-6909 Malaysia Tel: ( a 60-4) 644-9061 Singapore Tel: ( a 65) 255-2226 Taiwan Tel: a 886-2-521-3288 AUSTRALIA: Tel: ( a 61) 3-9558-9999 INDIA: Tel: ( a 91) 80-559-9467 Programming Considerations In addition to the application program, the ECON register needs to be programmed as well. The following tables provide examples of some ECON register values. For more detailed information refer to the ECON REGISTER section. Minimum Erasure Time EPROM Security Disabled RAM Memory External CKI RC Oscillator Crystal Oscillator 64 Bytes 38 30 20 128 Bytes 3A 32 22 External CKI RC Oscillator Crystal Oscillator 64 Bytes 18 10 00 128 Bytes 1A 12 02 Erasure Time* (Minutes) 15,000 10,000 8,500 36 50 60 *Does not include light intensity ramp up time. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance. Lamps lose intensity as they age. When a lamp has aged, the system should be checked to make certain that adequate UV dosages are being applied for full erasure. Common symptoms of insufficient erasure are: EPROM Security Enabled RAM Memory Light Intensity (Micro-Watts/cm2) # Inability to be programmed. # Operational malfunctions associated with VCC, tempera- EPROM programmer manufacturers may not all calculate a ‘‘checksum’’ the same way. Before implementing an inhouse verification by comparing checksums, need to ensure how each programming system utilized calculates a checksum. It is strongly recommended not to include the ECON register in the checksum for not all programmers include this byte in their calculated checksum. ture, or clock frequency. # Loss of data in program memory. # A change in configuration values in the ECON register. 21 http://www.national.com Physical Dimensions inches, (millimeters) Order Number COP8780CEL NS Package Number EL44C http://www.national.com 22 Physical Dimensions inches, (millimeters) (Continued) Order Number COP8782CJ NS Package Number J20AQ 23 http://www.national.com Physical Dimensions inches, (millimeters) (Continued) Order Number COP8781CJ NS Package Number J28AQ Order Number COP8780CJ NS Package Number J40AQ http://www.national.com 24 Physical Dimensions inches, (millimeters) (Continued) Order Number COP8782CWM NS Package Number M20B Small Outline Molded Dual-In-Line Package (WM) Order Number COP8781CWM NS Package Number M28B 25 http://www.national.com Physical Dimensions inches, (millimeters) (Continued) Order Number COP8782CN NS Package Number N20A http://www.national.com 26 Physical Dimensions inches, (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number COP8781CN NS Package Number N28B Molded Dual-In-Line Package (N) Order Number COP8780CN NS Package Number N40A 27 http://www.national.com COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller Physical Dimensions inches, (millimeters) (Continued) Plastic Leaded Chip Carrier (V) Order Number COP8780CV NS Package Number V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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