TI SN74F190A

SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
•
•
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
High-Speed fmax of 125 MHz Typical
Single Down/Up Count Control Line
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
Fully Synchronous in Count Modes
Asynchronously Presettable With Load
Control
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
B
QB
QA
CTEN
D/U
QC
QD
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
A
CLK
RCO
MAX/MIN
LOAD
C
D
description
The SN74F190A is a synchronous, 4-bit decade reversible up/down counter. Synchronous counting operation
is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the
enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the
level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.
This counter features a fully independent clock circuit. Changes at the control (CTEN and D/U) inputs that modify
the operating mode have no effect on the contents of the counter until clocking occurs. The function of the
counter is dictated solely by the condition meeting the stable setup and hold times. This counter is fully
programmable; that is, it may be preset to any number between 0 and 9 by placing a low on the load input and
entering the desired data at the data inputs. The output changes to agree with the data inputs independent of
the level of the clock input. This feature allows the counter to be used as a modulo-N divider by simply modifying
the count length with the preset inputs.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete
cycle of the clock while the count is minimum (0) counting down or maximum (9) counting up. The ripple-clock
(RCO) output produces a low-level output pulse under those same conditions, but only while the clock input is
low. The counter can easily be cascaded by feeding the ripple-clock output to the enable input of the succeeding
counter if parallel clocking is used or to the clock input if parallel enabling is used. The maximum/minimum count
(MAX/MIN) output can be used to accomplish look-ahead for high speed operation.
The SN74F190A is characterized for operation from 0°C to 70°C.
Copyright  1993, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
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2−1
SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
logic symbol†
CTEN
D/U
CLK
LOAD
A
B
C
D
4
5
14
11
15
1
G1
CTRDIV10
M2 [DOWN] 2(CT=0)Z6
3(CT=9)Z6
M3 [UP]
1,2− / 1,3+
G4
6,1,4
13
MAX/MIN
RCO
C5
[1]
5D
[2]
10
[3]
9
[4]
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2−2
12
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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3
2
6
7
QA
QB
QC
QD
SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
logic diagram(positive logic)
12
CTEN
MAX/
MIN
4
13
RCO
5
D/U
CLK
14
11
LOAD
15
A
3
S
1D
R
QA
C1
1
B
2
S
C1
1D
R
C
QB
10
6
S
QC
C1
1D
R
D
9
7
S
QD
C1
1D
R
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
2−3
SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
LOAD
A
B
Data
Inputs
C
D
CLK
D/U
CTEN
QA
QB
QC
QD
MAX/MIN
RCO
7
8
9
0
1
2
Count Up
2
2
Inhibit
Load
2−4
•
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1
0
9
Count Down
8
7
SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 30 mA to 5 mA
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input-voltage ratings may be exceeded if the input-current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
V
Input clamp current
18
mA
IOH
IOL
High-level output current
−1
mA
Low-level output current
20
mA
TA
Operating free-air temperature
70
°C
High-level input voltage
2
V
V
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = − 18 mA
IOH = − 1 mA
VCC = 4.75 V,
VCC = 4.5 V,
IOH = − 1 mA
IOL = 20 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
VCC = 5.5 V,
VI = 0.5 V
IOS§
ICC
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0
Outputs open
MIN
TYP‡
2.5
3.4
MAX
UNIT
− 1.2
V
V
2.7
0.3
0.5
V
0.1
mA
20
µA
CTEN
− 1.8
Others
− 0.6
− 60
40
mA
− 150
mA
55
mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
•
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•
2−5
SDFS026B − D3690, JULY 1990 − REVISED OCTOBER 1993
timing requirements
VCC = 5 V,
TA = 25°C
fclock
tw
tsu
th
MIN
MAX
MIN
MAX
0
90
0
90
Clock frequency
Pulse duration
Setup time
Hold time
VCC = 4.5 V to 5.5 V,
TA = MIN to MAX†
LOAD low
6
6
CLK high
4
4
CLK low
7
7
Data before LOAD↑
4
4
CTEN before CLK↑
6.5
6.5
D/U before CLK↑
15
15
LOAD inactive before CLK↑
10
10
Data after LOAD↑
2
2
CTEN after CLK↑
1
1
D/U after CLK↑
0
0
UNIT
MHz
ns
ns
ns
switching characteristics (see Note )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
TYP
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX †
MAX
90
CLK
Any Q
CLK
MAX/MIN
CLK
RCO
CTEN
RCO
D/U
RCO
D/U
MAX/MIN
A, B, C, or D
Any Q
A, B, C, or D
MAX/MIN
A, B, C, or D
RCO
LOAD
Any Q
LOAD
MAX/MIN
LOAD
RCO
MIN
2−6
•
MHz
2.5
4.8
8
2
8.5
5
7
11.5
5
12
6.5
9.4
12.5
6
13
6
8.9
11
6
12
2.5
5.2
7.5
2
8
3
4.8
7.5
2.5
8
2
5.7
7
2
7.8
3
5
7.5
3
8
8
13
16
8
17.8
4.5
8.1
10.5
4
11
4
7.9
9.8
3
11.3
3
7.5
9.5
3
10
2
4.7
7
1.5
7.5
6.5
8.9
12
6.5
13
5.5
10.5
13.6
5
15.4
6.5
10
13
6
14
6
15
18.6
6
21.1
6
9.5
13.5
6
15
4.5
7.7
9.8
4
11.4
5.5
9.9
12.1
5
13.1
5.5
12.3
15.2
5.5
17
6
11.7
14
6
15.6
8.5
16.8
19.9
8.5
23.2
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•
MAX
90
tPHL
7.5
11.6
14
7
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
UNIT
15.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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